Resistivity curves for subsurface diffused layers in silicon

World abstracts on microelectronics and reliability with higher transmission probability, which dominate the tunneling process, have been reduced by the presence of an impurity band, the tunneling current density becomes lower and hence the specific contact resistivity becomes higher for the case with the impurity band than that without the impurity band. Considering the physical properties inherent in a heavily-doped semiconductor, it is possible to explain the deviations of the experimental data from the theoretical results obtained from the conventionally used tunnneling theory for the ohmic contacts. Furthermore, by comparing the simulated results and the measured Pc data deduced from the AI and Ti contacts on both doping types of the Si-substrate, satisfactory agreements have been obtained. Resistivity curves for subsurface diffused layers in silicon. CONSTANTINBULUCEA.Solid-State Electronics, 38, 2, 367 (1995). Average resistivity curves are calculated for subsurface diffused layers in silicon using the updated resistivity-concentration data available for boron- and phosphorus-doped bulk silicon. This complements a recent paper of the author on full-depth diffused profiles, making up a complete equivalent of Irvin's original set. An improved representation format is used, which decompresses the resistivity scale and also reduces to half the total number of graphs involved in average resistivity calculations. Plasma-grown oxides on silicon with extremely low interface state densities. G. P. KENNEDY, S. TAYLOR, W. ECCLESTON and M. J. UREN. Microelectronics Journal, 25, 485 (1994). Plasma-grown oxides on silicon with midgap interface state densities less than 101 o cm 2 eV i have been obtained using low process temperatures ( < 120°C). Slow and fast interface state densities were measured over a wide frequency range by two different techniques: the quasistatic (CV) and the conductance (Gp/w)methods. Careful attention to system apparatus design, cleanliness and operation are thought to be the main factors responsible for the low interface trap densities. MOSFET degradation during substrate hot electron stress. S. P. ZHAO, S. TAYLOR and A. McPHIv. Microelectronics Journal, 25, 515 (1994). The reliability of n-channel MOSFETs during hot electron injection is studied using the SHE technique on CMOS samples. Results show the degradation dependence of the oxide bulk and interface over the field range from 0.5 to 6 MV cm t for different injection fluence levels, which has been conveniently monitored using subthreshold current measurements. A novel hot carrier reliability monitor for LDD p-MOSFETs. Y. PAN, K. K. NG and W. KWONG. Solid-State Electronics, 37, 12, 1961 (1994). The gate-edge shape of an LDD p-MOSFET exhibits large influences upon the hot carrier induced degradation and its performances. It is observed that the gate-to-drain tunneling current is strongly correlated

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to the reentrant gate oxide thickness and to the device degradation. A simple model is then constructed to provide an explanation for the observation. Under the tunneling current measurement conditions, a thicker oxide at the gate-edge leads to a weaker peak electric field in the p-LDD and to a lower gate-to-drain current. On the other hand, under the hot carrier stressing conditions, the thicker oxide decreases the oxide electric field and thus suppresses the hot electron injection. The observed correlation can be employed to monitor the process induced gate-edge (overlap) variation. 8. THICK- AND THIN-FILM COMPONENTS, HYBRID CIRCUITS AND MATERIALS Application of lead-free eutectic Sn-Ag solder in no-clean thick film electronic modules. DONGKAI SHANGGUAN, ACHYUTA ACHARI and WELLS GREEN.

IEEE Transactions on Components, Packaging, and Manufacturin 9 Technology--Part B, 17, 4, 603 (November 1994). As part of the lead-free solder development process currently underway, this paper presents the evaluation of the lead-free Sn-Ag solder for use in no-clean thick film electronics packages. The Sn-Ag (96.5/3.5 wt%) eutectic solder alloy, with a no-clean flux system, is the focus of this study. Based on studies of metallurgical interactions, the conductor/substrate adhesion, and electromigration/ dendritic growth, it is concluded that this solder has superior overall properties and is suitable for solder interconnects in thick film automotive electronics packages when used with a mined bonded Ag conductor. Fracture mechanics for thin-film adhesion. M. D. THOULESS. IBM Journal of Research and Development, 38, 4, 367 (July 1994). The essential elements of the mechanics of delamination are reviewed and their implications for design are discussed. Two important concepts for the prediction of the reliability of thin-film systems are emphasized: (1) limiting solutions for the crack-driving force that are independent of flaw size, and (2) 'mixed-mode fracture'. Consideration of the first concept highlights the possibility of flaw-tolerant design in which the statistical effects associated with flaw distributions can be eliminated. The significance of mode-mixedness includes its effect on crack trajectories and on the interface toughness, two key variables in determining failure mechanisms. Theoretical predictions are given for some cases of delamination of thin films under compressive stresses, and the results are compared with experimental observations to illustrate appropriate design criteria for the model systems studied. A vertical suhmicron SiC thin film transistor. J. D. HWANG, Y. K. FANG and T. Y. TSAI. Solid-State Electronics, 38, 2, 275 (1995). Two vertical type submicron p-channel depletion mode SiC MOSFETs have been studied. To produce the first M O S F E T a