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Resolving trapping effects by scanning microwave microscopy
Microelectronics Reliability 92 (2019) 179–181
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Resolving trapping effects by scanning microwave microscopy S. Hommel a b
a,b,⁎
a
a
a
, N. Killat , T. Schweinboeck , A. Altes , F. Kreupl
b
T
Infineon Technologies AG – Failure Analysis, Am Campeon 1-12, 85579 Neubiberg, Germany Department of Hybrid Electronic Systems, Technical University of Munich, Arcisstraße 21, 80333 Munich, Germany
ABSTRACT
Trapping effects are playing an essential role in semiconductor devices. The localization of trapping effects with a high spatial resolution can provide valuable information on the interface and oxide quality in state of the art semiconductor devices. On the example of a Si diode with suspected oxide traps, a method based on Scanning Microwave Microscopy (SMM) is shown to resolve charge carriers, which accumulate within the silicon due to trapping effects at the Si/SiO2 interface.
1. Introduction
1.1. Method and setup
Trapping effects and their influence on device performance are critical for device reliability in semiconductor applications. Ongoing miniaturization in the semiconductor industry leads to an even higher sensitivity of device characteristics on trap-related effects such as unexpected charges or unstable potentials. Techniques to improve the understanding of trapping effects and trap distribution in electronic devices are therefore essential to enhance device performance and reliability. Various established methods investigate the trapping effects in semiconductors by analyzing the electrical properties on device level. As example, capacitance voltage (CeV) curves, voltage pulse measurements, charge pumping techniques, and deep-level transient spectroscopy (DLTS) can be used to characterize the influence of traps on the device performance in great detail [1–3]. Nonetheless, these methods investigate the impact of charge trapping on the final device characteristics and can only provide, in combination with a trap model, a rough estimate of the location of traps within the device. Hence, a direct and reliable method is needed to spatially resolve trapping effects within electronic devices. Scanning microwave microscopy (SMM) has been shown to be a powerful tool to characterize charge carrier distributions in semiconductor devices with a resolution down to at least 50 nm [4–6]. This Atomic Force Microscope (AFM)-based method is ideally suited to spatially probe electrical properties in semiconductors, but is not directly sensitive to oxide or interface trap states. Since traps induce a change in charge distribution, i.e., in the local capacitance, the trapping effect may still be visualized by observing the accumulated charge carriers at the Si-side of the Si-SiO2 interface in case of interface-near oxide traps. This paper demonstrates SMM to enable the detection of trapping effects with sub-micrometer resolution by probing their accumulated charges at the semiconductor interface.
The Keysight AFM 5600 LS system was used to acquire the measurement data for this work [7]. The setup consists of an AFM, a lock-in amplifier and a network analyzer. A conductive metal tip is used to apply the electrical signals to the sample. The lock-in amplifier supports frequencies between 200 Hz and 6 MHz. The vector network analyzer is used to apply a microwave through the tip towards the sample in a frequency range from 10 MHz to 20 GHz. The backscattered part of the microwave is measured in terms of the scattering parameter S11m. The relation between the measured reflection S11m and the reflection of the actual device under test S11DUT can be described as
⁎
e
S
_ 11m
= e
_ 00
+
e
_ 10 _ 01
1
e S
_ 11 _ 11DUT
S
_ 11DUT
where e00, e01, e10 and e11 are the respective error parameters used to describe the unknown network between port and DUT [9]. The relation between the reflection S11DUT, the complex impedance Z of the DUT, and the networks characteristic impedance Z0 = 50 Ω is given by
_S11DUT =
_Z
_Z0 _Z + _Z0
The measured reflection can be calibrated into complex impedance by fitting the measured S11m data to a low frequency capacitance and solving the equations to calculate the respective error parameters. This fit introduced by Gramse et al. is calculated using a python script provided by Keysight Technologies [8]. Once the capacitive part is separated from the resistive part of the signal, the accumulation of negative carriers can be extracted from the scan with a positively biased cantilever. The accumulation of positive carriers is then given by the data acquired with the negatively biased tip. The charge carrier type can thus be
Corresponding author at: Infineon Technologies AG – Failure Analysis, Am Campeon 1-12, 85579 Neubiberg, Germany. E-mail address: [email protected] (S. Hommel).
https://doi.org/10.1016/j.microrel.2018.11.018 Received 11 September 2018; Accepted 29 November 2018 Available online 13 December 2018 0026-2714/ © 2018 Elsevier Ltd. All rights reserved.
Microelectronics Reliability 92 (2019) 179–181
S. Hommel et al.
Fig. 1. Differential Capacitance of a test sample with different levels of p- and n-type doping. Positive differential capacitance values show n-type, negative ones p-type semiconductor.
distinguished using the difference between data acquired with a positive and a negative tip bias [5]. The resulting differential capacitance shows positive values for n-type and negative values for p-type silicon. This is demonstrated on the calibration sample in Fig. 1, where the Si surface is divided in n- and p-doped stripes also varying in dopant density between 4 × 1015 atoms cm−3 and 1 × 1020 atoms cm−3. In principle, the measurement structure is a metal oxide semiconductor (MOS) structure, as illustrated in Fig. 2. It consists of the metallic tip, a native oxide layer and the investigated semiconductor. Accordingly, the positive and negative values in differential capacitance correspond to the positive or negative slope in the CeV characteristic of this MOS structure. In contrast to typical SMM applications, this work investigates the localization of traps in the oxide or the oxide interface on the example of two Si-based structures. The first example is given by the edge of a diode structure, which showed a 60% increased capacitance as a result of an electrically abnormal leakage. This hints to a conductive path at the Si/SiO2 interface. Considering trapping effects in the oxide to be a possible root cause, the accumulated electrons forming the leakage path could be caused by positively charged oxide or interface traps [11]. For comparison, a second Si-based device was investigated. The Si capacitance consisted of a pdoped Si substrate and a SiO2 layer grown using silanium oxide in a lowtemperature chemical vapor deposition (CVD) process. The oxide grown by CVD at 400 °C is known to inherit oxide traps and interface states. The trap density in CVD processes without additions, such as chlorine, typically exhibits a significantly higher trap density than thermal oxides, which Park et al. attributed to dangling Si bonds, called Pb centers [12]. A cross-section of the sample was prepared to access the corresponding sample region. The respective sample was grinded and polished to the region of interest. SMM differential capacitance measurement was employed to spatially resolve the expected electron accumulation at the Si/SiO2 interface.
Si SiO2 Fig. 3. Real part of the dS11/dV signal. The rectangle marks the Si/SiO2 interface where the “trap channel” would have been suspected.
the dS11/dV signal across the sample cross-section, similar to the dC/dV signal in SCM. Fig. 3 shows the spatial distribution of the measured dS11/dV signal in the active device region. The Si/SiO2-interface located on the right part of the image does not show any abnormality, which would, however, not confirm the suspected electron channel concluded from electrical measurements. Therefore, a more reliable SMM-based method was employed to investigate the respective sample. The SMM scan using the differential capacitance approach on the embedded cross-section of the diode structure was performed at 7 GHz, scanning each line twice, first with a tip bias of +3 V and second with a tip bias of −3 V. The capacitance data was then calculated from the acquired S11m signal, as shown in Fig. 4 for the +3 V scan. A relatively sharp cantilever tip was used to obtain an improved resolution. As the area of the MOS capacitor is mainly defined by the tip diameter, the measured capacitance was relatively small. That led to a large influence of the typical drift in the reflected microwave. In the marked region in the upper right of Fig. 4 the interface between p-doped Si and the SiO2 can be seen. Although no accumulated charges in the intentionally lowly p-doped region would be expected for
2. Results and discussion The conventional approach for charge carrier detection was to scan
Fig. 4. Capacitance data acquired at +3 V tip bias, calculated from a scan at the edge structure of the diode. The expected regions of differently doped Si are indicated by dashed lines. The solid rectangle marks the region of accumulated carriers.
Fig. 2. Schematics of the tip-sample interface as employed in SMM. Typical CeV characteristics for n- and p-type silicon including the expected effect on the semiconductor for different tip bias are shown in the overlay. 180
Microelectronics Reliability 92 (2019) 179–181
S. Hommel et al.
type. Hence, the possibility of positive charges in the silicon can be ruled out. The detected negative charge on the Si-side hints to the location of positively charged oxide traps at/near the Si/SiO2 interface, which most likely provides the driving force for the accumulation of electrons in the semiconductor. For comparison, a Si/SiO2 capacitance structure with a low-temperature oxide, known to inherit oxide and interface traps, was investigated by SMM. The differential capacitance scan of the cross-section depicted in Fig. 6 clearly resolves the electron channel in the silicon, which mirrors the trapped oxide charges at the Si-SiO2 interface. Since the low-temperature oxide investigated here is known to inherit a high trap density, the observed electron channel proves the detected accumulated charge to be caused by oxide traps. This underlines the capability of the SMM-based differential capacitance method to spatially resolve trapping effects in Si/SiO2 structures. Since this method is based on the analysis of differential capacitance, it is also applicable to other SMM-related methods such as scanning microwave impedance microscopy (sMIM) and scanning capacitance microscopy (SCM), where capacitive data is acquired. An established procedure for sMIM, e.g., enables the separation of the capacitive part of the signal from the resistive part [13]. For SCM, a similar procedure could in principle be applied to the resonance circuits raw data output. Hence, the differential capacitance method presented here provides a universal approach to study trapping effects in electric devices by different scanning techniques.
Fig. 5. Differential capacitance distribution calculated from a scan at the edge structure of the diode. Positive values correlate to n-type carriers, negative ones to p-type.
3. Conclusion By means of the example of a Si diode, SMM has proven to be a valuable method to spatially resolve charge carriers accumulated by trapping effects. The extraction of differential capacitance from SMM data has clearly identified the distribution of differently doped regions in the semiconductor. The SMM-based differential capacitance method confirmed trapping effects at the Si/SiO2 interface with low-temperature CVD-grown oxide, known for a high trap density. Consequently, the presented SMM-based method enables the spatially resolved imaging of trapped charges in semiconductor-oxide structures. In conclusion, the SMM-based method provides a way to localize trapping effects at the semiconductor-oxide interface with a high spatial resolution. The differential capacitive method presented here provides a way to study trapping effects by SMM as well as related measurement systems.
Si SiO2 Fig. 6. Differential capacitance distribution calculated from a scan at the Si/ SiO2 interface. Positive values correlate to n-type carriers, negative ones to ptype.
Acknowledgments This work has been performed in the project SAM3, where the German partners are funded by the BMBF under contract 16ES0339k and the French partners by the French Ministry for Industry and Economy. SAM3 is a joint project running in the European EUREKA EURIPIDES and CATRENE programs.
p-type, a small channel with a higher capacitance was found at the Si/ SiO2 interface. This channel hints to n-type carriers at the interface caused by process related interface traps. Still, the increased capacitance might also relate to a higher amount of p-type carriers at the Si/SiO2 interface, which would increase the depletion capacitance. In Fig. 5, the calculated differential capacitance of this SMM scan is shown, revealing the spatial distribution of the dopant type. The drift is eliminated by the subtraction of positive and negative data. The p + region on the left side of the image is clearly distinguished as well as the n + region on the lower right. The p- region in the center could not clearly be separated from undoped regions, possibly due to its low doping concentration of less than 1016 Atoms cm−3, which is close to the detection limit of SMM. In the marked area on the upper right of the sample, similarly to the initial S11m data (see Fig. 4), the expected accumulated charge appears at the interface between p-doped silicon and oxide, which forms a conductive path. The differential capacitance data clearly proves this charge, accumulated on the Si-side of the Si/SiO2 interface, to be n-
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12]
N.L. Cohen, et al., IEEE Trans. Electron Devices vol. 42, (1995) 2004–2009. H. Tahi, et al., Microelectron. Reliab. 54 (2014) 882–888. D. Vuillaume, et al., Phys. Rev. B 34 (1986) 1171–1183. T. Schweinböck, S. Hommel, Microelectron. Reliab. 54 (2014) 2070–2074. S. Hommel, et al., Microelectron. Reliab. 76-77 (2017) 218–221. E. Brinciotti, et al., Nanoscale 7 (2015) 14715–14722. P. Huber, et al., J. Appl. Phys. Vol. 111 (2012) 014301. G. Gramse, et al., Nanotechnology 25 (2014) 145703. G. Zimmer, Hochfrequenztechnik, Springer, 2000. T.R. Oldham, F.B. McLean, IEEE Trans. Nucl. Sci. vol. 50, (2003) 483–499. Y.B. Park, et al., J. Vac. Sci. Technol., B: Microelectron. Process. Phenom. 14 (1996) 2660–2666. [13] O. Amster, et al., Microelectron. Reliab. 76 (2017) 214–217.
181
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Resolving trapping effects by scanning microwave microscopy S. Hommel a b
a,b,⁎
a
a
a
, N. Killat , T. Schweinboeck , A. Altes , F. Kreupl
b
T
Infineon Technologies AG – Failure Analysis, Am Campeon 1-12, 85579 Neubiberg, Germany Department of Hybrid Electronic Systems, Technical University of Munich, Arcisstraße 21, 80333 Munich, Germany
ABSTRACT
Trapping effects are playing an essential role in semiconductor devices. The localization of trapping effects with a high spatial resolution can provide valuable information on the interface and oxide quality in state of the art semiconductor devices. On the example of a Si diode with suspected oxide traps, a method based on Scanning Microwave Microscopy (SMM) is shown to resolve charge carriers, which accumulate within the silicon due to trapping effects at the Si/SiO2 interface.
1. Introduction
1.1. Method and setup
Trapping effects and their influence on device performance are critical for device reliability in semiconductor applications. Ongoing miniaturization in the semiconductor industry leads to an even higher sensitivity of device characteristics on trap-related effects such as unexpected charges or unstable potentials. Techniques to improve the understanding of trapping effects and trap distribution in electronic devices are therefore essential to enhance device performance and reliability. Various established methods investigate the trapping effects in semiconductors by analyzing the electrical properties on device level. As example, capacitance voltage (CeV) curves, voltage pulse measurements, charge pumping techniques, and deep-level transient spectroscopy (DLTS) can be used to characterize the influence of traps on the device performance in great detail [1–3]. Nonetheless, these methods investigate the impact of charge trapping on the final device characteristics and can only provide, in combination with a trap model, a rough estimate of the location of traps within the device. Hence, a direct and reliable method is needed to spatially resolve trapping effects within electronic devices. Scanning microwave microscopy (SMM) has been shown to be a powerful tool to characterize charge carrier distributions in semiconductor devices with a resolution down to at least 50 nm [4–6]. This Atomic Force Microscope (AFM)-based method is ideally suited to spatially probe electrical properties in semiconductors, but is not directly sensitive to oxide or interface trap states. Since traps induce a change in charge distribution, i.e., in the local capacitance, the trapping effect may still be visualized by observing the accumulated charge carriers at the Si-side of the Si-SiO2 interface in case of interface-near oxide traps. This paper demonstrates SMM to enable the detection of trapping effects with sub-micrometer resolution by probing their accumulated charges at the semiconductor interface.
The Keysight AFM 5600 LS system was used to acquire the measurement data for this work [7]. The setup consists of an AFM, a lock-in amplifier and a network analyzer. A conductive metal tip is used to apply the electrical signals to the sample. The lock-in amplifier supports frequencies between 200 Hz and 6 MHz. The vector network analyzer is used to apply a microwave through the tip towards the sample in a frequency range from 10 MHz to 20 GHz. The backscattered part of the microwave is measured in terms of the scattering parameter S11m. The relation between the measured reflection S11m and the reflection of the actual device under test S11DUT can be described as
⁎
e
S
_ 11m
= e
_ 00
+
e
_ 10 _ 01
1
e S
_ 11 _ 11DUT
S
_ 11DUT
where e00, e01, e10 and e11 are the respective error parameters used to describe the unknown network between port and DUT [9]. The relation between the reflection S11DUT, the complex impedance Z of the DUT, and the networks characteristic impedance Z0 = 50 Ω is given by
_S11DUT =
_Z
_Z0 _Z + _Z0
The measured reflection can be calibrated into complex impedance by fitting the measured S11m data to a low frequency capacitance and solving the equations to calculate the respective error parameters. This fit introduced by Gramse et al. is calculated using a python script provided by Keysight Technologies [8]. Once the capacitive part is separated from the resistive part of the signal, the accumulation of negative carriers can be extracted from the scan with a positively biased cantilever. The accumulation of positive carriers is then given by the data acquired with the negatively biased tip. The charge carrier type can thus be
Corresponding author at: Infineon Technologies AG – Failure Analysis, Am Campeon 1-12, 85579 Neubiberg, Germany. E-mail address: [email protected] (S. Hommel).
https://doi.org/10.1016/j.microrel.2018.11.018 Received 11 September 2018; Accepted 29 November 2018 Available online 13 December 2018 0026-2714/ © 2018 Elsevier Ltd. All rights reserved.
Microelectronics Reliability 92 (2019) 179–181
S. Hommel et al.
Fig. 1. Differential Capacitance of a test sample with different levels of p- and n-type doping. Positive differential capacitance values show n-type, negative ones p-type semiconductor.
distinguished using the difference between data acquired with a positive and a negative tip bias [5]. The resulting differential capacitance shows positive values for n-type and negative values for p-type silicon. This is demonstrated on the calibration sample in Fig. 1, where the Si surface is divided in n- and p-doped stripes also varying in dopant density between 4 × 1015 atoms cm−3 and 1 × 1020 atoms cm−3. In principle, the measurement structure is a metal oxide semiconductor (MOS) structure, as illustrated in Fig. 2. It consists of the metallic tip, a native oxide layer and the investigated semiconductor. Accordingly, the positive and negative values in differential capacitance correspond to the positive or negative slope in the CeV characteristic of this MOS structure. In contrast to typical SMM applications, this work investigates the localization of traps in the oxide or the oxide interface on the example of two Si-based structures. The first example is given by the edge of a diode structure, which showed a 60% increased capacitance as a result of an electrically abnormal leakage. This hints to a conductive path at the Si/SiO2 interface. Considering trapping effects in the oxide to be a possible root cause, the accumulated electrons forming the leakage path could be caused by positively charged oxide or interface traps [11]. For comparison, a second Si-based device was investigated. The Si capacitance consisted of a pdoped Si substrate and a SiO2 layer grown using silanium oxide in a lowtemperature chemical vapor deposition (CVD) process. The oxide grown by CVD at 400 °C is known to inherit oxide traps and interface states. The trap density in CVD processes without additions, such as chlorine, typically exhibits a significantly higher trap density than thermal oxides, which Park et al. attributed to dangling Si bonds, called Pb centers [12]. A cross-section of the sample was prepared to access the corresponding sample region. The respective sample was grinded and polished to the region of interest. SMM differential capacitance measurement was employed to spatially resolve the expected electron accumulation at the Si/SiO2 interface.
Si SiO2 Fig. 3. Real part of the dS11/dV signal. The rectangle marks the Si/SiO2 interface where the “trap channel” would have been suspected.
the dS11/dV signal across the sample cross-section, similar to the dC/dV signal in SCM. Fig. 3 shows the spatial distribution of the measured dS11/dV signal in the active device region. The Si/SiO2-interface located on the right part of the image does not show any abnormality, which would, however, not confirm the suspected electron channel concluded from electrical measurements. Therefore, a more reliable SMM-based method was employed to investigate the respective sample. The SMM scan using the differential capacitance approach on the embedded cross-section of the diode structure was performed at 7 GHz, scanning each line twice, first with a tip bias of +3 V and second with a tip bias of −3 V. The capacitance data was then calculated from the acquired S11m signal, as shown in Fig. 4 for the +3 V scan. A relatively sharp cantilever tip was used to obtain an improved resolution. As the area of the MOS capacitor is mainly defined by the tip diameter, the measured capacitance was relatively small. That led to a large influence of the typical drift in the reflected microwave. In the marked region in the upper right of Fig. 4 the interface between p-doped Si and the SiO2 can be seen. Although no accumulated charges in the intentionally lowly p-doped region would be expected for
2. Results and discussion The conventional approach for charge carrier detection was to scan
Fig. 4. Capacitance data acquired at +3 V tip bias, calculated from a scan at the edge structure of the diode. The expected regions of differently doped Si are indicated by dashed lines. The solid rectangle marks the region of accumulated carriers.
Fig. 2. Schematics of the tip-sample interface as employed in SMM. Typical CeV characteristics for n- and p-type silicon including the expected effect on the semiconductor for different tip bias are shown in the overlay. 180
Microelectronics Reliability 92 (2019) 179–181
S. Hommel et al.
type. Hence, the possibility of positive charges in the silicon can be ruled out. The detected negative charge on the Si-side hints to the location of positively charged oxide traps at/near the Si/SiO2 interface, which most likely provides the driving force for the accumulation of electrons in the semiconductor. For comparison, a Si/SiO2 capacitance structure with a low-temperature oxide, known to inherit oxide and interface traps, was investigated by SMM. The differential capacitance scan of the cross-section depicted in Fig. 6 clearly resolves the electron channel in the silicon, which mirrors the trapped oxide charges at the Si-SiO2 interface. Since the low-temperature oxide investigated here is known to inherit a high trap density, the observed electron channel proves the detected accumulated charge to be caused by oxide traps. This underlines the capability of the SMM-based differential capacitance method to spatially resolve trapping effects in Si/SiO2 structures. Since this method is based on the analysis of differential capacitance, it is also applicable to other SMM-related methods such as scanning microwave impedance microscopy (sMIM) and scanning capacitance microscopy (SCM), where capacitive data is acquired. An established procedure for sMIM, e.g., enables the separation of the capacitive part of the signal from the resistive part [13]. For SCM, a similar procedure could in principle be applied to the resonance circuits raw data output. Hence, the differential capacitance method presented here provides a universal approach to study trapping effects in electric devices by different scanning techniques.
Fig. 5. Differential capacitance distribution calculated from a scan at the edge structure of the diode. Positive values correlate to n-type carriers, negative ones to p-type.
3. Conclusion By means of the example of a Si diode, SMM has proven to be a valuable method to spatially resolve charge carriers accumulated by trapping effects. The extraction of differential capacitance from SMM data has clearly identified the distribution of differently doped regions in the semiconductor. The SMM-based differential capacitance method confirmed trapping effects at the Si/SiO2 interface with low-temperature CVD-grown oxide, known for a high trap density. Consequently, the presented SMM-based method enables the spatially resolved imaging of trapped charges in semiconductor-oxide structures. In conclusion, the SMM-based method provides a way to localize trapping effects at the semiconductor-oxide interface with a high spatial resolution. The differential capacitive method presented here provides a way to study trapping effects by SMM as well as related measurement systems.
Si SiO2 Fig. 6. Differential capacitance distribution calculated from a scan at the Si/ SiO2 interface. Positive values correlate to n-type carriers, negative ones to ptype.
Acknowledgments This work has been performed in the project SAM3, where the German partners are funded by the BMBF under contract 16ES0339k and the French partners by the French Ministry for Industry and Economy. SAM3 is a joint project running in the European EUREKA EURIPIDES and CATRENE programs.
p-type, a small channel with a higher capacitance was found at the Si/ SiO2 interface. This channel hints to n-type carriers at the interface caused by process related interface traps. Still, the increased capacitance might also relate to a higher amount of p-type carriers at the Si/SiO2 interface, which would increase the depletion capacitance. In Fig. 5, the calculated differential capacitance of this SMM scan is shown, revealing the spatial distribution of the dopant type. The drift is eliminated by the subtraction of positive and negative data. The p + region on the left side of the image is clearly distinguished as well as the n + region on the lower right. The p- region in the center could not clearly be separated from undoped regions, possibly due to its low doping concentration of less than 1016 Atoms cm−3, which is close to the detection limit of SMM. In the marked area on the upper right of the sample, similarly to the initial S11m data (see Fig. 4), the expected accumulated charge appears at the interface between p-doped silicon and oxide, which forms a conductive path. The differential capacitance data clearly proves this charge, accumulated on the Si-side of the Si/SiO2 interface, to be n-
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12]
N.L. Cohen, et al., IEEE Trans. Electron Devices vol. 42, (1995) 2004–2009. H. Tahi, et al., Microelectron. Reliab. 54 (2014) 882–888. D. Vuillaume, et al., Phys. Rev. B 34 (1986) 1171–1183. T. Schweinböck, S. Hommel, Microelectron. Reliab. 54 (2014) 2070–2074. S. Hommel, et al., Microelectron. Reliab. 76-77 (2017) 218–221. E. Brinciotti, et al., Nanoscale 7 (2015) 14715–14722. P. Huber, et al., J. Appl. Phys. Vol. 111 (2012) 014301. G. Gramse, et al., Nanotechnology 25 (2014) 145703. G. Zimmer, Hochfrequenztechnik, Springer, 2000. T.R. Oldham, F.B. McLean, IEEE Trans. Nucl. Sci. vol. 50, (2003) 483–499. Y.B. Park, et al., J. Vac. Sci. Technol., B: Microelectron. Process. Phenom. 14 (1996) 2660–2666. [13] O. Amster, et al., Microelectron. Reliab. 76 (2017) 214–217.
181