- Email: [email protected]
Robust and efficient quantum-dot cellular automata synchronous counters
Microelectronics Journal 61 (2017) 6–14
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Robust and efficient quantum-dot cellular automata synchronous counters M.M. Abutaleb
MARK
Department of Electronics and Communications Engineering, Helwan University, Cairo, Egypt
A R T I C L E I N F O
A B S T R A C T
Keywords: Quantum-dot cellular automata Nanoelectronics Synchronous counter D-type flip-flop
The design of a synchronous sequential circuit is a very interesting and challenging research topic in quantumdot cellular automata (QCA) technology. In this paper, a robust and efficient QCA design of synchronous counters is proposed. Firstly an innovative design of level-sensitive D-type flip–flip (D-FF) and an appropriate “edge-to-level” converter are introduced by utilizing inherent capabilities of QCA implementations. Secondly these efficient elements are used for designing QCA counters with different bit sizes. Simulations using QCADesigner and QCAPro tools are performed to check performance and power of proposed designs. Results indicate the superiority of proposed designs in terms of complexity and power dissipation as compared to their latest counterparts.
1. Introduction The QCA (Quantum-dot Cellular Automata) is probably going being the foremost beneficial alternative for future high-performance integrated circuits. The QCA is body of classic cellular automata supported the mechanic quantum impact recommended in [1,2] and fabricated in [3–5]. Quantum-dots are used in this technology rather than transistors in CMOS technology for implementing circuits while the position of electrons in these dots demonstrates logic states [6]. QCA design styles have engaging options for digital circuits like further low power dissipation [7] and high operational speed (THz range) [8,9] at Nanoscale. QCA sequential circuits still attract attention in research where QCA-based designs are inherently pipelined and need clocking scheme, which is different significantly from conventional designs in CMOS technology. The sequential logic circuit can be constructed using flipflops with supplementary combinational logic circuits. In synchronous sequential circuits, all flip-flops are connected in parallel and triggered together by a single clock signal. The most important sequential circuit is a synchronous counter that is widely used in digital systems. Consequently, designing well-optimized and high-speed counters leads to higher performance for digital systems. The synchronous counter circuit can be constructed using any type of flip-flops. In QCA technology, synchronous counters have been implemented based on the JK-FF (JK-type flip-flop) as in [10–12] and based on the T-FF (Ttype flip-flop) as in [13]. Nevertheless, there is nothing to date to implement synchronous counters using the D-FF (D-type flip-flop) in QCA technology. The main aim of this work is to present low-complexity and power-
efficient QCA synchronous counters based on D-FFs. Therefore, a QCA falling-edge triggered cascaded design is proposed by employing welloptimized level-sensitive D-FFs in parallel with “edge-to-level” converter to realize synchronous counters with different bit sizes. Proposed power-efficient counters have robust QCA implementations with improvements in cell count, area and latency in comparison to earlier designs in literature. 2. Quantum-dot cellular automata In this section, the quantum-dot cellular automata (QCA) basics that will be helpful in this paper are presented. The QCA is an emerging technology that supplies logic states not as voltage levels but rather based on the situation of electrons pair [1]. There are two types of QCA cells: 90° cells as shown in Fig. 1a and 45° cells Fig. 1b. As shown in Fig. 1, the QCA cell consists of four quantum-dots that are positioned in corners of a square. There are two extra mobile electrons for each QCA cell which are allowed to tunnel together between dots inside the cell. The Columbic repulsion between two electrons makes the QCA cell as a bi-state device with a polarization (P) of −1 (binary logic 0) and +1 (binary logic 1) [14,15] as shown in Fig. 1. Two structure types of QCA wire are shown in Fig. 2. If QCA cells are located next to each other and formed a wire, the Columbic repulsion between electrons makes cells to have the same polarization as shown in Fig. 2a or opposite polarization as shown in Fig. 2b [16]. A coplanar crossover can be implemented by two types of QCA wires in one layer as shown in Fig. 3a. In QCA technology, most of circuits are designed based on majority and inverter gates. The majority gate (Maj) is implemented by five QCA
E-mail address: [email protected]. http://dx.doi.org/10.1016/j.mejo.2016.12.013 Received 28 April 2016; Received in revised form 23 December 2016; Accepted 29 December 2016 0026-2692/ © 2016 Elsevier Ltd. All rights reserved.
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 1. QCA cell: (a) 90° type, (b) 45° type.
Fig. 2. QCA wire: (a) 90° type, (b) 45° type.
Fig. 6. USE grid: (a) structure, (b) partitioned 4×4 grid.
polarized. The real computation is performed in this clock phase. In the hold phase, barriers are held high to prevent electrons tunneling and to fix the polarization of QCA cells. In release phase, barriers are lowered and then cells are completely unpolarized in relax phase [2,17]. The clocking system of QCA structures is composed of four clock zones as shown in Fig. 5b. All cells in each zone are controlled by the same QCA clock to perform a specific functionality and then serve as inputs for cells in next zone. The data is transmitted in a pipeline mechanism. The USE clocking scheme [18] is a recently proposed technique for clocking and timing of the QCA systems. It is regular and flexible enough to allow placement and routing, besides avoiding thermodynamics effects due to long wires. Moreover, its physical implementation can be fabricated using current integrated circuit fabrication technologies. The structure of USE consists of a grid of clock zones with adjacent numbers and equal sizes as shown in Fig. 6. Each square is a clock zone that contains a predefined number of QCA cells, while the arrows indicate the information flow between cells. This structure can be partitioned or extended based on the circuit size, and more information regarding the clocking circuitry can be found in [18]. For an exact operation of the QCA circuit, the synchronization of majority gates with a four-phase clock signal and optimized delay are important issues. QCA gates should be arranged in successive clocking zones and added cells may be applied to the inputs and outputs in different clock zones for circuit synchronization [16]. The closed loop should be implemented by using, at least, four clocking zones to allow the motion of the stored data through the loop cells [19]. Moreover, individual cells in the clocking zones lead to noisy QCA structures [16]. Nevertheless, if many cells are involved through a one clock zone, the clock rate and delay could descend [20]. Timing and layout issues related to QCA design rules are collected in [21,22]. All these rules give consistency and robustness for proposed QCA-based circuits.
Fig. 3. (a) Coplanar crossover technique and (b) QCA majority gate.
Fig. 4. QCA inverter.
cells as shown in Fig. 3b and its logic function can be expressed by Eq. (1). Two-input and OR gates can be implemented using three-input majority gate by setting one of majority gate inputs to constant logic value '0' and '1', respectively. The other gate in QCA is inverter gate that can be implemented using seven cells or by placing two cells in a diagonal arrangement as illustrated in Fig. 4. This gate is used to reverse the polarization of QCA cells.
Maj (A, B, C )=A. B + B. C + A. C
3. QCA D-type flip-flops
(1)
A QCA cell has four clock phases [2,17] called switch, hold, release and relax as shown in Fig. 5a. During the switch phase, potential barriers rise and input cells interact with neighbor cells into become
Several useful features can be gained by implementing sequential circuits in QCA technology such as high-speed, low-power consumption and consistency [23]. However, QCA sequential circuits still attract
Fig. 5. QCA clocking mechanism: (a) four phases of complete cycle, (b) four clock zones.
7
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
attention in literature because of their difficulties in terms of architectural complexity and synchronous mechanism. Definitely, significant parts of the sequential circuit design are flip-flops [24]. By utilizing QCA inherent capabilities, two key methods are classified for planning QCA flip-flops as line-based [25,26] and loop-based [27–34] designs. In the line-based method, data storage is performed through three clock zones wire while in the loop-based method, data storage is performed using a loop of four clock zones. In QCA technology, the loop-based design has lower complexity than the line-based design. A D-type flip-flop (D-FF) is one of most fundamental parts in the sequential circuit design. In this section, earlier presented designs of level-sensitive D-FFs will be stated. Thus after studying these designs, the QCA level-sensitive D-FF is proposed to decrease the latency by providing less clock zones in addition to decrease the area and power dissipation with using less possible number of QCA cells. Fig. 8. QCA layout of D-FF presented in [32].
3.1. Previous QCA D-type flip-flops In QCA technology, the D-FF has been implemented based on builtin wires by utilizing the clock cycles arrangement [35]. However, this technique causes the complexity in implementing sequential circuits due to timing and synchronization constraints. To reduce the effect of these constraints, the clock (CLK) signal should be entered as an external input for QCA flip-flops. Consequently, D-FF designs have been introduced and implemented in QCA technology based on this knowledge. An overview of these previous designs will be presented below. The early QCA design of level-triggered D-FF has been introduced in [24]. This design is loop-based structure and its output is sensitive to the level of clock input. The coplanar wire crossing scheme has been used in [24] to implement and optimize QCA D-FF design. The QCA layout of this design is shown in Fig. 7. On the other hand, the loopbased design of level-sensitive D-FFs in [32,33] has been implemented using 90° QCA cells without any crossover wire as shown in Figs. 8 and 9, respectively. The output of these implementations is sensitive to the positive level of input clock signal. Moreover, the level-triggered D-FF has been presented in [34] based on QCA multiplexer follows the property of loop-based design as shown in Fig. 10.
Fig. 9. QCA layout of D-FF presented in [33].
3.2. Proposed QCA D-type flip-flop A new innovative QCA design of level-sensitive D-FF is introduced here with the goal of building a high performance constructive model for implementing different sequential circuits in QCA technology, especially QCA counters in this work. The D-FF is a memory element
Fig. 10. QCA layout of D-FF presented in [34].
with two inputs (D and CLK) and an output (Q) whose graphic symbol is shown in Fig. 11a. It implements the following functionality: transparent (Q follows input D) and hold (Q remains unchanged). The logic function of the level-sensitive D-FF design can be expressed using Eq. (2). The operation of this D-FF is shown in Table 1. According to this table when the clock (CLK) signal is activated by '1', the value of data input (D) is stored in the output (Q) and when CLK signal is deactivated by ‘0’, the output is not changed. Due to the fact that majority gates are key components in designing QCA circuits, the corresponding design equation can also be represented based on majority voter gates as shown in Eq. (3).
Qt = CLK. D+CLK. Qt−1 Qt = Maj (Maj (CLK , D,′0′),
(2)
Maj (CLK , Qt−1,′0′), ′1′)
(3)
The corresponding schematic diagram of level-sensitive D-FF is illustrated in Fig. 11b. As it is shown in Fig. 11b, this design requires three majority gates connected together in two successive gate-levels. Fig. 11c depicts the first QCA layout, overlapped by a grid graph, for the proposed D-FF (DFF-I) with regular clock zones. It is implemented by
Fig. 7. QCA layout of D-FF presented in [24].
8
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 11. Proposed level-sensitive D-FF: (a) graphic symbol, (b) schematic diagram, (c) first QCA layout (DFF-I), (d) second QCA layout (DFF-II).
Table 1 Operation table of level-sensitive D-FF. CLK
D
Qt
State
0 0 1 1
0 1 0 1
Qt−1 Qt−1 0 1
Hold Transparent
using the 4×4 USE grid with a square dimension of 5×5 QCA cells. The regular clock scheme is used here as discussed in Section 2, and the square size is defined as 5×5 to avoid thermodynamic problems [18]. As shown in Fig. 11c, when the CLK signal is in high, the input bit D is transferred into the output Q and stored in the closed loop. On the other hand, when the CLK signal is in low, the stored value is preserved in the loop due to a QCA pipelined process. It consists of 74 cells in an area of 0.1 µm2 and latency of 1.5 QCA clocking cycle from input to output. In addition to this regular QCA structure, another QCA layout for the proposed level-sensitive D-FF (DFF-II) is shown in Fig. 11d. It consists of 27 cells in an area of 0.02 µm2 and latency of 0.5 QCA clocking cycle from input to output. This implementation has a robust QCA structure that is achieved by applying design rules mentioned in [16,19–22]. It is worth mentioning that the proposed structures are implemented in a single layer using 90° QCA cells without any crossover wire.
Fig. 12. Proposed falling-edge converter: (a) signals, (b) QCA layout.
phenomenon, an "edge-to-level" converter is essential to enable the edge detecting technique in the proposed D-FF. The "edge-to-level" converter is used to create a narrow pulse with each falling transition of input signal. Input and output signals of falling-edge converter are shown in Fig. 12a. The proposed "edge-to-level" converter is constructed in QCA technology and its layout is shown in Fig. 12b. This converter utilizes the inherent capability of QCA clocking zones. Obviously, an AND logic operation between the inversion value of current clock signal and its delayed version (by a one QCA clock cycle) are used to generate a narrow pulse at each negative transition (high-tolow) of input signal. This converter operates based on the operation
Table 2 Operation table of proposed falling-edge converter.
4. Proposed QCA synchronous counters In this section, a well-optimized QCA design of n-bit synchronous counter is proposed. A counter design is comprised of 'n' D-FFs and other simple combinational circuits to generate 2n ascending count states. The level-sensitive D-FF is susceptible to noise if the period of positive level is long in the clock signal. In this case, the output of D-FF would have a race-round condition [36]. In order to avoid this unstable 9
CLKin (t-1)
CLKin (t)
CLKout
0 0 1 1
0 1 0 1
0 0 1 0
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 13. Proposed 1-bit counter: (a) block diagram, (b) QCA layout.
Fig. 14. Proposed 3-bit counter: (a) block diagram, (b) QCA layout.
clock signal (CLK). Moreover, an AND gate is placed at the converter output for adding the control mechanism to the counter through the count enable (CE) terminal. As a result, the output Q0 changes to its opposite value on each CLK falling-edge when the CE signal is active high. The corresponding QCA layout is explored in Fig. 13b. The QCA layout is achieved by employing proposed level-sensitive D-FF and
table demonstrated in Table 2. The proposed level-sensitive D-FF can be used for designing 1-bit counter by attaching a falling-edge converter at the clock terminal as shown in Fig. 13a. As can be seen from Fig. 13a, a 1-bit counter can be constructed using a simple and robust D-FF (DFF-II) feeding back the inversed output value directly to the input D at each falling-edge of 10
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 15. Proposed n-bit synchronous counter.
Fig. 18. Simulation result of proposed 3-bit synchronous counter.
Table 3 Comparison of D-FF designs by conventional metrics.
Fig. 16. Simulation results of proposed D-FFs: (a) DFF-I, (b) DFF-II.
Presented in
Cell Count (# cells)
Area (µm2)
Latency (10–12 s)
[24] [32] [33] [34] Proposed DFF-I Proposed DFF-II
66 49 36 30 74 28
0.08 0.05 0.04 0.03 0.1 0.02
1.5 1 1.25 0.75 1.5 0.5
Fig. 17. Simulation result of proposed 1-bit counter. Fig. 19. Comparison of D-FF designs by QCA-specific cost function.
11
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
CE1=Q0 and CE2=Q0Q1. As a result, three outputs of D-FFs (Q2Q1Q0) counts through 000–001–010–011–100–101–110–111 (from decimal 0–7, returning 0 again). The corresponding efficient QCA layout is shown in Fig. 14b. The QCA layout is achieved by employing three level-sensitive D-FFs that are clocked by a falling-edge converter simultaneously. The proposed counter is a high-speed QCA structure where the input-to-output delay is only 2 QCA clocking cycles. Generally, n-bit synchronous counter can be implemented as shown in Fig. 15 in single-layer by involving cascade structure of 'n' levelsensitive D-FFs that are clocked in parallel using a falling-edge converter and controlled by a logical AND of previous outputs.
Table 4 Comparison of 3-bit synchronous counters by conventional metrics. Presented in
Single layer
Cell Count (# cells)
Area (µm2)
Latency (10–12 s)
[10] [11] [12] [13] Proposed Design
Yes No No Yes Yes
616 428 287 238 196
1.2 0.48 0.33 0.36 0.22
5 2 2 2.25 2
5. Results and discussion In this section, proposed QCA designs are simulated to confirm their functions and to assess the overall figures of merit such as number of QCA cells, area, latency and power dissipation. 5.1. Performance study of proposed QCA structures The QCADesigner [37] is a popular QCA layout and simulation tool developed at the University of Calgary. For QCA circuit layout and performance analyzing, all proposed QCA designs in this paper are firstly examined using both bistable approximation and coherence vector simulation engines of QCADesigner version 2.0.3 with default parameters. The simulation results of proposed level-sensitive D-FFs in Fig. 11c and d are provided with input and output waveforms as depicted in Fig. 16a and b, respectively. Based on this result, the first meaningful output waveform is gained after 1.5 clock cycle delay for DFF-I and after 0.5 clock cycle for DFF-II. Input waveform with different binary values is applied at inputs D. As is apparent, when the clock (CLK) is equal to value of '1', the value of input (D) is transmitted to the output (Q) and otherwise, the output Q is remained unchanged. Colored arrows in Fig. 16 show the input D to output Q mapping of binary data at different CLK levels. These results are verified by comparing with the theoretical result in Table 1 and show that the circuits work accurately. It can be seen that proposed structures provide a great value of polarization equal to ± 9.88e-001 at the output. The simulation result of proposed 1-bit counter in Fig. 13 is provided with input and output waveforms as depicted in Fig. 17. As shown in Fig. 17, when the clock (CLK) is altered from value of '1' to '0' and the enable (CE) is equal to value of '1', the value of output (Q) is reversed. Two arrows in Fig. 17 show the moment at which the counter starts counting where the related decimal number is presented in the top of figure. It is clear that the proposed QCA implementation works accurately and achieves a high polarization rate. Similarly, the simulation result of 3-bit synchronous counter (Fig. 14) is provided as depicted in Fig. 18. Based on this result, the first meaningful output state is gained after 2 clock cycles delay. The solid red rectangular box in this figure shows generated output states from 0 (binary 000) to 7 (binary 111). This result indicates that the proposed QCA implementation works efficiently. Then simulations are carried out to study the architectural complexity of proposed QCA structures and to compare various designs. The most widely accepted metrics in the literature are number of QCA cells, covered area and circuit latency. Table 3 shows the comparison results between QCA level-sensitive D-FFs presented in this paper and previous deigns in [24,32–34]. Regarding these results, the proposed regular QCA D-FF (DFF-I) is designed with reasonable clock zones regularity but its structure is bigger than other D-FFs. On the other hand, the proposed robust QCA D-FF (DFF-II) design surpasses previous QCA designs in terms of consumed cells, occupation area and computation delay with better polarization at the output, considerably. A new QCA-specific cost function estimation is recently proposed in [38]. The number of logic gates and wire crossings are new evaluation
Fig. 20. Cost function comparison of five QCA n-bit counters.
Table 5 Power comparison of QCA level-sensitive D-FF designs. Presented in
[24] [32] [33] [34] Proposed DFF-I Proposed DFF-II
Avg. leakage energy dissipation (meV)
Avg. switching energy dissipation (meV)
0.5 Ek
1 Ek
1.5 Ek
0.5 Ek
1 Ek
1.5 Ek
37.78 14.08 12.39 8.77 22.42
104.59 43.62 35.06 26.91 68.94
179.09 78.84 60.88 48.06 123.66
96.69 75.49 43.37 37.84 111.35
80.83 65.34 36.85 32.53 95.20
67.01 55.49 30.89 27.50 79.87
8.49
24.96
43.94
31.50
26.72
22.35
Table 6 Power analysis of proposed QCA synchronous counters. QCA design
2-bit counter 3-bit counter 4-bit counter
Avg. leakage energy dissipation (meV)
Avg. switching energy dissipation (meV)
0.5 Ek
1 Ek
1.5 Ek
0.5 Ek
1 Ek
1.5 Ek
39.10 66.65 94.71
109.67 193.40 279.28
189.91 340.45 495.42
105.95 176.56 259.67
89.08 149.95 221.56
74.37 125.90 186.51
falling-edge converter as shown by dashed rectangular boxes in Fig. 13b. The proposed 1-bit counter in Fig. 13 can be expanded for building n-bit synchronous counters. As an instance, the proposed 3-bit synchronous counter is designed as shown in Fig. 14a by employing the same building block that is depicted by a solid red rectangular box. As illustrated in Fig. 14a, this counter is implemented by cascading three level-sensitive D-FFs. It is worth to mention that to create a QCA fallingedge design, an "edge-to-level" converter is connected to the clock terminal of each D-FF. Count enable signals are evaluated as CE0=1, 12
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
6. Conclusions
metrics that are taken into account along with the QCA delay (T) in order to measure the performance of QCA designs. The equation for the cost function calculation in [38] is given at Eq. (4). The number of majority gates (M) is a better metric to measure both complexity and irreversible power dissipation. The number of inverters (I) is only associated with the complexity. The number of crossovers (C) is an important metric to evaluate both complexity and fabrication difficulty. As a multilayer crossover uses at least three single layers, the cost of a multilayer crossover is three times more than that of a coplanar crossing [38]. Consequently, the cost of a multilayer gate is also greater than that of a single-layer gate according to the number of layers.
CostQCA = (M2 + I + C 2 )xT 2
In this paper, innovative robust QCA designs of level-sensitive Dtype flip-flop (D-FF) and n-bit synchronous counter have been introduced and analyzed. The proposed designs have efficient QCA implementations in terms of complexity and power where simulations have been carried out using both QCAdesigner and QCAPro tools to estimate performance and power, respectively. The proposed QCA designs provide good opportunities to significantly improve the performance especially for designing larger power-efficient high-speed digital systems. According to the author's knowledge, this paper is the first to demonstrate the use of D-FF in design of QCA synchronous counters.
(4) References
The same D-FF designs of Table 3 are now compared by applying this metric, where the normalized QCA-specific cost results are represented in Fig. 19. As shown in this figure, the best QCA D-FF under this cost function is the proposed DFF-II design, which can be a useful module for use in more complex QCA designs. To assess overall figures of merit for the proposed n-bit synchronous counter in realistic case, a proposed QCA 3-bit counter in Fig. 14 is analyzed and compared with previously designed 3-bit counters in [10– 13]. The complexity of these counters is analyzed and compared in terms of QCA cell count, layout area and latency where corresponding estimated values are summarized in Table 4. Moreover, Fig. 20 shows the cost curves comparison of QCA counter proposed in this paper to that in [10–13] with different bit sizes. The superiority of the proposed counter design is evident by the lowest curve. It is obvious that the proposed single-layer synchronous counter has less complexity and highest performance in the QCA technology.
[1] C.S. Lent, P.D. Tougaw, W. Porod, G.H. Bernstein, Quantum cellular automata, Nanotechnology 4 (1993) 49–57. [2] C.S. Lent, P.D. Tougaw, A device architecture for computing with quantum dots, Proc. IEEE 85 (1997) 541–557. [3] M. Khatun, B. Padgett, G. Anduwan, I. Sturzu, D. Tougaw, Defect and temperature effects on complex quantum-dot cellular automata devices, J. Appl. Math. Phys. 1 (2013) 7–15. [4] K.K. Yadavalli, A.O. Orlov, K. Kummamuru, C.S. Lent, G.H. Bernstein, G.L. Snider, Fanout in quantum dot cellular automata63rd Device Research Conference Digest (DRC ‘05), Santa Barbara, CA, 2005, pp. 121–122. [5] W. Hu, K. Sarveswaran, M. Lieberman, G.H. Bernstein, High-resolution electron beam lithography and DNA nano-patterning for molecular QCA, IEEE Trans. Nanotechnol. 4 (2005) 312–316. [6] Y. Lu, C.S. Lent, Theoretical study of molecular quantum-dot cellular automata, J. Comput. Electron. 5 (2005) 115–118. [7] E.P. Blair, E. Yost, C.S. Lent, Power dissipation in clocking wires for clocked molecular quantum-dot cellular automata, J. Comput. Electron. 9 (2009) 49–55. [8] Y. Lu, M. Liu, C. Lent, Molecular quantum-dot cellular automata: from molecular structure, J. Appl. Phys. 102 (2007) 034311–034317. [9] T.J. Dysart, Modeling of electrostatic QCA wires, IEEE Trans. Nanotechnol. 12 (2013) 553–560. [10] X. Yang, L. Cai, X. Zhaho, N. Zhang, Design and simulation of sequential circuits in quantum-dot cellular automata: falling edge-triggered flip-flop and counter study, Microelectron. J. 41 (2010) 56–63. [11] S. Sheikhfaal, K. Navi, S. Angizi, A.H. Navin, Designing high speed sequential circuits by quantum-dot cellular automata: memory cell and counter study, Quant. Matter 4 (2015) 190–197. [12] S. Angizi, S. Sayedsalehi, A. Roohi, N. Bagherzadeh, K. Navi, Design and verification of new n-Bit quantum-dot synchronous counters using majority function-based JK flip-flops, J. Circuits, Syst. Comput. 24 (2015) 1550153:1‐17. [13] S. Angizi, M.H. Moaiyeri, S. Farrokhi, K. Navi, N. Bagherzadeh, Designing quantumdot cellular automata counters with energy consumption analysis, Microprocess. Microsyst. 39 (2015) 512–520. [14] C.S. Lent, M. Liu, Y. Lu, Bennett clocking of quantum dot cellular automata and the limits to binary logic scaling, Nanotechnology 17 (16) (2006) 4240–4251. [15] R. Ravichandran, S.K. Lim, M. Niemier, Automatic cell placement for quantum-dot cellular automata, Integr., VLSI J. 38 (2005) 541–548. [16] K. Kim, K. Wu, R. Karri, Quantum-dot cellular automata design guideline, IEICE Trans.trans. Fundam. Electron. Commun. Comput. Sci. 89 (2006) 1607–1614. [17] H. Cho, E.E. Swartzlander Jr., Adder and multiplier design in quantum-dot cellular automata, IEEE Trans. Comput. 58 (2009) 721–727. [18] C. Campos, A. Marciano, O.P. Vilela Neto, F. Sill Torres, Use: a universal, scalable, and efficient clocking scheme for QCA, IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. 35 (3) (2016) 513–517. [19] S.E. Frost, A.F. Rodrigues, A.W. Janiszewski, R.T. Rausch, P.M. Kogge, Memory in motion: a study of storage structures in QCA, First Workshop Non-Silicon Comput. (2002). [20] D.A. Antonelli, D.Z. Chen, T.J. Dysart, X.S. Hu, A.B. Kahng, P.M. Kogge, R.C. Murphy, M.T. Niemier, Quantum-dot cellular automata (QCA) circuit partitioning: problem modeling and solutions, 41st Des. Autom. Conf. (DAC) (2004) 363–368. [21] W. Liu, L. Lu, M. O’Neill, E.E. Swartzlander Jr., Design rules for quantum-dot cellular automata, Proc. IEEE Int. Symp. Circuits Syst. (2011) 2361–2364. [22] W. Liu, E.E. Swartzlander Jr., M. O’Neill, Design of Semiconductor QCA Systems, Artech House, USA, 2013. [23] S. Sheikhfaal, S. Angizi, S. Sarmadi, M.H. Moaiyeri, S. Sayedsalehi, Designing efficient QCA logical circuits with power dissipation analysis, Microelectron. J. 46 (2015) 462–471. [24] A. Vetteth, K. Walus, V.S. Dimitrov, and G.A. Jullien, Quantum-dot cellular automata of flip-flops, ATIPS Laboratory 2500 University Drive, NW, Calgary, Alberta, Canada, T2N 1N4, 2003. [25] V. Vankamamidi, M. Ottavi, F. Lombardi, A line-based parallel memory for QCA implementation, IEEE Trans. Nanotechnol. 4 (2005) 690–698. [26] B. Taskin, B. Hong, Improving line-based QCA memory cell design through dual phase clocking, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16 (2008) 1648–1656.
5.2. Power study of proposed structures It is worth pointing out that several studies have indicated the importance of QCA power dissipation. One of the greatest accurate power dissipation models has been presented in [39]. Results of this model have been used in [40] to estimate the upper-bound power dissipation for QCA structures. In [41], an accurate energy estimation tool named QCAPro has been developed for QCA structures. This tool separates the total energy consumption in a QCA structure to two main terms called "leakage energy" and "switching energy". Energy losses during clock transitions lead to "leakage energy" and energy losses corresponding to switching periods of cells leads to "switching energy". Based on this tool, the power dissipation is estimated in various tunneling energy levels under non-adiabatic switching and the circuit functionality is verified according to the Bayesian network analysis [41]. The power dissipation of proposed QCA D-FF designs is evaluated as well as previously designs presented in [24,32–34] using QCAPro tool. All designs are examined by considering three different tunnelingenergy levels (0.5 Ek, 1 Ek and 1.5 Ek) in 2° K temperature, and the power analysis is performed as shown in Table 5 by estimating average leakage and switching energy dissipations over all vector pairs. Based on achieved results in this table, the proposed QCA circuit of levelsensitive D-FF in Fig. 11d consumes lowest leakage and switching energies as compared to earlier QCA D-FFs. It is worth mentioning that the proposed DFF-II can be considered as low-power and low-complexity QCA design for implementing sequential circuits. Furthermore, the power of proposed QCA 2-bit, 3-bit and 4-bit synchronous counters is studied and estimated values are summarized in Table 6. According to observing results in Tables 4, 6, the proposed counter circuit has less hardware complexity with low power dissipation. Consequently, the proposed QCA synchronous counter is the best QCA design to be used in future digital systems. 13
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb [27] V. Vankamamidi, M. Ottavi, F. Lombardi, A serial memory by quantum-dot cellular automata (QCA), IEEE Trans. Comput. 57 (2008) 606–618. [28] A.S. Shamsabadi, B.S. Ghahfarokhi, K. Zamanifar, A. Vafaei, Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study, J. Syst. Archit. 55 (2009) 180–187. [29] X. Yang, L. Cai, X. Zhao, Low power dual-edge triggered flip-flop structure in quantum dot cellular automata, Electron. Lett. 46 (2010) 825–626. [30] M.A. Dehkordi, A.S. Shamsabadi, B.S. Ghahfarokhi, A. Vafaei, Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata, Microelectron. J. 42 (2011) 701–708. [31] S. Angizi, K. Navi, S. Sayedsalehi, A.H. Navin, Efficient quantum dot cellular automata memory architectures based on the new wiring approach, J. Comput. Theor. Nanosci. 11 (2014) 2318–2328. [32] S. Hashemi, K. Navi, New robust QCA D flip flop and memory structures, Microelectron. J. 43 (2012) 929–940. [33] R. Sabbaghi-Nadooshan, M. Kianpour, A novel QCA implementation of MUX-based universal shift register, J. Comput. Electron. 13 (2014) 198–210. [34] M. Goswami, B. Kumar, H. Tibrewal, S. Mazumdar, Efficient realization of digital
[35] [36] [37]
[38]
[39] [40] [41]
14
logic circuit using QCA multiplexer, IEEE 2nd Int. Conf. Bus. Inf. Manag. (ICBIM) (2014) 165–170. J. Huang, M. Momenzadeh, F. Lombardi, Design of sequential circuits by quantum dot cellular automata, Microelectron. J. 38 (2007) 525–537. P. Victor, H. Nelson, Troy Nagle, D. Bill, J. Carroll, David Irwin, Digital Logic Circuit Analysis & Design, Prentice-Hall, 1995. K. Walus, T.J. Dysart, G.A. Jullien, R.A. Budiman, QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata, IEEE Trans. Nanotechnol. 3 (2004) 26–31. W. Liu, L. Liang, M. O’Neill, E. Swartzlander, A first step towards cost functions for quantum-dot cellular automata designs, IEEE Trans. Nanotechnol. 13 (3) (2014) 476–487. J. Timler, C.S. Lent, Power gain and dissipation in quantum dot cellular automata, J. Appl. Phys. 91 (2002) 823–830. S. Srivastava, S. Sarkar, S. Bhanja, Estimation of upper bound of power dissipation in QCA circuits, IEEE Trans. Nanotechnol. 8 (2009) 116–127. S. Srivastava, A. Asthana, S. Bhanja, S. Sarkar, QCAPro-an error power estimation tool for QCA circuit design, Proc. IEEE Int. Symp. Circuits Syst. (2011) 2377–2380.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Robust and efficient quantum-dot cellular automata synchronous counters M.M. Abutaleb
MARK
Department of Electronics and Communications Engineering, Helwan University, Cairo, Egypt
A R T I C L E I N F O
A B S T R A C T
Keywords: Quantum-dot cellular automata Nanoelectronics Synchronous counter D-type flip-flop
The design of a synchronous sequential circuit is a very interesting and challenging research topic in quantumdot cellular automata (QCA) technology. In this paper, a robust and efficient QCA design of synchronous counters is proposed. Firstly an innovative design of level-sensitive D-type flip–flip (D-FF) and an appropriate “edge-to-level” converter are introduced by utilizing inherent capabilities of QCA implementations. Secondly these efficient elements are used for designing QCA counters with different bit sizes. Simulations using QCADesigner and QCAPro tools are performed to check performance and power of proposed designs. Results indicate the superiority of proposed designs in terms of complexity and power dissipation as compared to their latest counterparts.
1. Introduction The QCA (Quantum-dot Cellular Automata) is probably going being the foremost beneficial alternative for future high-performance integrated circuits. The QCA is body of classic cellular automata supported the mechanic quantum impact recommended in [1,2] and fabricated in [3–5]. Quantum-dots are used in this technology rather than transistors in CMOS technology for implementing circuits while the position of electrons in these dots demonstrates logic states [6]. QCA design styles have engaging options for digital circuits like further low power dissipation [7] and high operational speed (THz range) [8,9] at Nanoscale. QCA sequential circuits still attract attention in research where QCA-based designs are inherently pipelined and need clocking scheme, which is different significantly from conventional designs in CMOS technology. The sequential logic circuit can be constructed using flipflops with supplementary combinational logic circuits. In synchronous sequential circuits, all flip-flops are connected in parallel and triggered together by a single clock signal. The most important sequential circuit is a synchronous counter that is widely used in digital systems. Consequently, designing well-optimized and high-speed counters leads to higher performance for digital systems. The synchronous counter circuit can be constructed using any type of flip-flops. In QCA technology, synchronous counters have been implemented based on the JK-FF (JK-type flip-flop) as in [10–12] and based on the T-FF (Ttype flip-flop) as in [13]. Nevertheless, there is nothing to date to implement synchronous counters using the D-FF (D-type flip-flop) in QCA technology. The main aim of this work is to present low-complexity and power-
efficient QCA synchronous counters based on D-FFs. Therefore, a QCA falling-edge triggered cascaded design is proposed by employing welloptimized level-sensitive D-FFs in parallel with “edge-to-level” converter to realize synchronous counters with different bit sizes. Proposed power-efficient counters have robust QCA implementations with improvements in cell count, area and latency in comparison to earlier designs in literature. 2. Quantum-dot cellular automata In this section, the quantum-dot cellular automata (QCA) basics that will be helpful in this paper are presented. The QCA is an emerging technology that supplies logic states not as voltage levels but rather based on the situation of electrons pair [1]. There are two types of QCA cells: 90° cells as shown in Fig. 1a and 45° cells Fig. 1b. As shown in Fig. 1, the QCA cell consists of four quantum-dots that are positioned in corners of a square. There are two extra mobile electrons for each QCA cell which are allowed to tunnel together between dots inside the cell. The Columbic repulsion between two electrons makes the QCA cell as a bi-state device with a polarization (P) of −1 (binary logic 0) and +1 (binary logic 1) [14,15] as shown in Fig. 1. Two structure types of QCA wire are shown in Fig. 2. If QCA cells are located next to each other and formed a wire, the Columbic repulsion between electrons makes cells to have the same polarization as shown in Fig. 2a or opposite polarization as shown in Fig. 2b [16]. A coplanar crossover can be implemented by two types of QCA wires in one layer as shown in Fig. 3a. In QCA technology, most of circuits are designed based on majority and inverter gates. The majority gate (Maj) is implemented by five QCA
E-mail address: [email protected]. http://dx.doi.org/10.1016/j.mejo.2016.12.013 Received 28 April 2016; Received in revised form 23 December 2016; Accepted 29 December 2016 0026-2692/ © 2016 Elsevier Ltd. All rights reserved.
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 1. QCA cell: (a) 90° type, (b) 45° type.
Fig. 2. QCA wire: (a) 90° type, (b) 45° type.
Fig. 6. USE grid: (a) structure, (b) partitioned 4×4 grid.
polarized. The real computation is performed in this clock phase. In the hold phase, barriers are held high to prevent electrons tunneling and to fix the polarization of QCA cells. In release phase, barriers are lowered and then cells are completely unpolarized in relax phase [2,17]. The clocking system of QCA structures is composed of four clock zones as shown in Fig. 5b. All cells in each zone are controlled by the same QCA clock to perform a specific functionality and then serve as inputs for cells in next zone. The data is transmitted in a pipeline mechanism. The USE clocking scheme [18] is a recently proposed technique for clocking and timing of the QCA systems. It is regular and flexible enough to allow placement and routing, besides avoiding thermodynamics effects due to long wires. Moreover, its physical implementation can be fabricated using current integrated circuit fabrication technologies. The structure of USE consists of a grid of clock zones with adjacent numbers and equal sizes as shown in Fig. 6. Each square is a clock zone that contains a predefined number of QCA cells, while the arrows indicate the information flow between cells. This structure can be partitioned or extended based on the circuit size, and more information regarding the clocking circuitry can be found in [18]. For an exact operation of the QCA circuit, the synchronization of majority gates with a four-phase clock signal and optimized delay are important issues. QCA gates should be arranged in successive clocking zones and added cells may be applied to the inputs and outputs in different clock zones for circuit synchronization [16]. The closed loop should be implemented by using, at least, four clocking zones to allow the motion of the stored data through the loop cells [19]. Moreover, individual cells in the clocking zones lead to noisy QCA structures [16]. Nevertheless, if many cells are involved through a one clock zone, the clock rate and delay could descend [20]. Timing and layout issues related to QCA design rules are collected in [21,22]. All these rules give consistency and robustness for proposed QCA-based circuits.
Fig. 3. (a) Coplanar crossover technique and (b) QCA majority gate.
Fig. 4. QCA inverter.
cells as shown in Fig. 3b and its logic function can be expressed by Eq. (1). Two-input and OR gates can be implemented using three-input majority gate by setting one of majority gate inputs to constant logic value '0' and '1', respectively. The other gate in QCA is inverter gate that can be implemented using seven cells or by placing two cells in a diagonal arrangement as illustrated in Fig. 4. This gate is used to reverse the polarization of QCA cells.
Maj (A, B, C )=A. B + B. C + A. C
3. QCA D-type flip-flops
(1)
A QCA cell has four clock phases [2,17] called switch, hold, release and relax as shown in Fig. 5a. During the switch phase, potential barriers rise and input cells interact with neighbor cells into become
Several useful features can be gained by implementing sequential circuits in QCA technology such as high-speed, low-power consumption and consistency [23]. However, QCA sequential circuits still attract
Fig. 5. QCA clocking mechanism: (a) four phases of complete cycle, (b) four clock zones.
7
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
attention in literature because of their difficulties in terms of architectural complexity and synchronous mechanism. Definitely, significant parts of the sequential circuit design are flip-flops [24]. By utilizing QCA inherent capabilities, two key methods are classified for planning QCA flip-flops as line-based [25,26] and loop-based [27–34] designs. In the line-based method, data storage is performed through three clock zones wire while in the loop-based method, data storage is performed using a loop of four clock zones. In QCA technology, the loop-based design has lower complexity than the line-based design. A D-type flip-flop (D-FF) is one of most fundamental parts in the sequential circuit design. In this section, earlier presented designs of level-sensitive D-FFs will be stated. Thus after studying these designs, the QCA level-sensitive D-FF is proposed to decrease the latency by providing less clock zones in addition to decrease the area and power dissipation with using less possible number of QCA cells. Fig. 8. QCA layout of D-FF presented in [32].
3.1. Previous QCA D-type flip-flops In QCA technology, the D-FF has been implemented based on builtin wires by utilizing the clock cycles arrangement [35]. However, this technique causes the complexity in implementing sequential circuits due to timing and synchronization constraints. To reduce the effect of these constraints, the clock (CLK) signal should be entered as an external input for QCA flip-flops. Consequently, D-FF designs have been introduced and implemented in QCA technology based on this knowledge. An overview of these previous designs will be presented below. The early QCA design of level-triggered D-FF has been introduced in [24]. This design is loop-based structure and its output is sensitive to the level of clock input. The coplanar wire crossing scheme has been used in [24] to implement and optimize QCA D-FF design. The QCA layout of this design is shown in Fig. 7. On the other hand, the loopbased design of level-sensitive D-FFs in [32,33] has been implemented using 90° QCA cells without any crossover wire as shown in Figs. 8 and 9, respectively. The output of these implementations is sensitive to the positive level of input clock signal. Moreover, the level-triggered D-FF has been presented in [34] based on QCA multiplexer follows the property of loop-based design as shown in Fig. 10.
Fig. 9. QCA layout of D-FF presented in [33].
3.2. Proposed QCA D-type flip-flop A new innovative QCA design of level-sensitive D-FF is introduced here with the goal of building a high performance constructive model for implementing different sequential circuits in QCA technology, especially QCA counters in this work. The D-FF is a memory element
Fig. 10. QCA layout of D-FF presented in [34].
with two inputs (D and CLK) and an output (Q) whose graphic symbol is shown in Fig. 11a. It implements the following functionality: transparent (Q follows input D) and hold (Q remains unchanged). The logic function of the level-sensitive D-FF design can be expressed using Eq. (2). The operation of this D-FF is shown in Table 1. According to this table when the clock (CLK) signal is activated by '1', the value of data input (D) is stored in the output (Q) and when CLK signal is deactivated by ‘0’, the output is not changed. Due to the fact that majority gates are key components in designing QCA circuits, the corresponding design equation can also be represented based on majority voter gates as shown in Eq. (3).
Qt = CLK. D+CLK. Qt−1 Qt = Maj (Maj (CLK , D,′0′),
(2)
Maj (CLK , Qt−1,′0′), ′1′)
(3)
The corresponding schematic diagram of level-sensitive D-FF is illustrated in Fig. 11b. As it is shown in Fig. 11b, this design requires three majority gates connected together in two successive gate-levels. Fig. 11c depicts the first QCA layout, overlapped by a grid graph, for the proposed D-FF (DFF-I) with regular clock zones. It is implemented by
Fig. 7. QCA layout of D-FF presented in [24].
8
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 11. Proposed level-sensitive D-FF: (a) graphic symbol, (b) schematic diagram, (c) first QCA layout (DFF-I), (d) second QCA layout (DFF-II).
Table 1 Operation table of level-sensitive D-FF. CLK
D
Qt
State
0 0 1 1
0 1 0 1
Qt−1 Qt−1 0 1
Hold Transparent
using the 4×4 USE grid with a square dimension of 5×5 QCA cells. The regular clock scheme is used here as discussed in Section 2, and the square size is defined as 5×5 to avoid thermodynamic problems [18]. As shown in Fig. 11c, when the CLK signal is in high, the input bit D is transferred into the output Q and stored in the closed loop. On the other hand, when the CLK signal is in low, the stored value is preserved in the loop due to a QCA pipelined process. It consists of 74 cells in an area of 0.1 µm2 and latency of 1.5 QCA clocking cycle from input to output. In addition to this regular QCA structure, another QCA layout for the proposed level-sensitive D-FF (DFF-II) is shown in Fig. 11d. It consists of 27 cells in an area of 0.02 µm2 and latency of 0.5 QCA clocking cycle from input to output. This implementation has a robust QCA structure that is achieved by applying design rules mentioned in [16,19–22]. It is worth mentioning that the proposed structures are implemented in a single layer using 90° QCA cells without any crossover wire.
Fig. 12. Proposed falling-edge converter: (a) signals, (b) QCA layout.
phenomenon, an "edge-to-level" converter is essential to enable the edge detecting technique in the proposed D-FF. The "edge-to-level" converter is used to create a narrow pulse with each falling transition of input signal. Input and output signals of falling-edge converter are shown in Fig. 12a. The proposed "edge-to-level" converter is constructed in QCA technology and its layout is shown in Fig. 12b. This converter utilizes the inherent capability of QCA clocking zones. Obviously, an AND logic operation between the inversion value of current clock signal and its delayed version (by a one QCA clock cycle) are used to generate a narrow pulse at each negative transition (high-tolow) of input signal. This converter operates based on the operation
Table 2 Operation table of proposed falling-edge converter.
4. Proposed QCA synchronous counters In this section, a well-optimized QCA design of n-bit synchronous counter is proposed. A counter design is comprised of 'n' D-FFs and other simple combinational circuits to generate 2n ascending count states. The level-sensitive D-FF is susceptible to noise if the period of positive level is long in the clock signal. In this case, the output of D-FF would have a race-round condition [36]. In order to avoid this unstable 9
CLKin (t-1)
CLKin (t)
CLKout
0 0 1 1
0 1 0 1
0 0 1 0
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 13. Proposed 1-bit counter: (a) block diagram, (b) QCA layout.
Fig. 14. Proposed 3-bit counter: (a) block diagram, (b) QCA layout.
clock signal (CLK). Moreover, an AND gate is placed at the converter output for adding the control mechanism to the counter through the count enable (CE) terminal. As a result, the output Q0 changes to its opposite value on each CLK falling-edge when the CE signal is active high. The corresponding QCA layout is explored in Fig. 13b. The QCA layout is achieved by employing proposed level-sensitive D-FF and
table demonstrated in Table 2. The proposed level-sensitive D-FF can be used for designing 1-bit counter by attaching a falling-edge converter at the clock terminal as shown in Fig. 13a. As can be seen from Fig. 13a, a 1-bit counter can be constructed using a simple and robust D-FF (DFF-II) feeding back the inversed output value directly to the input D at each falling-edge of 10
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
Fig. 15. Proposed n-bit synchronous counter.
Fig. 18. Simulation result of proposed 3-bit synchronous counter.
Table 3 Comparison of D-FF designs by conventional metrics.
Fig. 16. Simulation results of proposed D-FFs: (a) DFF-I, (b) DFF-II.
Presented in
Cell Count (# cells)
Area (µm2)
Latency (10–12 s)
[24] [32] [33] [34] Proposed DFF-I Proposed DFF-II
66 49 36 30 74 28
0.08 0.05 0.04 0.03 0.1 0.02
1.5 1 1.25 0.75 1.5 0.5
Fig. 17. Simulation result of proposed 1-bit counter. Fig. 19. Comparison of D-FF designs by QCA-specific cost function.
11
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
CE1=Q0 and CE2=Q0Q1. As a result, three outputs of D-FFs (Q2Q1Q0) counts through 000–001–010–011–100–101–110–111 (from decimal 0–7, returning 0 again). The corresponding efficient QCA layout is shown in Fig. 14b. The QCA layout is achieved by employing three level-sensitive D-FFs that are clocked by a falling-edge converter simultaneously. The proposed counter is a high-speed QCA structure where the input-to-output delay is only 2 QCA clocking cycles. Generally, n-bit synchronous counter can be implemented as shown in Fig. 15 in single-layer by involving cascade structure of 'n' levelsensitive D-FFs that are clocked in parallel using a falling-edge converter and controlled by a logical AND of previous outputs.
Table 4 Comparison of 3-bit synchronous counters by conventional metrics. Presented in
Single layer
Cell Count (# cells)
Area (µm2)
Latency (10–12 s)
[10] [11] [12] [13] Proposed Design
Yes No No Yes Yes
616 428 287 238 196
1.2 0.48 0.33 0.36 0.22
5 2 2 2.25 2
5. Results and discussion In this section, proposed QCA designs are simulated to confirm their functions and to assess the overall figures of merit such as number of QCA cells, area, latency and power dissipation. 5.1. Performance study of proposed QCA structures The QCADesigner [37] is a popular QCA layout and simulation tool developed at the University of Calgary. For QCA circuit layout and performance analyzing, all proposed QCA designs in this paper are firstly examined using both bistable approximation and coherence vector simulation engines of QCADesigner version 2.0.3 with default parameters. The simulation results of proposed level-sensitive D-FFs in Fig. 11c and d are provided with input and output waveforms as depicted in Fig. 16a and b, respectively. Based on this result, the first meaningful output waveform is gained after 1.5 clock cycle delay for DFF-I and after 0.5 clock cycle for DFF-II. Input waveform with different binary values is applied at inputs D. As is apparent, when the clock (CLK) is equal to value of '1', the value of input (D) is transmitted to the output (Q) and otherwise, the output Q is remained unchanged. Colored arrows in Fig. 16 show the input D to output Q mapping of binary data at different CLK levels. These results are verified by comparing with the theoretical result in Table 1 and show that the circuits work accurately. It can be seen that proposed structures provide a great value of polarization equal to ± 9.88e-001 at the output. The simulation result of proposed 1-bit counter in Fig. 13 is provided with input and output waveforms as depicted in Fig. 17. As shown in Fig. 17, when the clock (CLK) is altered from value of '1' to '0' and the enable (CE) is equal to value of '1', the value of output (Q) is reversed. Two arrows in Fig. 17 show the moment at which the counter starts counting where the related decimal number is presented in the top of figure. It is clear that the proposed QCA implementation works accurately and achieves a high polarization rate. Similarly, the simulation result of 3-bit synchronous counter (Fig. 14) is provided as depicted in Fig. 18. Based on this result, the first meaningful output state is gained after 2 clock cycles delay. The solid red rectangular box in this figure shows generated output states from 0 (binary 000) to 7 (binary 111). This result indicates that the proposed QCA implementation works efficiently. Then simulations are carried out to study the architectural complexity of proposed QCA structures and to compare various designs. The most widely accepted metrics in the literature are number of QCA cells, covered area and circuit latency. Table 3 shows the comparison results between QCA level-sensitive D-FFs presented in this paper and previous deigns in [24,32–34]. Regarding these results, the proposed regular QCA D-FF (DFF-I) is designed with reasonable clock zones regularity but its structure is bigger than other D-FFs. On the other hand, the proposed robust QCA D-FF (DFF-II) design surpasses previous QCA designs in terms of consumed cells, occupation area and computation delay with better polarization at the output, considerably. A new QCA-specific cost function estimation is recently proposed in [38]. The number of logic gates and wire crossings are new evaluation
Fig. 20. Cost function comparison of five QCA n-bit counters.
Table 5 Power comparison of QCA level-sensitive D-FF designs. Presented in
[24] [32] [33] [34] Proposed DFF-I Proposed DFF-II
Avg. leakage energy dissipation (meV)
Avg. switching energy dissipation (meV)
0.5 Ek
1 Ek
1.5 Ek
0.5 Ek
1 Ek
1.5 Ek
37.78 14.08 12.39 8.77 22.42
104.59 43.62 35.06 26.91 68.94
179.09 78.84 60.88 48.06 123.66
96.69 75.49 43.37 37.84 111.35
80.83 65.34 36.85 32.53 95.20
67.01 55.49 30.89 27.50 79.87
8.49
24.96
43.94
31.50
26.72
22.35
Table 6 Power analysis of proposed QCA synchronous counters. QCA design
2-bit counter 3-bit counter 4-bit counter
Avg. leakage energy dissipation (meV)
Avg. switching energy dissipation (meV)
0.5 Ek
1 Ek
1.5 Ek
0.5 Ek
1 Ek
1.5 Ek
39.10 66.65 94.71
109.67 193.40 279.28
189.91 340.45 495.42
105.95 176.56 259.67
89.08 149.95 221.56
74.37 125.90 186.51
falling-edge converter as shown by dashed rectangular boxes in Fig. 13b. The proposed 1-bit counter in Fig. 13 can be expanded for building n-bit synchronous counters. As an instance, the proposed 3-bit synchronous counter is designed as shown in Fig. 14a by employing the same building block that is depicted by a solid red rectangular box. As illustrated in Fig. 14a, this counter is implemented by cascading three level-sensitive D-FFs. It is worth to mention that to create a QCA fallingedge design, an "edge-to-level" converter is connected to the clock terminal of each D-FF. Count enable signals are evaluated as CE0=1, 12
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb
6. Conclusions
metrics that are taken into account along with the QCA delay (T) in order to measure the performance of QCA designs. The equation for the cost function calculation in [38] is given at Eq. (4). The number of majority gates (M) is a better metric to measure both complexity and irreversible power dissipation. The number of inverters (I) is only associated with the complexity. The number of crossovers (C) is an important metric to evaluate both complexity and fabrication difficulty. As a multilayer crossover uses at least three single layers, the cost of a multilayer crossover is three times more than that of a coplanar crossing [38]. Consequently, the cost of a multilayer gate is also greater than that of a single-layer gate according to the number of layers.
CostQCA = (M2 + I + C 2 )xT 2
In this paper, innovative robust QCA designs of level-sensitive Dtype flip-flop (D-FF) and n-bit synchronous counter have been introduced and analyzed. The proposed designs have efficient QCA implementations in terms of complexity and power where simulations have been carried out using both QCAdesigner and QCAPro tools to estimate performance and power, respectively. The proposed QCA designs provide good opportunities to significantly improve the performance especially for designing larger power-efficient high-speed digital systems. According to the author's knowledge, this paper is the first to demonstrate the use of D-FF in design of QCA synchronous counters.
(4) References
The same D-FF designs of Table 3 are now compared by applying this metric, where the normalized QCA-specific cost results are represented in Fig. 19. As shown in this figure, the best QCA D-FF under this cost function is the proposed DFF-II design, which can be a useful module for use in more complex QCA designs. To assess overall figures of merit for the proposed n-bit synchronous counter in realistic case, a proposed QCA 3-bit counter in Fig. 14 is analyzed and compared with previously designed 3-bit counters in [10– 13]. The complexity of these counters is analyzed and compared in terms of QCA cell count, layout area and latency where corresponding estimated values are summarized in Table 4. Moreover, Fig. 20 shows the cost curves comparison of QCA counter proposed in this paper to that in [10–13] with different bit sizes. The superiority of the proposed counter design is evident by the lowest curve. It is obvious that the proposed single-layer synchronous counter has less complexity and highest performance in the QCA technology.
[1] C.S. Lent, P.D. Tougaw, W. Porod, G.H. Bernstein, Quantum cellular automata, Nanotechnology 4 (1993) 49–57. [2] C.S. Lent, P.D. Tougaw, A device architecture for computing with quantum dots, Proc. IEEE 85 (1997) 541–557. [3] M. Khatun, B. Padgett, G. Anduwan, I. Sturzu, D. Tougaw, Defect and temperature effects on complex quantum-dot cellular automata devices, J. Appl. Math. Phys. 1 (2013) 7–15. [4] K.K. Yadavalli, A.O. Orlov, K. Kummamuru, C.S. Lent, G.H. Bernstein, G.L. Snider, Fanout in quantum dot cellular automata63rd Device Research Conference Digest (DRC ‘05), Santa Barbara, CA, 2005, pp. 121–122. [5] W. Hu, K. Sarveswaran, M. Lieberman, G.H. Bernstein, High-resolution electron beam lithography and DNA nano-patterning for molecular QCA, IEEE Trans. Nanotechnol. 4 (2005) 312–316. [6] Y. Lu, C.S. Lent, Theoretical study of molecular quantum-dot cellular automata, J. Comput. Electron. 5 (2005) 115–118. [7] E.P. Blair, E. Yost, C.S. Lent, Power dissipation in clocking wires for clocked molecular quantum-dot cellular automata, J. Comput. Electron. 9 (2009) 49–55. [8] Y. Lu, M. Liu, C. Lent, Molecular quantum-dot cellular automata: from molecular structure, J. Appl. Phys. 102 (2007) 034311–034317. [9] T.J. Dysart, Modeling of electrostatic QCA wires, IEEE Trans. Nanotechnol. 12 (2013) 553–560. [10] X. Yang, L. Cai, X. Zhaho, N. Zhang, Design and simulation of sequential circuits in quantum-dot cellular automata: falling edge-triggered flip-flop and counter study, Microelectron. J. 41 (2010) 56–63. [11] S. Sheikhfaal, K. Navi, S. Angizi, A.H. Navin, Designing high speed sequential circuits by quantum-dot cellular automata: memory cell and counter study, Quant. Matter 4 (2015) 190–197. [12] S. Angizi, S. Sayedsalehi, A. Roohi, N. Bagherzadeh, K. Navi, Design and verification of new n-Bit quantum-dot synchronous counters using majority function-based JK flip-flops, J. Circuits, Syst. Comput. 24 (2015) 1550153:1‐17. [13] S. Angizi, M.H. Moaiyeri, S. Farrokhi, K. Navi, N. Bagherzadeh, Designing quantumdot cellular automata counters with energy consumption analysis, Microprocess. Microsyst. 39 (2015) 512–520. [14] C.S. Lent, M. Liu, Y. Lu, Bennett clocking of quantum dot cellular automata and the limits to binary logic scaling, Nanotechnology 17 (16) (2006) 4240–4251. [15] R. Ravichandran, S.K. Lim, M. Niemier, Automatic cell placement for quantum-dot cellular automata, Integr., VLSI J. 38 (2005) 541–548. [16] K. Kim, K. Wu, R. Karri, Quantum-dot cellular automata design guideline, IEICE Trans.trans. Fundam. Electron. Commun. Comput. Sci. 89 (2006) 1607–1614. [17] H. Cho, E.E. Swartzlander Jr., Adder and multiplier design in quantum-dot cellular automata, IEEE Trans. Comput. 58 (2009) 721–727. [18] C. Campos, A. Marciano, O.P. Vilela Neto, F. Sill Torres, Use: a universal, scalable, and efficient clocking scheme for QCA, IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. 35 (3) (2016) 513–517. [19] S.E. Frost, A.F. Rodrigues, A.W. Janiszewski, R.T. Rausch, P.M. Kogge, Memory in motion: a study of storage structures in QCA, First Workshop Non-Silicon Comput. (2002). [20] D.A. Antonelli, D.Z. Chen, T.J. Dysart, X.S. Hu, A.B. Kahng, P.M. Kogge, R.C. Murphy, M.T. Niemier, Quantum-dot cellular automata (QCA) circuit partitioning: problem modeling and solutions, 41st Des. Autom. Conf. (DAC) (2004) 363–368. [21] W. Liu, L. Lu, M. O’Neill, E.E. Swartzlander Jr., Design rules for quantum-dot cellular automata, Proc. IEEE Int. Symp. Circuits Syst. (2011) 2361–2364. [22] W. Liu, E.E. Swartzlander Jr., M. O’Neill, Design of Semiconductor QCA Systems, Artech House, USA, 2013. [23] S. Sheikhfaal, S. Angizi, S. Sarmadi, M.H. Moaiyeri, S. Sayedsalehi, Designing efficient QCA logical circuits with power dissipation analysis, Microelectron. J. 46 (2015) 462–471. [24] A. Vetteth, K. Walus, V.S. Dimitrov, and G.A. Jullien, Quantum-dot cellular automata of flip-flops, ATIPS Laboratory 2500 University Drive, NW, Calgary, Alberta, Canada, T2N 1N4, 2003. [25] V. Vankamamidi, M. Ottavi, F. Lombardi, A line-based parallel memory for QCA implementation, IEEE Trans. Nanotechnol. 4 (2005) 690–698. [26] B. Taskin, B. Hong, Improving line-based QCA memory cell design through dual phase clocking, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16 (2008) 1648–1656.
5.2. Power study of proposed structures It is worth pointing out that several studies have indicated the importance of QCA power dissipation. One of the greatest accurate power dissipation models has been presented in [39]. Results of this model have been used in [40] to estimate the upper-bound power dissipation for QCA structures. In [41], an accurate energy estimation tool named QCAPro has been developed for QCA structures. This tool separates the total energy consumption in a QCA structure to two main terms called "leakage energy" and "switching energy". Energy losses during clock transitions lead to "leakage energy" and energy losses corresponding to switching periods of cells leads to "switching energy". Based on this tool, the power dissipation is estimated in various tunneling energy levels under non-adiabatic switching and the circuit functionality is verified according to the Bayesian network analysis [41]. The power dissipation of proposed QCA D-FF designs is evaluated as well as previously designs presented in [24,32–34] using QCAPro tool. All designs are examined by considering three different tunnelingenergy levels (0.5 Ek, 1 Ek and 1.5 Ek) in 2° K temperature, and the power analysis is performed as shown in Table 5 by estimating average leakage and switching energy dissipations over all vector pairs. Based on achieved results in this table, the proposed QCA circuit of levelsensitive D-FF in Fig. 11d consumes lowest leakage and switching energies as compared to earlier QCA D-FFs. It is worth mentioning that the proposed DFF-II can be considered as low-power and low-complexity QCA design for implementing sequential circuits. Furthermore, the power of proposed QCA 2-bit, 3-bit and 4-bit synchronous counters is studied and estimated values are summarized in Table 6. According to observing results in Tables 4, 6, the proposed counter circuit has less hardware complexity with low power dissipation. Consequently, the proposed QCA synchronous counter is the best QCA design to be used in future digital systems. 13
Microelectronics Journal 61 (2017) 6–14
M.M. Abutaleb [27] V. Vankamamidi, M. Ottavi, F. Lombardi, A serial memory by quantum-dot cellular automata (QCA), IEEE Trans. Comput. 57 (2008) 606–618. [28] A.S. Shamsabadi, B.S. Ghahfarokhi, K. Zamanifar, A. Vafaei, Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study, J. Syst. Archit. 55 (2009) 180–187. [29] X. Yang, L. Cai, X. Zhao, Low power dual-edge triggered flip-flop structure in quantum dot cellular automata, Electron. Lett. 46 (2010) 825–626. [30] M.A. Dehkordi, A.S. Shamsabadi, B.S. Ghahfarokhi, A. Vafaei, Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata, Microelectron. J. 42 (2011) 701–708. [31] S. Angizi, K. Navi, S. Sayedsalehi, A.H. Navin, Efficient quantum dot cellular automata memory architectures based on the new wiring approach, J. Comput. Theor. Nanosci. 11 (2014) 2318–2328. [32] S. Hashemi, K. Navi, New robust QCA D flip flop and memory structures, Microelectron. J. 43 (2012) 929–940. [33] R. Sabbaghi-Nadooshan, M. Kianpour, A novel QCA implementation of MUX-based universal shift register, J. Comput. Electron. 13 (2014) 198–210. [34] M. Goswami, B. Kumar, H. Tibrewal, S. Mazumdar, Efficient realization of digital
[35] [36] [37]
[38]
[39] [40] [41]
14
logic circuit using QCA multiplexer, IEEE 2nd Int. Conf. Bus. Inf. Manag. (ICBIM) (2014) 165–170. J. Huang, M. Momenzadeh, F. Lombardi, Design of sequential circuits by quantum dot cellular automata, Microelectron. J. 38 (2007) 525–537. P. Victor, H. Nelson, Troy Nagle, D. Bill, J. Carroll, David Irwin, Digital Logic Circuit Analysis & Design, Prentice-Hall, 1995. K. Walus, T.J. Dysart, G.A. Jullien, R.A. Budiman, QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata, IEEE Trans. Nanotechnol. 3 (2004) 26–31. W. Liu, L. Liang, M. O’Neill, E. Swartzlander, A first step towards cost functions for quantum-dot cellular automata designs, IEEE Trans. Nanotechnol. 13 (3) (2014) 476–487. J. Timler, C.S. Lent, Power gain and dissipation in quantum dot cellular automata, J. Appl. Phys. 91 (2002) 823–830. S. Srivastava, S. Sarkar, S. Bhanja, Estimation of upper bound of power dissipation in QCA circuits, IEEE Trans. Nanotechnol. 8 (2009) 116–127. S. Srivastava, A. Asthana, S. Bhanja, S. Sarkar, QCAPro-an error power estimation tool for QCA circuit design, Proc. IEEE Int. Symp. Circuits Syst. (2011) 2377–2380.