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Safety-related systems. Competence, liability and practice
1420
World Abstracts on Microelectronics and Reliability
point becomes dominant. Most of the mathematical theoreticians have gone out of sight in a maze of abstract models and refinements far removed from the world of obtainable data. Some of our physicists are doing worthwhile work in fundamental processes, which can form the basis for engineering but does not constitute engineering. In the meantime, technical clerks grind numbers through formulas while junk continues to flow from the production lines. Are we heading for sterility, and if so can we halt the process? These are gloomy thoughts, but the intent of their publication is not to spread doubt or despair. Much remains to be done in reliability, by engineers and others. On the one hand, we are in need of advances of the kind identified recently, in these pages, by the Advanced-Techniques Committee. On the other hand, enough solid progress through application of existing techniques has been demonstrated--as in the history of spacecraft and the concurrent growth of
2. R E L I A B I L I T Y O F C O M P O N E N T S ,
Versatile COF, COB HIC technology attracts industry attention. JEE (Japan) 41 (August 1992). As electronic devices become smaller and lighter than ever, the electronic parts in them must also be smaller and lighter and ICs must be more easy to integrate into devices. To meet these requirements, Fuji Electrochemical, a hybrid IC (HIC) manufacturer, studies HICs made from materials offering advantages that are not found in the printed circuit board (PCB). This article describes chip-on-flexible board (COF) method made of direct die- or wire-bonding IC bare chips to a polyimide-base flexible board and the chip-on-board (COB) process that directly mounts bare chips on a metallic block.
A directed-graph classifier of semiconductor wafer-test patterns. MICHAELW. CRESSWELLet al. IEEE Transactions on Semiconductor Manufacturing 5(3), 255 (1992). This paper describes a technique for training an expert system for semiconductor wafer fabrication process diagnosis. The technique partitions an existing set of electrically tested semiconductor wafers into groups so that all wafers within each group have similar spatial distributions of the electrical test data across selected die sites. The spatial distribution of test data from the selected die sites on each wafer is referred to as the test pattern of that wafer. The supposition is that test patterns reflect the known processing histories of the respective wafers. A directed graph that is developed by the partitioning algorithm then efficiently classifies a new incoming wafer to one of the groups established during partitioning on the basis of its test pattern. The distribution of known processing histories of wafers within the group to which the new incoming wafer is classified provides a provisional diagnosis of the
complexity and reliability in data processing equipment--to show that real benefits from reliability engineering are possible. If we can convince our managements and customers, in Government and in the civilian economy, that support of technology advancement is not a luxury to be postponed in the hope of looser budgets, and that application of existing technology to commercial products can yield near-term payoffs, we will find that more than enough challenge remains to keep our field active and interesting for many years to come.
Safety-related systems. Competence, liability and practice. ALASDAIRKEMP. IEEE Review 350 (October 1992). Engineers are increasingly required to consider in detail the safety implications of their work. Alasdair Kemp, of the IEE's Public Affairs Board, describes the IEE's new Professional Brief on the subject.
TUBES, TRANSISTORS
A N D ICs
incoming wafer's process history. Furthermore, the way in which similar known processing histories agglomerate within particular groups enables the formulation of rules for a diagnostic expert system. Intralevel isolation test-structure data are used to illustrate the principles of the construction of the directed graph. The technique is appropriate for any available test pattern, whether it is extracted from a test structure or from a functional integrated circuit device or from both.
Reliability of commercial relays during life tests at low electrical contact load. WERNER F. RIEDER and THOMAS W. STROF. IEEE Transactions on Components, Hybrids, and ManuJacturmg Technology 15(2), 166 (1992). The influence of the electrical stress on the contact resistance behavior of several signal and power relays, respectively, has been investigated during life tests comprising 2 million operations. The results obtained with the aid of a specially developed test device showed characteristic contact resistance patterns for different electrical loads, contact materials, and designs. Under certain load conditions the contact resistance was increased by carbon deposits while both lower and higher loads caused lower contact resistance values.
A stochastic algorithm for high speed capacitance extraction in integrated circuits. Y. L. LE Coz and R. B. IVERSON. Solid-State Electronics 35(7), 1005 (1992). We present the theory of a novel stochastic algorithm for high-speed capacitance extraction in complex integrated circuits. The algorithm is most closely related to a statistical procedure for solving Laplace's equation known as the floating randomwalk method. Overall computational efficiency
World Abstracts on Microelectronics and Reliability
point becomes dominant. Most of the mathematical theoreticians have gone out of sight in a maze of abstract models and refinements far removed from the world of obtainable data. Some of our physicists are doing worthwhile work in fundamental processes, which can form the basis for engineering but does not constitute engineering. In the meantime, technical clerks grind numbers through formulas while junk continues to flow from the production lines. Are we heading for sterility, and if so can we halt the process? These are gloomy thoughts, but the intent of their publication is not to spread doubt or despair. Much remains to be done in reliability, by engineers and others. On the one hand, we are in need of advances of the kind identified recently, in these pages, by the Advanced-Techniques Committee. On the other hand, enough solid progress through application of existing techniques has been demonstrated--as in the history of spacecraft and the concurrent growth of
2. R E L I A B I L I T Y O F C O M P O N E N T S ,
Versatile COF, COB HIC technology attracts industry attention. JEE (Japan) 41 (August 1992). As electronic devices become smaller and lighter than ever, the electronic parts in them must also be smaller and lighter and ICs must be more easy to integrate into devices. To meet these requirements, Fuji Electrochemical, a hybrid IC (HIC) manufacturer, studies HICs made from materials offering advantages that are not found in the printed circuit board (PCB). This article describes chip-on-flexible board (COF) method made of direct die- or wire-bonding IC bare chips to a polyimide-base flexible board and the chip-on-board (COB) process that directly mounts bare chips on a metallic block.
A directed-graph classifier of semiconductor wafer-test patterns. MICHAELW. CRESSWELLet al. IEEE Transactions on Semiconductor Manufacturing 5(3), 255 (1992). This paper describes a technique for training an expert system for semiconductor wafer fabrication process diagnosis. The technique partitions an existing set of electrically tested semiconductor wafers into groups so that all wafers within each group have similar spatial distributions of the electrical test data across selected die sites. The spatial distribution of test data from the selected die sites on each wafer is referred to as the test pattern of that wafer. The supposition is that test patterns reflect the known processing histories of the respective wafers. A directed graph that is developed by the partitioning algorithm then efficiently classifies a new incoming wafer to one of the groups established during partitioning on the basis of its test pattern. The distribution of known processing histories of wafers within the group to which the new incoming wafer is classified provides a provisional diagnosis of the
complexity and reliability in data processing equipment--to show that real benefits from reliability engineering are possible. If we can convince our managements and customers, in Government and in the civilian economy, that support of technology advancement is not a luxury to be postponed in the hope of looser budgets, and that application of existing technology to commercial products can yield near-term payoffs, we will find that more than enough challenge remains to keep our field active and interesting for many years to come.
Safety-related systems. Competence, liability and practice. ALASDAIRKEMP. IEEE Review 350 (October 1992). Engineers are increasingly required to consider in detail the safety implications of their work. Alasdair Kemp, of the IEE's Public Affairs Board, describes the IEE's new Professional Brief on the subject.
TUBES, TRANSISTORS
A N D ICs
incoming wafer's process history. Furthermore, the way in which similar known processing histories agglomerate within particular groups enables the formulation of rules for a diagnostic expert system. Intralevel isolation test-structure data are used to illustrate the principles of the construction of the directed graph. The technique is appropriate for any available test pattern, whether it is extracted from a test structure or from a functional integrated circuit device or from both.
Reliability of commercial relays during life tests at low electrical contact load. WERNER F. RIEDER and THOMAS W. STROF. IEEE Transactions on Components, Hybrids, and ManuJacturmg Technology 15(2), 166 (1992). The influence of the electrical stress on the contact resistance behavior of several signal and power relays, respectively, has been investigated during life tests comprising 2 million operations. The results obtained with the aid of a specially developed test device showed characteristic contact resistance patterns for different electrical loads, contact materials, and designs. Under certain load conditions the contact resistance was increased by carbon deposits while both lower and higher loads caused lower contact resistance values.
A stochastic algorithm for high speed capacitance extraction in integrated circuits. Y. L. LE Coz and R. B. IVERSON. Solid-State Electronics 35(7), 1005 (1992). We present the theory of a novel stochastic algorithm for high-speed capacitance extraction in complex integrated circuits. The algorithm is most closely related to a statistical procedure for solving Laplace's equation known as the floating randomwalk method. Overall computational efficiency