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Sawing systems update
World Abstracts on Microelectronics and Reliability increased systematically to improve modelling accuracy using a concept of logical strength, which corresponds to current drive capability in analog circuits. It is shown that both the behaviour and layout of most types of MOS logic circuits, including contact, gate, and non-classical mixed circuits, can be treated in a uniform and rigorous manner using CSA network models with either four or seven logic values. The use of a digital charge-storage element called a well to represent sequential behaviour is examined. CSA theory is applied to two VLSI design issues, inverter synthesis and fault simulation. Metal migrations outside the package during accelerated life tests. PHILIPPE DUMOULIN, JEAN-PAuL SEURIN and PIERRE MARCE. IEEE Trans. Components Hybrids m[9 Technol. CHMT-5 (4), 479 (1982). Various large-scale integrated (LSI) ceramic and plastic packages are stressed through different accelerated life tests including temperature, humidity, hostile gases, and bias. Migration phenomena are observed after biased tests, with metal dendritic growth from the cathodic pins and large corrosion areas around the anodes. When no bias is applied only corrosion areas which could affect any pin are evidenced. The metals found to migrate are Ni, Cu, Sn, and Ag. The influence of hostile gases proves dominant through solubility control in the anodically corroded areas. The effect of residual contamination on the substrates is also described. Physical failure mechanisms are investigated through the accelerated tests results and data from defective components in service conditions. It appears that silver migration is the main concern and that the use of Ag package technology should be severely limited. The temperaturehumidity bias tests are more convenient to predict package life time in service conditions in order to provide a reliable quantitative evaluation. Trends in metallizatiou materials. RON ISCOFF.Semiconductor Int., 57 (October 1982). New metallization materials, including silicides of refractory metals, are winning wide interest and presenting a future challenge to aluminium--the leading interconnect material. Sawing systems update. PIETER S. BURGGRAAF.Semiconductor Int., 47 (December 1982). Dicing saws have become the premier method for separating completed ICs. Sawing is cost effective and some of today's saws are designed for integration of the assembly process through die bonding. CVD Tungsten interconnect and contact barrier technology for VLSI. NICHOLAS E. MILLER and ISRAELBEINGLASS.Solid St. Technol., 85 (December 1982). The use of chemical vapour deposited (CVD) tungsten in VLSI device fabrication is discussed. Applications include the use of CVD tungsten to fulfil the need for contact barriers that reduce contact resistance and protect shallow junctions from aluminium spike-induced failures. Also discussed are the applications of CVD tungsten as a sheet resistance-reducing shunt material for polysilicon gate and diffusion lines and as an alternative metallization material. Deposition process details, which are different for each application, are described. Plasma etching of aluminium: review of process and equipment technology. AARON WEISS. Semiconductor Int., 69 (October 1982). Since 1980 plasma etching of aluminium has been the subject of intense activity on the part of semiconductor houses and system manufacturers. Their efforts have resulted in significant improvements in plasma techniques for etching aluminium.
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , A CMOS process for VLSI instrumentation. TONG QIN YI and J. M. ROBERTSON.Microelectron. J. 13 (6), 29 (1982). An N-well CMOS process has been developed which can be combined with N M O S to provide a wider design choice for
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Mix-and-match of 10 : 1 wafer steppers with die-by-die alignment to 1 : 1 proximity and projection systems. H. L. STOVER, N. E. DAVID and T. H. LEWIS. Solid St. Technol., 124 (October 1982). The use of automatic die-by-die alignment to overlay 10 : 1 wafer-stepper images on patterns delineated by 1 : 1 proximity and projection systems is discussed. The motivation for these programs arises from considerations of cost-effectiveness and productivity while upgrading existing IC Cab lines. 1 : I lithographic systems already in place can be used to generate non-critical layers, while the wafer steppers can be used to align and delineate the patterns of critical layers. Excellent intra-die overlay match is demonstrated, mixing with some of the more prevalent 1 : 1 systems. Practical issues relating to net wafer throughput are also illuminated. Can velocity overshoot or ballistic transport be efficient in submicron devices? INSTITUT D'ELECTRONIQUE FONDAMENTALE. Microelectron. J. 13 (6), 18 (1982). Increasing electronic device speed implies the reduction of control region length. Velocity overshoot and quasi-ballistic transport are present in submicron structures, and some considerations about the advantage which can be taken from these effects are discussed. Creating the integrated engineering design office. HARVEY JONES. Microelectron. J. 13 (6), 15 (1982). In the design of VLSI devices, there is a proliferation of computer aids. The problem is that interfaces between them are largely nonexistent. The Daisy Logician is an attempt to provide a unified data base in an intelligent workstation which can access software at various locations and to integrate the analysis and simulation stages in the design process. Linewidth measurement on IC masks by diffraction from grating test patterns. W. A. BOSENBERG and H. P. KLEINKNECHT. Solid St. Technol., 110 (October 1982). As linewidths of integrated circuits approach the wavelength of light, diffraction effects cause more and more problems. In this series of two articles, diffraction effects are used to good advantage. A red helium/neon laser beam illuminates a properly designed grating test pattern and creates diffracted beams of many orders. The angular locations of the beams depend on the grating period. The intensities in the various beams are complicated functions of linewidth, thickness of transparent layers, step height and edge profile. In the case of a grating of rectangular shape the linewidth can be calculated from the ratio of the second order beam and first order beam intensities. This linewidth measuring technique is applied to IC masks. Isolation techniques for very large scale integration. D. BEERNAERT.G. SCHOLSand P. VAN ISEGHEM.Electl Commun. 57 (2), 161 (1982). Isolation techniques for VLSI are pushing the limits of materials technology for high speed, high density devices, and high voltage applications. A notation for designing restoring logic circuitry in CMOS. MARTIN REM and CARVER MEAD. Microelectron. J. 13 (6), 5 (1982). A program notation is introduced together with a technique for translating programs in that notation into transistor diagrams for CMOS integrated circuits. A number of restrictions are imposed on the programs ensuring every circuit thus obtained to be restoring. The program notation caters to hierarchical design. It is shown how the observance of the restrictions can be checked for each level of the hierarchy separately. The techniques discussed in this paper may be viewed as a modest step towards silicon compilation.
SYSTEMS
AND
EQUIPMENTS
instrumentation applications which require both analogue and digital circuits. This paper outlines the CMOS process and shows how it can be used to implement analogue circuits and small geometry structures.
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , A CMOS process for VLSI instrumentation. TONG QIN YI and J. M. ROBERTSON.Microelectron. J. 13 (6), 29 (1982). An N-well CMOS process has been developed which can be combined with N M O S to provide a wider design choice for
999
Mix-and-match of 10 : 1 wafer steppers with die-by-die alignment to 1 : 1 proximity and projection systems. H. L. STOVER, N. E. DAVID and T. H. LEWIS. Solid St. Technol., 124 (October 1982). The use of automatic die-by-die alignment to overlay 10 : 1 wafer-stepper images on patterns delineated by 1 : 1 proximity and projection systems is discussed. The motivation for these programs arises from considerations of cost-effectiveness and productivity while upgrading existing IC Cab lines. 1 : I lithographic systems already in place can be used to generate non-critical layers, while the wafer steppers can be used to align and delineate the patterns of critical layers. Excellent intra-die overlay match is demonstrated, mixing with some of the more prevalent 1 : 1 systems. Practical issues relating to net wafer throughput are also illuminated. Can velocity overshoot or ballistic transport be efficient in submicron devices? INSTITUT D'ELECTRONIQUE FONDAMENTALE. Microelectron. J. 13 (6), 18 (1982). Increasing electronic device speed implies the reduction of control region length. Velocity overshoot and quasi-ballistic transport are present in submicron structures, and some considerations about the advantage which can be taken from these effects are discussed. Creating the integrated engineering design office. HARVEY JONES. Microelectron. J. 13 (6), 15 (1982). In the design of VLSI devices, there is a proliferation of computer aids. The problem is that interfaces between them are largely nonexistent. The Daisy Logician is an attempt to provide a unified data base in an intelligent workstation which can access software at various locations and to integrate the analysis and simulation stages in the design process. Linewidth measurement on IC masks by diffraction from grating test patterns. W. A. BOSENBERG and H. P. KLEINKNECHT. Solid St. Technol., 110 (October 1982). As linewidths of integrated circuits approach the wavelength of light, diffraction effects cause more and more problems. In this series of two articles, diffraction effects are used to good advantage. A red helium/neon laser beam illuminates a properly designed grating test pattern and creates diffracted beams of many orders. The angular locations of the beams depend on the grating period. The intensities in the various beams are complicated functions of linewidth, thickness of transparent layers, step height and edge profile. In the case of a grating of rectangular shape the linewidth can be calculated from the ratio of the second order beam and first order beam intensities. This linewidth measuring technique is applied to IC masks. Isolation techniques for very large scale integration. D. BEERNAERT.G. SCHOLSand P. VAN ISEGHEM.Electl Commun. 57 (2), 161 (1982). Isolation techniques for VLSI are pushing the limits of materials technology for high speed, high density devices, and high voltage applications. A notation for designing restoring logic circuitry in CMOS. MARTIN REM and CARVER MEAD. Microelectron. J. 13 (6), 5 (1982). A program notation is introduced together with a technique for translating programs in that notation into transistor diagrams for CMOS integrated circuits. A number of restrictions are imposed on the programs ensuring every circuit thus obtained to be restoring. The program notation caters to hierarchical design. It is shown how the observance of the restrictions can be checked for each level of the hierarchy separately. The techniques discussed in this paper may be viewed as a modest step towards silicon compilation.
SYSTEMS
AND
EQUIPMENTS
instrumentation applications which require both analogue and digital circuits. This paper outlines the CMOS process and shows how it can be used to implement analogue circuits and small geometry structures.