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Scaling aspects for different CMOS circuit designs due to transient latch-up effects
Scaling aspects for different CMOS circuit designs due to transient latch-up effects* W. Reczek, F. Bonner and B. Murphy Siemens AG, Components Group, Otto-Hahn-Ring 6, D-8000 Munich 83, F.R.G.
The influence of three different scaling concepts: constant field (CE); constant voltage (CV); and compaction shrink (CS) on the latch-up behaviour of CMOS circuits is examined in detail for each of three circuit design methods: (1) floating well concept with substrate-bias (VBB) generator; (2) conventional LOGIC with grounded p-substrate and n-well connected to VCC; and (3) DRAM/LOGIC with VBB generator and n-well connected to VCC. Scaling results in increased power-on latch-up susceptibility for circuits with VBB generators. This risk can only be reduced by the use of protection circuits which limit the internal power supply ramp rate. Latch-up susceptibility to pulses (e.g. overshoot, undershoot and glitches) is increased for each circuit type as a result of scaling and can only be reduced by the use of novel device structures or by new and better developed technologies. For example, a highly doped substrate with a box isolation may be used, where the trench reaches far into the highly-doped region. The results presented are valid for both p-well and n-well concepts as the mechanism which initiates transient latch-up is independent of the well concept used.
1. Introduction In recent years, the effects of different scaling concepts on MOS device dimensions, on packing density, on performance as well as on the proper choice of well concept have been studied extensively [I-5]. Table 1 shows the impact of constant field (CE), constant voltage (CV) and compaction shrink (CS) on the most important parameters: device dimensions (gate oxide thickness, To~d~,channel length, L, channel width, W), impurity concentration, supply voltage, device current, capacitance, RC delay, power per element and line resistance. For the CE concept, supply voltage and current are reduced by a factor 1/k. This appears to be the best way to scale down device dimensions but is in conflict with established user power supply standards. The question arises as to whether on-chip voltage reduction should be used or if a new voltage standard at board level (e.g. 3.3 V) should be adopted. The second scaling concept (CV) can result in the problem of hot carrier generation. Hot electrons have up until now played the most important role. In the deep submicron region, however, hot holes seem to be the biggest problem. • An earlier version of this paper was presented at MIEL "89. Nig. Yugosla~4a. May 9-1 I. 1989
MICROELECTRONICS JOURNAL Vol. 21 No. 3 © 1990 Elsevier Science Publishers Ltd., England
15
16
W. Reczek. F. Bonner and B. Murphy
TABLE 1 CMOS scaling (k>l) for CE, CV and CS Parameter
CE factor
CV factor
CS factor
ToxiJ~, L, W
l/k
1/k
l/k
k
k
1
Voltage
1/k
1
1
Current
l/k
I
1/k
Capacitance
1/k
l/k
l/k
Delay
1/k
l/k
1
Power/element
1/k-'
1
1/k
Line resistance
k
k
k
Doping concentration
Toxid e a n d L = c o n s t a n t
The third scaling concept (CS) is a tradeoffbetween these two scaling concepts, orientated towards industrial requirements. The impact of different scaling trends on static latch-up behaviour has been much discussed [6]. No attempt has been made, however, to describe the effects of different scaling concepts on transient latch-up susceptibility, which is the subject of this paper. The basis for investigation is an n-well CMOS technology. The results presented and conclusions drawn are valid for both n-well and p-well concepts as the mechanism which initiates latch-up is independent of the well concept used.
2. Power-on latch-up As a CMOS circuit is supplied with VCC, the substrate/well depletion zone is established. Majority carriers then flow to their respective contacts, i.e. electrons in the n-well flow to the n-well contact and holes in the p-substrate flow to the psubstrate contact. This leads to an ohmic voltage drop which causes forward biasing of the p-n junctions and consequent latch-up if this forward-bias is large enough. Majority carrier current resulting from the charging of capacitances in the environment of the latch-up path must also be considered for the triggering of latch-up. At power-on the rise time, At, of the supply voltage, AV, is the critical parameter in determining whether a critical forward-bias level for the initiation of latch-up is reached [7]. M a n y actual circuit designs have severe problems at ramp rates equal to or greater than 1 V ps -j. Such ramp rates are often achieved even at board level. Table 2 shows the effect scaling will have on the future critical rise time. Figures 1 3 show the equivalent circuits for each circuit design method used and the relevant parameters are given in Table 3.
Scaling aspects lbr difl'erent CMOS circuit designs due to transient latch-up effects
17
TABLE 2 Allowable rise-time of the supply voltage due to power-on latch-up (k> 1)
Circuit/design method
CE
CV
CS
Case I*
1
v/k
1
Base charge
Case 2**
1/k 2
1/k t~
l/k
Well capacitance
Case 3*** DRAM area shrink
Relevant parameter
Cell plate capacitance
k2
DRAM kc more cells
k'. kc
LOGIC area shrink LOGIC km more devices
1
v/k
1
km
km. v/k
km
Peripheral capacitance, without V~ transition to case 2
*Floating well concept with VBB generalor. **Conventional LOGIC v,ith grounded p-substrale and n-well connected to VDD. ***DRAM/LOGIC with VBB generator and n-well connected to VDI).
&VoD/&t
Cw
~
pn
Q8
Qc
np
Vss V 2Ss , So . A 2 • q" Nd" V QC = Nd (1 + -~a ) QB
=
q " AE
" NB
"
WB
Fig. 1 Power-on latch-up: equivalent circuit for the floating well concept with VBB generator
18
W. Reczetc F. Bonner and B. Murphy
&Voo/At
&Voo/&t
~Rw?
t ~np
tRw
Vss
Vss
(1 ÷ ~ =Cw(Rw+ Rs) Fig. 2 Power-on latch-up" equivalent circuit for conventional LOGIC circuits
AVoo/At
o
AVoo/At
_
RSl
=. I]la KI
Yea
C_
Vss
Idlso~ AM
Vs,,
VBEven . __1
81at~-(. L. /2
QB = q ' AE ' N8 ' WB Fig. 3 Power-on latch-up: equivalent circuit for DRAMs/LOGIC with VBB generator
2.1 CMOS with VBB generator and floating well Since the on-chip substrate-bias (VBB) generator only works after a time delay of some microseconds, the substrate is floating during this time, resulting in a substrate resistance that is close to infinity [7]. The equivalent circuit for the case of power-on is shown in Fig. 1. The lumped element model is similar to the conventional equivalent circuit of a silicon controlled rectifier [8], consisting only of the
Scaling aspects for different CMOS circuit designs due to transient latch-up effects
19
TABLE 3 List of parameters
CW
C+ C_ CvBa
Rs, Rs2 Rvaa Rw V VBElal VBEverl
Vaa VBBO
Vt~o Vss Qs Qc Idiso
A AE WB
q £s " £o
N~ N~ NB t n
D
13 "{7B
Substrate well capacitance Coupling capacitance [7] Buffering capacitance between VSS and VBB [7] VBB generator capacitance Substrate shunt resistance Distributed resistances in the substrate [7] Internal resistance of the VBB generator (also called R,) Well shunt resistance Corresponds to a voltage Base emitter voltage of the lateral bipolar transistor Base emitter voltage of the vertical bipolar transistor Back bias substrate voltage Internally generated voltage of the VBB generator Positive supply voltage Negative supply voltage (ground) Base charge of one of the parasitic bipolar transistors Charge stored at the substrate well junction [8] Displacement current Area of the substrate well junction Corresponding emitter area (e.g. n + or p+ diffusion in the substrate and well, respectively) Base width of the corresponding parasitic bipolar transistor Elementary charge Dielectric constant Impurity concentration of the substrate Impurity concentration of the well Impurity concentration of the corresponding base (e.g. substrate=lateral and well = vertical) Diffusion length of the (electron) minorities in the p-substrate Diffusion constant Current gain (e.g. 13,.,of the lateral bipolar transistor) Base transmit time of the corresponding bipolar transistor
vertical and lateral parasitic bipolar transistors and the substrate well capacitance, Cw. The relevant parameters for latch-up are the base charge, Qa, of one of the bipolar transistors and the charge, Qc, established on the substrate well capacitance, Cw (see Fig. 1). Any change in the relationship Of QB to Qc is critical in evaluating the impact of the different scaling concepts.
20
W. Reczek. F. Bonner and B. Murphy
For CE and CS the ratio of Q~ to Qc stays constant and the critical ramp rate of VCC is not affected. In the case of CV the ratio of QB to Qc increases by a factor of v/k. The rise time of the constant supply voltage, V, must then be increased by the same factor to avoid latch-up.
2.2 Conventional CMOS For conventional LOGIC circuits the substrate and the well are connected to VSS and VCC, respectively. Figure 2 shows the complete equivalent lumped element model as well as the simplified circuit, which consists only of a simple series RC network, comprising substrate and well shunt resistances Rs and Rw, and substrate well capacitance, Cw. The bipolar transistors may be neglected providing the forward bias of the base emitter junction is less than 0.7 V. With the ramp rate, AV/ At, as stimulus, expressions for the base emitter voltages of the parasitic bipolar transistors can be calculated (see Fig. 2). R s, Rw and Cw are shown to be the important parameters. For all three scaling concepts the resistances Rs and Rw stay the same to a first order approximation. In the case ofCE, Cw and V are reduced by a factor of 1/k resulting in an increase (relaxation) of the critical ramp rate by a factor of k2. For the case ofCV, V stays constant but Cw is reduced by l/k L5so that the critical ramp rate is increased by a factor of k LS. Using the CS method Cw is reduced by 1/k and V remains constant. The critical ramp rate is then increased by just a factor of K.
2.3 CMOS with VBB generator and conventional well contacts Circuits are considered with on-chip VBB generators and large capacitances in the periphery or environment of the functional unit latch-up path, as in the case of DRAMs. The equivalent circuit is shown in Fig. 3. The standard latch-up lumped element model is enhanced by the coupling capacitances, C+ (cell plate capacitance, and all other capacitance in the periphery tied between VBB and VSS), the buffering capacitance, C_ (capacitance between VSS and VBB) and the VBB generator. Furthermore the substrate resistance must be divided into two separate parts, Rs~ and Rs2, because of the VBB generator [7]. The circuit may then be re-simplified, to consist only ofRw, Rs, the large C+ (the ratio C+ :C_ = 20:1 in the case of a 1 Mbit DRAM) and the lateral bipolar transistor. The vertical bipolar transistor may be neglected because the base emitter voltage of 0.7 V at the vertical bipolar transistor is taken as the indicator for latch-up. The important parameters are [3~,,,of the lateral bipolar transistor and, more importantly, C+. As the capacitance per cell unit has to stay the same for soft error reasons, the ramp rate has to be reduced by a factor of k2. This slowing of the VCC ramp-rate can only be achieved through the use of power-on protection circuits [7]. A summary of the previous results is shown in Table 2. While for conventional LOGIC (Table 2, case 2) the risk of power-on latch-up is reduced, there is signifi-
Scaling aspects/or dillbrent CMOS circuit designs due to transient latch-up elTects
21
cant risk for all circuits with VBB generators. In particular, severe problems will arise for DRAMs, where the cell capacitance is the major reason for increased latch-up susceptibility. The internal ramp rate has to be reduced by the second power of the scaling factor (k> 1). This is achieved by the use of internal power-on protection circuits which limit the internal ramp rate [7]. The use of a highly doped substrate with an epilayer does not reduce the problem because the power-on latch-up susceptibility of circuits with an epilayer is at least twice that of circuits based on bulk material. One of the reasons for this increased latch-up susceptibility is the increased current gain of the lateral bipolar transistor [7].
3. Latch-up due to pulses
Figures 4 - 6 show the equivalent circuits for each circuit design method. Substrate triggering (forward biasing of the n ÷ p-substrate junction) is only possible in the case of conventional logic circuits [9]. In all cases (forward biasing of the p÷ nwell junction included), the increased latch-up susceptibility to pulses (e.g. overshoot, undershoot and glitches) is not only due to the reduction of the base charge, QB, but also to the reduction in base transit times of the parasitic bipolar transistors (by the second power of the scaling factor k). Even very short glitches (< 1 ns) may then initiate latch-up. The only methods to prevent latch-up are: (1) the use of Schottky diodes or special polysilicon p+n ÷ diodes [10] instead of ohmic substrate and well contacts; or (2) the use of new and further developed technologies, e.g. a highly doped substrate with box isolation where the trench reaches far into the highly doped region [3].
Voo
T pnp
Cw+ Qc
~ Q8
npn
Rsl I VBB '~ VSB°
RVBB I Vss
Qa=q'AE'Ns'We
wg
~S=2D
Fig. 4 Transient latch-up: equivalent circuit for the floating well concept with VBa generator
22
W. Reczek, F. Bonner and B. Murphy
Voo
0n0/
Rw
i
T Cw
Vss
QB = q" AE" NB" Ws
w#
~a= 2D
Fig. 5 Transient latch-up: equivalent circuit for conventional L O G I C circuits
~ Voo
!i~ =1
+ Cw
C+ RSl Vea
~
Veao
Ri
Rs2
~ CvaE~a
C_
Vss
Q8= q " AE' NS• Ws ~a= 20 Fig. 6 Transient latch-up: equivalent circuit for DRAMs/LOGIC with V.. generator 4. Conclusion
The impact of three different scaling laws on three different circuit design methods has been discussed. At power-on, each of the scaling concepts leads to an increased latch-up risk for circuits with VBB generators, making power-on protection circuits necessary. The risk of pulse-initiated latch-up is increased for each cir-
Scaling aspects for different CMOS circuit designs due to transient latch-up effects
23
cuit design method. Only novel device structures and/or box isolation can lead to increased transient latch-up hardness. The results presented are valid for both pwell and n-well concepts as the mechanism which initiates latch-up is independent of the well concept used.
5. Acknowledgements This report is based on a project which has been supported by the Minister for Research and Technology of the Federal Republic of Germany under the supportno. NT 2696. For the contents the authors alone are responsible.
6. References Kohyama, S. et al., "Directions in CMOS technology", I E D M Tech. Digest, p. 151, 1983. [2] Chen, J.Y., "'Scaling CMOS to submicron design rules for VLSI", VLSI Design, p. 78, July 1984. [3] Parrillo, L.C.,"Process and device considerations for micron and submicron CMOS technology", I E D M Tech. Digest, p. 398, 1985. [4] Chatterjee, P.K., "'The impact of scaling laws on the choice of n-channel or pchannel for MOS VLSI", IEEE Electron Device Lett.. vol. 1, p. 220, 1980. [5] Woods, M.H. and Euzent, B.L., "'Reliability in MOS integrated circuits", I E D M Tech. Digest, p. 50, 1984. [6] Estreich, D.B., Ph.D. Dissertation, Stanford University, CA, 1980. [7] Reczek, W, Ph.D. Dissertation, Technical University, Munich, 1988. [8] Gentry, et al., SCR: Principles and Application o f pnpn Devices, PrenticeHall, Englewood Cliffs, NJ, pp. 113-117, 1964. [9] Reczek, W. et al., "Guidelines for latch-up characterization techniques", ICMTS Tech. Digest, p. 120, 1988. [10] Pribyl, W. and Reczek, W., "A novel device structure for latch-up free VLSI CMOS circuits", S S D M Tech. Digest, p. 613, 1988. [1]
The influence of three different scaling concepts: constant field (CE); constant voltage (CV); and compaction shrink (CS) on the latch-up behaviour of CMOS circuits is examined in detail for each of three circuit design methods: (1) floating well concept with substrate-bias (VBB) generator; (2) conventional LOGIC with grounded p-substrate and n-well connected to VCC; and (3) DRAM/LOGIC with VBB generator and n-well connected to VCC. Scaling results in increased power-on latch-up susceptibility for circuits with VBB generators. This risk can only be reduced by the use of protection circuits which limit the internal power supply ramp rate. Latch-up susceptibility to pulses (e.g. overshoot, undershoot and glitches) is increased for each circuit type as a result of scaling and can only be reduced by the use of novel device structures or by new and better developed technologies. For example, a highly doped substrate with a box isolation may be used, where the trench reaches far into the highly-doped region. The results presented are valid for both p-well and n-well concepts as the mechanism which initiates transient latch-up is independent of the well concept used.
1. Introduction In recent years, the effects of different scaling concepts on MOS device dimensions, on packing density, on performance as well as on the proper choice of well concept have been studied extensively [I-5]. Table 1 shows the impact of constant field (CE), constant voltage (CV) and compaction shrink (CS) on the most important parameters: device dimensions (gate oxide thickness, To~d~,channel length, L, channel width, W), impurity concentration, supply voltage, device current, capacitance, RC delay, power per element and line resistance. For the CE concept, supply voltage and current are reduced by a factor 1/k. This appears to be the best way to scale down device dimensions but is in conflict with established user power supply standards. The question arises as to whether on-chip voltage reduction should be used or if a new voltage standard at board level (e.g. 3.3 V) should be adopted. The second scaling concept (CV) can result in the problem of hot carrier generation. Hot electrons have up until now played the most important role. In the deep submicron region, however, hot holes seem to be the biggest problem. • An earlier version of this paper was presented at MIEL "89. Nig. Yugosla~4a. May 9-1 I. 1989
MICROELECTRONICS JOURNAL Vol. 21 No. 3 © 1990 Elsevier Science Publishers Ltd., England
15
16
W. Reczek. F. Bonner and B. Murphy
TABLE 1 CMOS scaling (k>l) for CE, CV and CS Parameter
CE factor
CV factor
CS factor
ToxiJ~, L, W
l/k
1/k
l/k
k
k
1
Voltage
1/k
1
1
Current
l/k
I
1/k
Capacitance
1/k
l/k
l/k
Delay
1/k
l/k
1
Power/element
1/k-'
1
1/k
Line resistance
k
k
k
Doping concentration
Toxid e a n d L = c o n s t a n t
The third scaling concept (CS) is a tradeoffbetween these two scaling concepts, orientated towards industrial requirements. The impact of different scaling trends on static latch-up behaviour has been much discussed [6]. No attempt has been made, however, to describe the effects of different scaling concepts on transient latch-up susceptibility, which is the subject of this paper. The basis for investigation is an n-well CMOS technology. The results presented and conclusions drawn are valid for both n-well and p-well concepts as the mechanism which initiates latch-up is independent of the well concept used.
2. Power-on latch-up As a CMOS circuit is supplied with VCC, the substrate/well depletion zone is established. Majority carriers then flow to their respective contacts, i.e. electrons in the n-well flow to the n-well contact and holes in the p-substrate flow to the psubstrate contact. This leads to an ohmic voltage drop which causes forward biasing of the p-n junctions and consequent latch-up if this forward-bias is large enough. Majority carrier current resulting from the charging of capacitances in the environment of the latch-up path must also be considered for the triggering of latch-up. At power-on the rise time, At, of the supply voltage, AV, is the critical parameter in determining whether a critical forward-bias level for the initiation of latch-up is reached [7]. M a n y actual circuit designs have severe problems at ramp rates equal to or greater than 1 V ps -j. Such ramp rates are often achieved even at board level. Table 2 shows the effect scaling will have on the future critical rise time. Figures 1 3 show the equivalent circuits for each circuit design method used and the relevant parameters are given in Table 3.
Scaling aspects lbr difl'erent CMOS circuit designs due to transient latch-up effects
17
TABLE 2 Allowable rise-time of the supply voltage due to power-on latch-up (k> 1)
Circuit/design method
CE
CV
CS
Case I*
1
v/k
1
Base charge
Case 2**
1/k 2
1/k t~
l/k
Well capacitance
Case 3*** DRAM area shrink
Relevant parameter
Cell plate capacitance
k2
DRAM kc more cells
k'. kc
LOGIC area shrink LOGIC km more devices
1
v/k
1
km
km. v/k
km
Peripheral capacitance, without V~ transition to case 2
*Floating well concept with VBB generalor. **Conventional LOGIC v,ith grounded p-substrale and n-well connected to VDD. ***DRAM/LOGIC with VBB generator and n-well connected to VDI).
&VoD/&t
Cw
~
pn
Q8
Qc
np
Vss V 2Ss , So . A 2 • q" Nd" V QC = Nd (1 + -~a ) QB
=
q " AE
" NB
"
WB
Fig. 1 Power-on latch-up: equivalent circuit for the floating well concept with VBB generator
18
W. Reczetc F. Bonner and B. Murphy
&Voo/At
&Voo/&t
~Rw?
t ~np
tRw
Vss
Vss
(1 ÷ ~ =Cw(Rw+ Rs) Fig. 2 Power-on latch-up" equivalent circuit for conventional LOGIC circuits
AVoo/At
o
AVoo/At
_
RSl
=. I]la KI
Yea
C_
Vss
Idlso~ AM
Vs,,
VBEven . __1
81at~-(. L. /2
QB = q ' AE ' N8 ' WB Fig. 3 Power-on latch-up: equivalent circuit for DRAMs/LOGIC with VBB generator
2.1 CMOS with VBB generator and floating well Since the on-chip substrate-bias (VBB) generator only works after a time delay of some microseconds, the substrate is floating during this time, resulting in a substrate resistance that is close to infinity [7]. The equivalent circuit for the case of power-on is shown in Fig. 1. The lumped element model is similar to the conventional equivalent circuit of a silicon controlled rectifier [8], consisting only of the
Scaling aspects for different CMOS circuit designs due to transient latch-up effects
19
TABLE 3 List of parameters
CW
C+ C_ CvBa
Rs, Rs2 Rvaa Rw V VBElal VBEverl
Vaa VBBO
Vt~o Vss Qs Qc Idiso
A AE WB
q £s " £o
N~ N~ NB t n
D
13 "{7B
Substrate well capacitance Coupling capacitance [7] Buffering capacitance between VSS and VBB [7] VBB generator capacitance Substrate shunt resistance Distributed resistances in the substrate [7] Internal resistance of the VBB generator (also called R,) Well shunt resistance Corresponds to a voltage Base emitter voltage of the lateral bipolar transistor Base emitter voltage of the vertical bipolar transistor Back bias substrate voltage Internally generated voltage of the VBB generator Positive supply voltage Negative supply voltage (ground) Base charge of one of the parasitic bipolar transistors Charge stored at the substrate well junction [8] Displacement current Area of the substrate well junction Corresponding emitter area (e.g. n + or p+ diffusion in the substrate and well, respectively) Base width of the corresponding parasitic bipolar transistor Elementary charge Dielectric constant Impurity concentration of the substrate Impurity concentration of the well Impurity concentration of the corresponding base (e.g. substrate=lateral and well = vertical) Diffusion length of the (electron) minorities in the p-substrate Diffusion constant Current gain (e.g. 13,.,of the lateral bipolar transistor) Base transmit time of the corresponding bipolar transistor
vertical and lateral parasitic bipolar transistors and the substrate well capacitance, Cw. The relevant parameters for latch-up are the base charge, Qa, of one of the bipolar transistors and the charge, Qc, established on the substrate well capacitance, Cw (see Fig. 1). Any change in the relationship Of QB to Qc is critical in evaluating the impact of the different scaling concepts.
20
W. Reczek. F. Bonner and B. Murphy
For CE and CS the ratio of Q~ to Qc stays constant and the critical ramp rate of VCC is not affected. In the case of CV the ratio of QB to Qc increases by a factor of v/k. The rise time of the constant supply voltage, V, must then be increased by the same factor to avoid latch-up.
2.2 Conventional CMOS For conventional LOGIC circuits the substrate and the well are connected to VSS and VCC, respectively. Figure 2 shows the complete equivalent lumped element model as well as the simplified circuit, which consists only of a simple series RC network, comprising substrate and well shunt resistances Rs and Rw, and substrate well capacitance, Cw. The bipolar transistors may be neglected providing the forward bias of the base emitter junction is less than 0.7 V. With the ramp rate, AV/ At, as stimulus, expressions for the base emitter voltages of the parasitic bipolar transistors can be calculated (see Fig. 2). R s, Rw and Cw are shown to be the important parameters. For all three scaling concepts the resistances Rs and Rw stay the same to a first order approximation. In the case ofCE, Cw and V are reduced by a factor of 1/k resulting in an increase (relaxation) of the critical ramp rate by a factor of k2. For the case ofCV, V stays constant but Cw is reduced by l/k L5so that the critical ramp rate is increased by a factor of k LS. Using the CS method Cw is reduced by 1/k and V remains constant. The critical ramp rate is then increased by just a factor of K.
2.3 CMOS with VBB generator and conventional well contacts Circuits are considered with on-chip VBB generators and large capacitances in the periphery or environment of the functional unit latch-up path, as in the case of DRAMs. The equivalent circuit is shown in Fig. 3. The standard latch-up lumped element model is enhanced by the coupling capacitances, C+ (cell plate capacitance, and all other capacitance in the periphery tied between VBB and VSS), the buffering capacitance, C_ (capacitance between VSS and VBB) and the VBB generator. Furthermore the substrate resistance must be divided into two separate parts, Rs~ and Rs2, because of the VBB generator [7]. The circuit may then be re-simplified, to consist only ofRw, Rs, the large C+ (the ratio C+ :C_ = 20:1 in the case of a 1 Mbit DRAM) and the lateral bipolar transistor. The vertical bipolar transistor may be neglected because the base emitter voltage of 0.7 V at the vertical bipolar transistor is taken as the indicator for latch-up. The important parameters are [3~,,,of the lateral bipolar transistor and, more importantly, C+. As the capacitance per cell unit has to stay the same for soft error reasons, the ramp rate has to be reduced by a factor of k2. This slowing of the VCC ramp-rate can only be achieved through the use of power-on protection circuits [7]. A summary of the previous results is shown in Table 2. While for conventional LOGIC (Table 2, case 2) the risk of power-on latch-up is reduced, there is signifi-
Scaling aspects/or dillbrent CMOS circuit designs due to transient latch-up elTects
21
cant risk for all circuits with VBB generators. In particular, severe problems will arise for DRAMs, where the cell capacitance is the major reason for increased latch-up susceptibility. The internal ramp rate has to be reduced by the second power of the scaling factor (k> 1). This is achieved by the use of internal power-on protection circuits which limit the internal ramp rate [7]. The use of a highly doped substrate with an epilayer does not reduce the problem because the power-on latch-up susceptibility of circuits with an epilayer is at least twice that of circuits based on bulk material. One of the reasons for this increased latch-up susceptibility is the increased current gain of the lateral bipolar transistor [7].
3. Latch-up due to pulses
Figures 4 - 6 show the equivalent circuits for each circuit design method. Substrate triggering (forward biasing of the n ÷ p-substrate junction) is only possible in the case of conventional logic circuits [9]. In all cases (forward biasing of the p÷ nwell junction included), the increased latch-up susceptibility to pulses (e.g. overshoot, undershoot and glitches) is not only due to the reduction of the base charge, QB, but also to the reduction in base transit times of the parasitic bipolar transistors (by the second power of the scaling factor k). Even very short glitches (< 1 ns) may then initiate latch-up. The only methods to prevent latch-up are: (1) the use of Schottky diodes or special polysilicon p+n ÷ diodes [10] instead of ohmic substrate and well contacts; or (2) the use of new and further developed technologies, e.g. a highly doped substrate with box isolation where the trench reaches far into the highly doped region [3].
Voo
T pnp
Cw+ Qc
~ Q8
npn
Rsl I VBB '~ VSB°
RVBB I Vss
Qa=q'AE'Ns'We
wg
~S=2D
Fig. 4 Transient latch-up: equivalent circuit for the floating well concept with VBa generator
22
W. Reczek, F. Bonner and B. Murphy
Voo
0n0/
Rw
i
T Cw
Vss
QB = q" AE" NB" Ws
w#
~a= 2D
Fig. 5 Transient latch-up: equivalent circuit for conventional L O G I C circuits
~ Voo
!i~ =1
+ Cw
C+ RSl Vea
~
Veao
Ri
Rs2
~ CvaE~a
C_
Vss
Q8= q " AE' NS• Ws ~a= 20 Fig. 6 Transient latch-up: equivalent circuit for DRAMs/LOGIC with V.. generator 4. Conclusion
The impact of three different scaling laws on three different circuit design methods has been discussed. At power-on, each of the scaling concepts leads to an increased latch-up risk for circuits with VBB generators, making power-on protection circuits necessary. The risk of pulse-initiated latch-up is increased for each cir-
Scaling aspects for different CMOS circuit designs due to transient latch-up effects
23
cuit design method. Only novel device structures and/or box isolation can lead to increased transient latch-up hardness. The results presented are valid for both pwell and n-well concepts as the mechanism which initiates latch-up is independent of the well concept used.
5. Acknowledgements This report is based on a project which has been supported by the Minister for Research and Technology of the Federal Republic of Germany under the supportno. NT 2696. For the contents the authors alone are responsible.
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