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Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults
Microelectronics Journal 34 (2003) 23–29 www.elsevier.com/locate/mejo
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults C. Metraa,*, S. Di Francescantonioa, M. Favallib, B. Ricco`a a
DEIS-University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy b DI-University of Ferrara, Viale Saragat 1, 44100 Ferrara, Italy Revised 20 June 2002; accepted 9 September 2002
Abstract We propose a possible modification to the internal structure of scan flip-flops, which allows the online detection of delay and crosstalk faults affecting their input. Our solution allows to obtain, together with the flip-flop output datum, an indication denoting whether or not the provided datum is incorrect, because of an input crosstalk or delay fault. The proposed solution features self-checking ability with respect to a wide set of possible internal faults, including node stuck-ats, transistor stuck-ons and stuck-opens, resistive bridgings, delays, transient and crosstalk faults. q 2002 Elsevier Science Ltd. All rights reserved. Keywords: On-line testing; Scan flip-flops; Crosstalk faults; Delay faults; Self-checking ability
1. Introduction Crosstalk faults have always been a major concern for high reliability applications, like space and avionic. Currently, crosstalk faults are emerging as a major concern also for general purpose systems to be implemented using next generation very deep sub-micron technologies [1]. This is because of the expected reduced distance among interconnections and relative increase of their lateral capacitance (because of the adopted scaling rules), as well as because of the expected reduction of noise margins, which will make very deep sub-micron ICs extremely susceptible to this kind of faults. Meanwhile, the expected increase of ICs’ operation frequency will increase the probability that signals affected by crosstalk faults are sampled, thus resulting in the presence of incorrect data, which might cause system failures, with consequent dramatic impact on reliability and yield. As known [2 – 4], depending on the kind of transitions on the coupled lines, crosstalk faults may result in: (a) speededup transitions (in the case of transitions in the same direction on the coupled lines); (b) delayed transitions (in the case of * Corresponding author. Tel.: þ 39-051-2093785; fax: þ 39-051-2093073. E-mail addresses: [email protected] (C. Metra), [email protected] (S. Di Francescantonio), mfavalli@deis. unibo.it (M. Favalli), [email protected] (B. Ricco`).
opposite transitions on the coupled lines); (c) an undesired transition and a delayed transition, respectively (in the case of a transition only on one coupled line). From the point of view of sampling flip-flops, of course the most dangerous conditions are those of kind (b) and (c). General purpose systems frequently employ scan based techniques in order to improve their testability [5 –13]. As a result a fraction (in the case of partial scan) or all (in the case of full scan) flip-flops are of a scan type [14]. Their correct operation is mandatory for the system reliable operation and for the successful outcome of the testing phase. In this regard, we should note that conventional on-line testing techniques cannot be used to fulfill this purpose. In fact, for instance, duplication and comparison of the scan flip-flops may not detect a crosstalk fault affecting their common input. In addition, as shown in Ref. [15], also the self-checking circuit technique may fail in the on-line detection of logic errors due to crosstalks. Based on these results, in Ref. [16] we introduced a simple circuit allowing the on-line detection of crosstalks, as well as transient and delay faults affecting bus lines. Based on these considerations and previous researches, in this paper, we address the problem of the design of scan flip-flops which feature self-checking ability with respect to possible crosstalk and delay faults affecting the scan flip-flop input and making the flip-flop provide an incorrect
0026-2692/03/$ - see front matter q 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 6 9 2 ( 0 2 ) 0 0 1 2 5 - 8
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output datum, thus compromising either the global system correct operation, or the successful outcome of the testing phase, depending on whether the normal operation input or the test input of the scan flip-flop is affected by the fault. As for the flip-flop clock signal, we assume that it is properly checked by means of a specific scheme, for instance of the kind that we presented in Ref. [17]. Our proposed solution is conceived to be used for scan flip-flops and therefore allows obvious savings in terms of area overhead and flexibility with respect to the possible direct connection of a scheme of the kind in Refs. [15,16,18] to the scan flip-flop inputs. In particular, we propose the use of a suitable selfchecking, hardware scheme which operates in parallel with the latching stage of the scan flip-flop, with negligible impact on the flip-flop’s performance. The self-checking ability of our scheme is guaranteed with respect to a wide and realistic set of faults for very deep sub-micron technology. In particular, we have verified that our additional hardware is Strongly Code-Disjoint (SCD) [19] with respect to all possible internal node stuck-ats, transistor stuck-ons, transistor stuck-opens, resistive bridgings, crosstalks, delays and transient faults, but for a few transistor stuck-opens which, however, have been found less likely to occur than the other listed kinds of faults [20] and can be made even less likely by properly designing the circuit layout [21]. Therefore, but for these undetectable stuck-opens, it is guaranteed that, in the case of the occurrence of internal faults belonging to the considered set, our scheme either provides an output error message, or keeps on detecting on-line possible crosstalk or delay faults affecting the scan flip-flop input. This paper is organized as follows. In Section 2, we introduce the notation that will be used throughout this paper. In Section 3, we propose the basic ideas behind the proposed flip-flops’ modifications. In Section 4, we present a possible design of our additional hardware. In Section 5, we report some of the results obtained by means of conventional and Monte Carlo electrical simulations of the derived scan flip-flop. In Section 6, we discuss the costs and sensitivity of the proposed solution. In Section 7, we analyze the self-checking ability of our additional hardware, while some conclusive remarks are drawn in Section 8.
2. Used notation We refer to a general (master – slave) flip-flop with scan, schematically represented in Fig. 1. Throughout this paper we will refer to the case where the flip-flop is not configured in the test mode, so that the multiplexer connects the input D (hereafter simply referred to as ‘flip-flop input’) to the input of the master stage. However, our scheme could be as well used to check the correctness of the test input TI, when the flip-flop is configured in the test mode.
Fig. 1. Schematic representation of a scan (master–slave) flip-flop.
Assuming that the multiplexer behaves as an inverting gate, the complement of signal D (indicated by D0 in Fig. 1) is produced at the multiplexer output. However, our scheme can also be applied (by straightforward modifications) if the multiplexer behaves as a non-inverting gate. In the case of a delay fault (DF) or crosstalk fault (CF) affecting the flip-flop input during its normal operation, depending on the characteristics of the fault-induced spike or delay, as well as on the flip-flop set-up/hold times, an incorrect datum may or may not be produced at the flip-flop output, thus possibly compromising the correct operation of the whole system.
3. Basic ideas The main goals of our modification to scan flip-flops can be summarized as follows. 1. Ability to detect the presence of a DF or CF affecting the flip-flop input and resulting in an incorrect output as soon as possible (with respect to the instant of fault activation) and generation of an indication of error/non-error at the flip-flop output together with the output datum (and not, for instance, at the following clock period). This in order to possibly immediately block the propagation throughout the system of the incorrect datum, thus preserving data integrity and possibly activating a proper recovery technique in order to tolerate the detected fault. 2. Minimal impact on the flip-flop timing characteristics in order not to degrade system performance. To achieve these goals, a conceptual scheme of the kind in Fig. 2 can be connected in parallel to the latching stage of the scan flip-flop. The additional hardware receives the flip-flop signal D and D0 , and a suitable ENable signal (EN), which drives the input switches (for instance implemented by means of CMOS transfer gates). Such a signal allows to check the correctness of the flip-flop input datum only in the time intervals (for instance identified by EN ¼ 1) during which no transition of the input datum can occur in the fault-free case. Such a time interval should be properly chosen on the basis of timing and failure analyses and could be properly generated exploiting the clock signal (CK). Of course, the relative timing of the CK and EN signals should be managed by using proper routing techniques [22].
C. Metra et al. / Microelectronics Journal 34 (2003) 23–29
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they could be properly scanned out in order to facilitate fault diagnosis. Finally, in both cases, a proper recovery procedure may be activated to recover from the detected fault.
4. Possible design
Fig. 2. Schematic representation of the proposed modification to scan flipflops.
If the flip-flop input is stable when EN ¼ 1 we obtain a stable (10) or (01) on nodes (EX1, EX2), that is a codeword of the two-rail code. Instead, if a DF or CF affects the flipflop input when EN ¼ 1 and makes it either change later than expected for the fault-free case or undesirably change, because of the input –output delay of the inverting multiplexer, we have a (00) or (11) on (EX1, EX2), that is a noncodeword of the two-rail code. In particular, in the case of CFs resulting in the presence of a spike on the flip-flop input datum, the duration of the error message provided on (EX1, EX2), denoted by dER, is given by the following relationships: † if dMUX , dTRi # dMUX ; dER ¼ dTRi ; † if dTRi . dMUX ; dER ¼ dMUX ; where dTRi denotes the duration of the crosstalk-due spike (evaluated at the logic threshold of the fan-out gates), while dMUX is the input – output delay of the multiplexer and dMUX is the multiplexer inertial delay. Of course if dMUX $ dTRi ; the spike is filtered out by the input multiplexer and no error indication should be given. Instead, in the case of DFs or CFs resulting in a delayed transition of the flip-flop input datum, dER ¼ dMUX : In order not to risk to miss any error message, independently of the fan-out logic, a proper additional stage should be connected to the considered switches. Such a stage should: (i) if (EX1, EX2) ¼ 01 or 10, give output codewords; (ii) if (EX1, EX2) ¼ 00 or 11, give an output non-codeword and keep on giving output non-codewords until a suitable reset signal (RES) is activated, independently of the possible disappearance of the input noncodeword. In particular, such a reset signal will allow to start again the operation of our scheme, once fault detection and possible recovery are accomplished. Blocks of this kind are widely used in the case of self-checking circuits, and various designs have been up to now proposed [17,23,24]. At system level, depending on the considered application, the two additional outputs of all scan flip-flops could then be joined together by means of a conventional two-rail code checker, in order to provide a global error message, or
As an example of a possible application of our idea, we here consider the case of the scan flip-flop of the ES2 Standard Library (Fig. 3) [25]. The derived scan flip-flop is shown in Fig. 4 where as an example, we have considered the EI block implemented as in Ref. [17]. In particular, in Fig. 4, EN0 (CK0 ) denotes the complement of signal EN (CK), and RES and RES0 are the reset signal and its complement, respectively. We can easily verify that, in the case of a CF or DF affecting the input signal D and making the driven flip-flop sample an incorrect datum, a (00) or (11) is temporarily given to the input of the additional hardware, which results in the occurrence of an error indication on nodes (ER1, ER2), where it remains latched until reset.
5. Verification Our derived modified scan flip-flop has been implemented considering a standard 0.18 mm CMOS technology and designed with the following transistor aspect ratios: (i) ðW=LÞn ¼ 1 and ðW=LÞp ¼ 4:5; for the inverters and transfer gates; (ii) ðW=LÞn ¼ 2 and ðW=LÞp ¼ 9; for the series transistors of the scan flip-flop; (iii) ðW=LÞn ¼ 1:6 and ðW=LÞp ¼ 7; for the transistors of the feedback inverting gates. As an example, we have considered an EN signal, which remains ¼ 1 for a time interval equal to the sum of the scan flip-flop set-up and hold times. The behavior of our modified flip-flops has been verified by means of conventional and Monte Carlo electrical simulations, considering possible statistical variations (with uniform distribution) of electrical parameters and power supply up to the 20%. As for the parasitic coupling, we have considered the model in Ref. [2].
Fig. 3. Scan flip-flop of the ES2 Standard Library considered here as an example.
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Fig. 6. Example of the results obtained for the case of an input delay (due to a DF or CF) making the flip-flop produce an incorrect output datum.
Fig. 4. Modified scan flip-flop of the ES2 Standard Library.
The results achieved under nominal values of electrical parameters and considering fault-free conditions are reported in Fig. 5. We can easily see that our modified flip-flop provides an output indication of correct operation ðER1 – ER2Þ: Instead, Fig. 6 shows the results obtained in the case of a delay in the transition of the scan flip-flop input (due to a DF or CF affecting such an input) and making the flip-flop provide an incorrect output datum. As can be seen, an output error indication is produced ðER1 ¼ ER2 ¼ 1Þ: Similarly, Fig. 7 shows the results obtained in the case of a CF affecting the scan flip-flop input and resulting in an input spike. As can be seen, also in this case, an output error indication is produced ðER1 ¼ ER2 ¼ 1Þ:
Fig. 5. Example of the results obtained for the fault-free case.
Similar results have been obtained considering possible statistical variations (with uniform distribution) of electrical parameters and power supply up to the 20%. We should note (Fig. 5) that the proposed additional hardware provides the output indication concerning the correctness of the flip-flop output datum simultaneously with the sampled output datum itself, thus allowing (at the system level) to possibly avoid the propagation of incorrect data (due to input CFs or DFs) to the fan-out logic. Of course, to detect the possible incorrectness of the flipflop output because of logical faults (e.g. stuck-ats), a conventional off-line testing technique or conventional selfchecking techniques could be adopted.
6. Costs and sensitivity Let us discuss the costs of our scheme in terms of speed, possible impact on system’s performance and area overhead, as well as the fault sensitivity of our modified flipflops. As for speed, the input –output delay of our scheme (d ) with respect to the instant of fault activation is given by:
Fig. 7. Example of the results obtained in the case of a crosstalk fault affecting the scan flip-flop input and resulting in an input spike.
C. Metra et al. / Microelectronics Journal 34 (2003) 23–29
d ¼ dTG þ 3TNOT ; where dTG is the input – output delay of a conductive transfer gate, while TNOT is the input –output delay of the additional hardware inverter. This high speed in fault detection allows us to obtain the output indication concerning the correctness of the flip-flop output datum simultaneously with the sampled output datum itself, thus allowing (at the system level) to possibly avoid the propagation of incorrect data (due to input CFs or DFs) to the fan-out logic. As for the impact on system’s performance, we should consider that our additional hardware is conceived as operating in parallel with the system’s flip-flops. Therefore, its impact on performance is basically due only to the increase in the flip-flop input capacitive load, which can be considered negligible. As for our scheme sensitivity to faulty (i.e. delayed or undesired) transitions of the input datum (due to DFs or CFs), our scheme is conceived as able to detect on-line all transitions that occur when EN ¼ 1: In particular, delayed transitions (e.g. due to DFs or CFs) are always detected. As for spurious transitions (e.g. due to CFs), instead, they are detected if they are not filtered out by the MUX’s inertial delay. It should be noted that filtered transitions do not affect the value sampled by the flip-flops, so that it is desirable not to detect them. As for the interval during which EN ¼ 1, as already introduced, it should be chosen on the basis of timing and failure analysis, in order to guarantee the detection of all faulty transitions which prevent the flip-flop from providing the correct output signal, thus possibly compromising the system’s correct operation. As for area, our modification of course implies an increase which, however, is lower than that required by any other on-line testing strategy [15,16,18] possibly adopted to address the here considered problem. Of course, in the case of systems featuring a huge number of flip-flops and fullscan, the area overhead due to our flip-flop modification may be high. In this case, timing analysis can be used to identify those signals which are on critical paths, thus being more exposed to the effects of delay and crosstalk faults. The use of the proposed flip-flop modifications can then be applied only to the scan flip-flops sampling such signals.
7. Self-checking ability We have considered a set of faults (F0 ) possibly affecting our additional hardware composed of all possible node stuck-ats (SAs), transistor stuck-ons (SONs), transistor stuck-opens (SOPs), resistive bridgings (BFs), crosstalks (CTs), delays (DFs) and transient faults (TFs). We have referred to the following fault assumptions [26], generally considered in case of self-checking circuits: (1) faults occur one at a time; (2) the time elapsing between the occurrence of two following faults is long enough to allow the application of all possible input codewords. Of course,
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assumption (2) can be reasonably changed into the assumption that the time elapsing between the occurrence of two following faults is long enough to allow the application of all possible scan flip-flop inputs. To guarantee the self-checking behavior of our additional hardware, we must verify that, with respect to the possible internal faults, it satisfies the Totally Self-Checking (TSC) [27] or SCD [19] property. We have verified that our additional hardware is SCD with respect to all possible internal SAs, SONs, SOPs, BFs, CFs, DFs and TFs, but the SOPs possibly affecting the feedback inverting gates. As for these undetectable faults, we should consider that SOPs have been found less likely to occur than the other listed kinds of faults [20], and that their occurrence probability can be further reduced by properly designing the circuit layout [21]. The analyses performed for the different kinds of possible faults are summarized in Sections 7.1– 7.3. 7.1. Node stuck-at faults SAs might affect: (i) signal EN or EN0 (that we assume independently generated); (ii) input/output nodes of the used inverters; (iii) input/output nodes of the feedback inverting gates. The SA1 of kind (i) affecting EN makes the transfer gates always conductive, therefore also when signal transitions are actually allowed. Consequently, our scheme provides an output error message and is TSC (therefore also SCD) with respect to this SA. The SA0 of kind (i) affecting EN makes the n-channel pass-transistors of both transfer gates not conductive. Thus, only the p-channel pass-transistors are conductive when EN ¼ 1. When this is the case, the different ability of pchannel pass-transistors to transfer a high and a low logic value makes signal propagation delays through the pchannel pass-transistors asymmetric. Consequently, an error indication ((00) or (11)) is given to the input of the feedback inverting gates and an error indication is produced at the output of our scheme. Therefore, our scheme is TSC (hence SCD) with respect to the considered SA. Similar considerations hold true for the SA0/1 of kind (i) affecting EN0 . As for SAs of kinds (ii) and (iii), it can be easily verified that they result in the generation (and memorization) of an error message. Therefore our scheme is TSC (hence SCD) with respect to these faults. 7.2. Transistor stuck-on and stuck-open faults SONs might affect a transistor of: (i) the transfer gates; (ii) the proposed additional hardware inverters; (iii) the feedback inverting gates. SONs of kind (i) make a pass-transistor be conductive also in the time intervals during which transitions of the scan flip-flop input signal are allowed. Thus, the same
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considerations as for the SA1 of kind (i) affecting EN hold true. Depending on the circuit electrical level design, SONs of kind (ii) may, or may not, result equivalent to SAs of kind (ii). When this is the case, of course, the same considerations as for SAs of kind (ii) hold true. Instead, when they are not equivalent to such SAs, they are undetected. However, our scheme does not loose its ability to reveal the occurrence of logic errors due to CFs or DFs. Moreover, if other faults [ F0 occur, our additional hardware either gives an error indication, or does not loose its ability to detect the occurrence of logic errors due to CFs or DFs. Thus our scheme is SCD with respect to such SONs. Finally, SONs of kind (iii) result in an error message, that is consequently memorized. Hence, our proposed hardware is TSC (hence SCD) with respect to them. Now let us consider the possible SOPs, which might affect a transistor of: (i) the transfer gates; (ii) the scheme inverters; (iii) the feedback inverting gates. As for SOPs of kind (i), considerations similar to those as for the SA0 of kind (i) affecting EN hold true. Thus, our scheme is TSC (hence SCD) with respect to such faults. As for SOPs of kind (ii), they result in an incorrect logic value at the output of the faulty inverter (that retains the previously charged logic value). Thus, considerations similar to those for SAs of kind (ii) hold true, and our scheme is TSC (hence SCD) with respect to these faults. SOPs of kind (iii), instead, cannot be detected and our scheme is neither TSC, nor SCD with respect to them. However, SOPs have been verified to be less likely to occur than the other kinds of faults considered here [20]. Moreover, their likelihood can be further reduced by suitably designing the circuit layout [21].
behaving as if fault-free. Therefore, our scheme is SCD with respect to possible BFs. As for CTs affecting our proposed additional hardware, we have verified that our scheme either provides an output error message, or maintains its ability to reveal CFs or DFs that affect the scan flip-flop input line. Therefore, our proposed additional hardware is SCD with respect to CTs. Similar considerations hold true also for TFs and DFs affecting our proposed hardware, with respect to which the SCD property is therefore satisfied.
7.3. Resistive bridging, crosstalk, delay and transient faults
[1] Semiconductor Industry Association, San Jose, CA, The 2001 national technology roadmap for semiconductors, 2001. [2] F. Moll, A. Rubio, Methodology of detection of spurious signals in VLSI circuits, Proc Eur Des Test Conf (1993) 491 –496. [3] W. Chen, S.K. Gupta, M.A. Breuer, Analytic models for crosstalk delay and pulse analysis under non-ideal inputs, Proc IEEE Int Test Conf (1997) 809–818. [4] W. Chen, S.K. Gupta, M.A. Breuer, Test generation in VLSI circuits for crosstalk noise, Proc IEEE Int Test Conf (1998) 641– 650. [5] M. Abramovici, J. Kulikowski, R. Roy, The best flip-flops to scan, Proc IEEE Int Test Conf (1991) 166 –173. [6] C. Lin, Y. Zorian, S. Bhawmik, PSBIST: a partial-scan based built-in self-test scheme, Proc IEEE Int Test Conf (1993) 507–516. [7] M. Abramovici, P. Parikh, B. Mathew, D. Saab, On selecting flip-flops for partial reset, Proc IEEE Int Test Conf (1993) 1008–1012. [8] K. Lin, C. Chen, T. Hwang, Layout-driven chaining of scan flip-flops, IEE Proc Comput Dig Tech (1996) 421–425. [9] F. Corno, P. Prinetto, M. Rebaudengo, M.S. Reorda, Partial scan flip flop selection for simulation-based sequential ATPGs, Proc IEEE Int Test Conf (1996) 558 –564. [10] I. Ghosh, A practical method for selecting partial scan flip-flops for large circuits, VLSI Des (1996) 284– 288. [11] J. Savir, Scan latch design for delay test, Proc IEEE Int Test Conf (1997) 446 –453. [12] S. Chang, K. Lee, Z. Wu, W. Jone, Reducing test application time by scan flip-flops sharing, IEE Proc Comput Dig Tech (2000) 42–48.
As for possible BFs affecting the proposed additional hardware, electrical level simulations have been performed by means of HSPICE considering, for each BF, values of the connecting resistance the interval ]0, 6 kV] [28]. We have verified that: (i) for the largest fraction of BFs, our additional hardware gives an output error message for all the considered values of R; (ii) for the BFs (or the BF values) not resulting in an output error message, our scheme maintains its ability to detect the occurrence of logic errors due to CFs or DFs that affect the flip-flop input signal. Moreover, if BFs of kind (ii) are followed by other faults [ F0 , our additional hardware either gives an output error message, or maintains its ability to detect the occurrence of logic errors due to CFs or DFs that affect the scan flip-flop input signal. Similarly, BFs involving lines of the additional hardware used for different scan flip-flops either result in the generation of an output error message, or do not affect (from the logical and dynamical point of view) our scheme correct operation. In this last case, if following faults occur, either an error message is produced, or our scheme keeps on
8. Conclusions We have presented a possible modification to the internal structure of scan flip-flops which allows the on-line detection of DFs and CFs affecting their input data. The proposed solution allows to obtain, at the flip-flop output, together with the output datum, an indication denoting whether or not the provided datum is incorrect, because of an input crosstalk or delay fault. The proposed solution can be used for the scan flip-flop normal operation input and test input. A full-custom VLSI design of the proposed solution has been presented. However, standard cell based designs can be also easily conceived. The proposed solution features self-checking ability with respect to a wide set of possible internal faults, including node stuck-ats, transistor stuck-ons and stuck-opens, resistive bridgings, delays, crosstalks and transient faults.
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Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults C. Metraa,*, S. Di Francescantonioa, M. Favallib, B. Ricco`a a
DEIS-University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy b DI-University of Ferrara, Viale Saragat 1, 44100 Ferrara, Italy Revised 20 June 2002; accepted 9 September 2002
Abstract We propose a possible modification to the internal structure of scan flip-flops, which allows the online detection of delay and crosstalk faults affecting their input. Our solution allows to obtain, together with the flip-flop output datum, an indication denoting whether or not the provided datum is incorrect, because of an input crosstalk or delay fault. The proposed solution features self-checking ability with respect to a wide set of possible internal faults, including node stuck-ats, transistor stuck-ons and stuck-opens, resistive bridgings, delays, transient and crosstalk faults. q 2002 Elsevier Science Ltd. All rights reserved. Keywords: On-line testing; Scan flip-flops; Crosstalk faults; Delay faults; Self-checking ability
1. Introduction Crosstalk faults have always been a major concern for high reliability applications, like space and avionic. Currently, crosstalk faults are emerging as a major concern also for general purpose systems to be implemented using next generation very deep sub-micron technologies [1]. This is because of the expected reduced distance among interconnections and relative increase of their lateral capacitance (because of the adopted scaling rules), as well as because of the expected reduction of noise margins, which will make very deep sub-micron ICs extremely susceptible to this kind of faults. Meanwhile, the expected increase of ICs’ operation frequency will increase the probability that signals affected by crosstalk faults are sampled, thus resulting in the presence of incorrect data, which might cause system failures, with consequent dramatic impact on reliability and yield. As known [2 – 4], depending on the kind of transitions on the coupled lines, crosstalk faults may result in: (a) speededup transitions (in the case of transitions in the same direction on the coupled lines); (b) delayed transitions (in the case of * Corresponding author. Tel.: þ 39-051-2093785; fax: þ 39-051-2093073. E-mail addresses: [email protected] (C. Metra), [email protected] (S. Di Francescantonio), mfavalli@deis. unibo.it (M. Favalli), [email protected] (B. Ricco`).
opposite transitions on the coupled lines); (c) an undesired transition and a delayed transition, respectively (in the case of a transition only on one coupled line). From the point of view of sampling flip-flops, of course the most dangerous conditions are those of kind (b) and (c). General purpose systems frequently employ scan based techniques in order to improve their testability [5 –13]. As a result a fraction (in the case of partial scan) or all (in the case of full scan) flip-flops are of a scan type [14]. Their correct operation is mandatory for the system reliable operation and for the successful outcome of the testing phase. In this regard, we should note that conventional on-line testing techniques cannot be used to fulfill this purpose. In fact, for instance, duplication and comparison of the scan flip-flops may not detect a crosstalk fault affecting their common input. In addition, as shown in Ref. [15], also the self-checking circuit technique may fail in the on-line detection of logic errors due to crosstalks. Based on these results, in Ref. [16] we introduced a simple circuit allowing the on-line detection of crosstalks, as well as transient and delay faults affecting bus lines. Based on these considerations and previous researches, in this paper, we address the problem of the design of scan flip-flops which feature self-checking ability with respect to possible crosstalk and delay faults affecting the scan flip-flop input and making the flip-flop provide an incorrect
0026-2692/03/$ - see front matter q 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 6 9 2 ( 0 2 ) 0 0 1 2 5 - 8
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output datum, thus compromising either the global system correct operation, or the successful outcome of the testing phase, depending on whether the normal operation input or the test input of the scan flip-flop is affected by the fault. As for the flip-flop clock signal, we assume that it is properly checked by means of a specific scheme, for instance of the kind that we presented in Ref. [17]. Our proposed solution is conceived to be used for scan flip-flops and therefore allows obvious savings in terms of area overhead and flexibility with respect to the possible direct connection of a scheme of the kind in Refs. [15,16,18] to the scan flip-flop inputs. In particular, we propose the use of a suitable selfchecking, hardware scheme which operates in parallel with the latching stage of the scan flip-flop, with negligible impact on the flip-flop’s performance. The self-checking ability of our scheme is guaranteed with respect to a wide and realistic set of faults for very deep sub-micron technology. In particular, we have verified that our additional hardware is Strongly Code-Disjoint (SCD) [19] with respect to all possible internal node stuck-ats, transistor stuck-ons, transistor stuck-opens, resistive bridgings, crosstalks, delays and transient faults, but for a few transistor stuck-opens which, however, have been found less likely to occur than the other listed kinds of faults [20] and can be made even less likely by properly designing the circuit layout [21]. Therefore, but for these undetectable stuck-opens, it is guaranteed that, in the case of the occurrence of internal faults belonging to the considered set, our scheme either provides an output error message, or keeps on detecting on-line possible crosstalk or delay faults affecting the scan flip-flop input. This paper is organized as follows. In Section 2, we introduce the notation that will be used throughout this paper. In Section 3, we propose the basic ideas behind the proposed flip-flops’ modifications. In Section 4, we present a possible design of our additional hardware. In Section 5, we report some of the results obtained by means of conventional and Monte Carlo electrical simulations of the derived scan flip-flop. In Section 6, we discuss the costs and sensitivity of the proposed solution. In Section 7, we analyze the self-checking ability of our additional hardware, while some conclusive remarks are drawn in Section 8.
2. Used notation We refer to a general (master – slave) flip-flop with scan, schematically represented in Fig. 1. Throughout this paper we will refer to the case where the flip-flop is not configured in the test mode, so that the multiplexer connects the input D (hereafter simply referred to as ‘flip-flop input’) to the input of the master stage. However, our scheme could be as well used to check the correctness of the test input TI, when the flip-flop is configured in the test mode.
Fig. 1. Schematic representation of a scan (master–slave) flip-flop.
Assuming that the multiplexer behaves as an inverting gate, the complement of signal D (indicated by D0 in Fig. 1) is produced at the multiplexer output. However, our scheme can also be applied (by straightforward modifications) if the multiplexer behaves as a non-inverting gate. In the case of a delay fault (DF) or crosstalk fault (CF) affecting the flip-flop input during its normal operation, depending on the characteristics of the fault-induced spike or delay, as well as on the flip-flop set-up/hold times, an incorrect datum may or may not be produced at the flip-flop output, thus possibly compromising the correct operation of the whole system.
3. Basic ideas The main goals of our modification to scan flip-flops can be summarized as follows. 1. Ability to detect the presence of a DF or CF affecting the flip-flop input and resulting in an incorrect output as soon as possible (with respect to the instant of fault activation) and generation of an indication of error/non-error at the flip-flop output together with the output datum (and not, for instance, at the following clock period). This in order to possibly immediately block the propagation throughout the system of the incorrect datum, thus preserving data integrity and possibly activating a proper recovery technique in order to tolerate the detected fault. 2. Minimal impact on the flip-flop timing characteristics in order not to degrade system performance. To achieve these goals, a conceptual scheme of the kind in Fig. 2 can be connected in parallel to the latching stage of the scan flip-flop. The additional hardware receives the flip-flop signal D and D0 , and a suitable ENable signal (EN), which drives the input switches (for instance implemented by means of CMOS transfer gates). Such a signal allows to check the correctness of the flip-flop input datum only in the time intervals (for instance identified by EN ¼ 1) during which no transition of the input datum can occur in the fault-free case. Such a time interval should be properly chosen on the basis of timing and failure analyses and could be properly generated exploiting the clock signal (CK). Of course, the relative timing of the CK and EN signals should be managed by using proper routing techniques [22].
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they could be properly scanned out in order to facilitate fault diagnosis. Finally, in both cases, a proper recovery procedure may be activated to recover from the detected fault.
4. Possible design
Fig. 2. Schematic representation of the proposed modification to scan flipflops.
If the flip-flop input is stable when EN ¼ 1 we obtain a stable (10) or (01) on nodes (EX1, EX2), that is a codeword of the two-rail code. Instead, if a DF or CF affects the flipflop input when EN ¼ 1 and makes it either change later than expected for the fault-free case or undesirably change, because of the input –output delay of the inverting multiplexer, we have a (00) or (11) on (EX1, EX2), that is a noncodeword of the two-rail code. In particular, in the case of CFs resulting in the presence of a spike on the flip-flop input datum, the duration of the error message provided on (EX1, EX2), denoted by dER, is given by the following relationships: † if dMUX , dTRi # dMUX ; dER ¼ dTRi ; † if dTRi . dMUX ; dER ¼ dMUX ; where dTRi denotes the duration of the crosstalk-due spike (evaluated at the logic threshold of the fan-out gates), while dMUX is the input – output delay of the multiplexer and dMUX is the multiplexer inertial delay. Of course if dMUX $ dTRi ; the spike is filtered out by the input multiplexer and no error indication should be given. Instead, in the case of DFs or CFs resulting in a delayed transition of the flip-flop input datum, dER ¼ dMUX : In order not to risk to miss any error message, independently of the fan-out logic, a proper additional stage should be connected to the considered switches. Such a stage should: (i) if (EX1, EX2) ¼ 01 or 10, give output codewords; (ii) if (EX1, EX2) ¼ 00 or 11, give an output non-codeword and keep on giving output non-codewords until a suitable reset signal (RES) is activated, independently of the possible disappearance of the input noncodeword. In particular, such a reset signal will allow to start again the operation of our scheme, once fault detection and possible recovery are accomplished. Blocks of this kind are widely used in the case of self-checking circuits, and various designs have been up to now proposed [17,23,24]. At system level, depending on the considered application, the two additional outputs of all scan flip-flops could then be joined together by means of a conventional two-rail code checker, in order to provide a global error message, or
As an example of a possible application of our idea, we here consider the case of the scan flip-flop of the ES2 Standard Library (Fig. 3) [25]. The derived scan flip-flop is shown in Fig. 4 where as an example, we have considered the EI block implemented as in Ref. [17]. In particular, in Fig. 4, EN0 (CK0 ) denotes the complement of signal EN (CK), and RES and RES0 are the reset signal and its complement, respectively. We can easily verify that, in the case of a CF or DF affecting the input signal D and making the driven flip-flop sample an incorrect datum, a (00) or (11) is temporarily given to the input of the additional hardware, which results in the occurrence of an error indication on nodes (ER1, ER2), where it remains latched until reset.
5. Verification Our derived modified scan flip-flop has been implemented considering a standard 0.18 mm CMOS technology and designed with the following transistor aspect ratios: (i) ðW=LÞn ¼ 1 and ðW=LÞp ¼ 4:5; for the inverters and transfer gates; (ii) ðW=LÞn ¼ 2 and ðW=LÞp ¼ 9; for the series transistors of the scan flip-flop; (iii) ðW=LÞn ¼ 1:6 and ðW=LÞp ¼ 7; for the transistors of the feedback inverting gates. As an example, we have considered an EN signal, which remains ¼ 1 for a time interval equal to the sum of the scan flip-flop set-up and hold times. The behavior of our modified flip-flops has been verified by means of conventional and Monte Carlo electrical simulations, considering possible statistical variations (with uniform distribution) of electrical parameters and power supply up to the 20%. As for the parasitic coupling, we have considered the model in Ref. [2].
Fig. 3. Scan flip-flop of the ES2 Standard Library considered here as an example.
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Fig. 6. Example of the results obtained for the case of an input delay (due to a DF or CF) making the flip-flop produce an incorrect output datum.
Fig. 4. Modified scan flip-flop of the ES2 Standard Library.
The results achieved under nominal values of electrical parameters and considering fault-free conditions are reported in Fig. 5. We can easily see that our modified flip-flop provides an output indication of correct operation ðER1 – ER2Þ: Instead, Fig. 6 shows the results obtained in the case of a delay in the transition of the scan flip-flop input (due to a DF or CF affecting such an input) and making the flip-flop provide an incorrect output datum. As can be seen, an output error indication is produced ðER1 ¼ ER2 ¼ 1Þ: Similarly, Fig. 7 shows the results obtained in the case of a CF affecting the scan flip-flop input and resulting in an input spike. As can be seen, also in this case, an output error indication is produced ðER1 ¼ ER2 ¼ 1Þ:
Fig. 5. Example of the results obtained for the fault-free case.
Similar results have been obtained considering possible statistical variations (with uniform distribution) of electrical parameters and power supply up to the 20%. We should note (Fig. 5) that the proposed additional hardware provides the output indication concerning the correctness of the flip-flop output datum simultaneously with the sampled output datum itself, thus allowing (at the system level) to possibly avoid the propagation of incorrect data (due to input CFs or DFs) to the fan-out logic. Of course, to detect the possible incorrectness of the flipflop output because of logical faults (e.g. stuck-ats), a conventional off-line testing technique or conventional selfchecking techniques could be adopted.
6. Costs and sensitivity Let us discuss the costs of our scheme in terms of speed, possible impact on system’s performance and area overhead, as well as the fault sensitivity of our modified flipflops. As for speed, the input –output delay of our scheme (d ) with respect to the instant of fault activation is given by:
Fig. 7. Example of the results obtained in the case of a crosstalk fault affecting the scan flip-flop input and resulting in an input spike.
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d ¼ dTG þ 3TNOT ; where dTG is the input – output delay of a conductive transfer gate, while TNOT is the input –output delay of the additional hardware inverter. This high speed in fault detection allows us to obtain the output indication concerning the correctness of the flip-flop output datum simultaneously with the sampled output datum itself, thus allowing (at the system level) to possibly avoid the propagation of incorrect data (due to input CFs or DFs) to the fan-out logic. As for the impact on system’s performance, we should consider that our additional hardware is conceived as operating in parallel with the system’s flip-flops. Therefore, its impact on performance is basically due only to the increase in the flip-flop input capacitive load, which can be considered negligible. As for our scheme sensitivity to faulty (i.e. delayed or undesired) transitions of the input datum (due to DFs or CFs), our scheme is conceived as able to detect on-line all transitions that occur when EN ¼ 1: In particular, delayed transitions (e.g. due to DFs or CFs) are always detected. As for spurious transitions (e.g. due to CFs), instead, they are detected if they are not filtered out by the MUX’s inertial delay. It should be noted that filtered transitions do not affect the value sampled by the flip-flops, so that it is desirable not to detect them. As for the interval during which EN ¼ 1, as already introduced, it should be chosen on the basis of timing and failure analysis, in order to guarantee the detection of all faulty transitions which prevent the flip-flop from providing the correct output signal, thus possibly compromising the system’s correct operation. As for area, our modification of course implies an increase which, however, is lower than that required by any other on-line testing strategy [15,16,18] possibly adopted to address the here considered problem. Of course, in the case of systems featuring a huge number of flip-flops and fullscan, the area overhead due to our flip-flop modification may be high. In this case, timing analysis can be used to identify those signals which are on critical paths, thus being more exposed to the effects of delay and crosstalk faults. The use of the proposed flip-flop modifications can then be applied only to the scan flip-flops sampling such signals.
7. Self-checking ability We have considered a set of faults (F0 ) possibly affecting our additional hardware composed of all possible node stuck-ats (SAs), transistor stuck-ons (SONs), transistor stuck-opens (SOPs), resistive bridgings (BFs), crosstalks (CTs), delays (DFs) and transient faults (TFs). We have referred to the following fault assumptions [26], generally considered in case of self-checking circuits: (1) faults occur one at a time; (2) the time elapsing between the occurrence of two following faults is long enough to allow the application of all possible input codewords. Of course,
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assumption (2) can be reasonably changed into the assumption that the time elapsing between the occurrence of two following faults is long enough to allow the application of all possible scan flip-flop inputs. To guarantee the self-checking behavior of our additional hardware, we must verify that, with respect to the possible internal faults, it satisfies the Totally Self-Checking (TSC) [27] or SCD [19] property. We have verified that our additional hardware is SCD with respect to all possible internal SAs, SONs, SOPs, BFs, CFs, DFs and TFs, but the SOPs possibly affecting the feedback inverting gates. As for these undetectable faults, we should consider that SOPs have been found less likely to occur than the other listed kinds of faults [20], and that their occurrence probability can be further reduced by properly designing the circuit layout [21]. The analyses performed for the different kinds of possible faults are summarized in Sections 7.1– 7.3. 7.1. Node stuck-at faults SAs might affect: (i) signal EN or EN0 (that we assume independently generated); (ii) input/output nodes of the used inverters; (iii) input/output nodes of the feedback inverting gates. The SA1 of kind (i) affecting EN makes the transfer gates always conductive, therefore also when signal transitions are actually allowed. Consequently, our scheme provides an output error message and is TSC (therefore also SCD) with respect to this SA. The SA0 of kind (i) affecting EN makes the n-channel pass-transistors of both transfer gates not conductive. Thus, only the p-channel pass-transistors are conductive when EN ¼ 1. When this is the case, the different ability of pchannel pass-transistors to transfer a high and a low logic value makes signal propagation delays through the pchannel pass-transistors asymmetric. Consequently, an error indication ((00) or (11)) is given to the input of the feedback inverting gates and an error indication is produced at the output of our scheme. Therefore, our scheme is TSC (hence SCD) with respect to the considered SA. Similar considerations hold true for the SA0/1 of kind (i) affecting EN0 . As for SAs of kinds (ii) and (iii), it can be easily verified that they result in the generation (and memorization) of an error message. Therefore our scheme is TSC (hence SCD) with respect to these faults. 7.2. Transistor stuck-on and stuck-open faults SONs might affect a transistor of: (i) the transfer gates; (ii) the proposed additional hardware inverters; (iii) the feedback inverting gates. SONs of kind (i) make a pass-transistor be conductive also in the time intervals during which transitions of the scan flip-flop input signal are allowed. Thus, the same
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considerations as for the SA1 of kind (i) affecting EN hold true. Depending on the circuit electrical level design, SONs of kind (ii) may, or may not, result equivalent to SAs of kind (ii). When this is the case, of course, the same considerations as for SAs of kind (ii) hold true. Instead, when they are not equivalent to such SAs, they are undetected. However, our scheme does not loose its ability to reveal the occurrence of logic errors due to CFs or DFs. Moreover, if other faults [ F0 occur, our additional hardware either gives an error indication, or does not loose its ability to detect the occurrence of logic errors due to CFs or DFs. Thus our scheme is SCD with respect to such SONs. Finally, SONs of kind (iii) result in an error message, that is consequently memorized. Hence, our proposed hardware is TSC (hence SCD) with respect to them. Now let us consider the possible SOPs, which might affect a transistor of: (i) the transfer gates; (ii) the scheme inverters; (iii) the feedback inverting gates. As for SOPs of kind (i), considerations similar to those as for the SA0 of kind (i) affecting EN hold true. Thus, our scheme is TSC (hence SCD) with respect to such faults. As for SOPs of kind (ii), they result in an incorrect logic value at the output of the faulty inverter (that retains the previously charged logic value). Thus, considerations similar to those for SAs of kind (ii) hold true, and our scheme is TSC (hence SCD) with respect to these faults. SOPs of kind (iii), instead, cannot be detected and our scheme is neither TSC, nor SCD with respect to them. However, SOPs have been verified to be less likely to occur than the other kinds of faults considered here [20]. Moreover, their likelihood can be further reduced by suitably designing the circuit layout [21].
behaving as if fault-free. Therefore, our scheme is SCD with respect to possible BFs. As for CTs affecting our proposed additional hardware, we have verified that our scheme either provides an output error message, or maintains its ability to reveal CFs or DFs that affect the scan flip-flop input line. Therefore, our proposed additional hardware is SCD with respect to CTs. Similar considerations hold true also for TFs and DFs affecting our proposed hardware, with respect to which the SCD property is therefore satisfied.
7.3. Resistive bridging, crosstalk, delay and transient faults
[1] Semiconductor Industry Association, San Jose, CA, The 2001 national technology roadmap for semiconductors, 2001. [2] F. Moll, A. Rubio, Methodology of detection of spurious signals in VLSI circuits, Proc Eur Des Test Conf (1993) 491 –496. [3] W. Chen, S.K. Gupta, M.A. Breuer, Analytic models for crosstalk delay and pulse analysis under non-ideal inputs, Proc IEEE Int Test Conf (1997) 809–818. [4] W. Chen, S.K. Gupta, M.A. Breuer, Test generation in VLSI circuits for crosstalk noise, Proc IEEE Int Test Conf (1998) 641– 650. [5] M. Abramovici, J. Kulikowski, R. Roy, The best flip-flops to scan, Proc IEEE Int Test Conf (1991) 166 –173. [6] C. Lin, Y. Zorian, S. Bhawmik, PSBIST: a partial-scan based built-in self-test scheme, Proc IEEE Int Test Conf (1993) 507–516. [7] M. Abramovici, P. Parikh, B. Mathew, D. Saab, On selecting flip-flops for partial reset, Proc IEEE Int Test Conf (1993) 1008–1012. [8] K. Lin, C. Chen, T. Hwang, Layout-driven chaining of scan flip-flops, IEE Proc Comput Dig Tech (1996) 421–425. [9] F. Corno, P. Prinetto, M. Rebaudengo, M.S. Reorda, Partial scan flip flop selection for simulation-based sequential ATPGs, Proc IEEE Int Test Conf (1996) 558 –564. [10] I. Ghosh, A practical method for selecting partial scan flip-flops for large circuits, VLSI Des (1996) 284– 288. [11] J. Savir, Scan latch design for delay test, Proc IEEE Int Test Conf (1997) 446 –453. [12] S. Chang, K. Lee, Z. Wu, W. Jone, Reducing test application time by scan flip-flops sharing, IEE Proc Comput Dig Tech (2000) 42–48.
As for possible BFs affecting the proposed additional hardware, electrical level simulations have been performed by means of HSPICE considering, for each BF, values of the connecting resistance the interval ]0, 6 kV] [28]. We have verified that: (i) for the largest fraction of BFs, our additional hardware gives an output error message for all the considered values of R; (ii) for the BFs (or the BF values) not resulting in an output error message, our scheme maintains its ability to detect the occurrence of logic errors due to CFs or DFs that affect the flip-flop input signal. Moreover, if BFs of kind (ii) are followed by other faults [ F0 , our additional hardware either gives an output error message, or maintains its ability to detect the occurrence of logic errors due to CFs or DFs that affect the scan flip-flop input signal. Similarly, BFs involving lines of the additional hardware used for different scan flip-flops either result in the generation of an output error message, or do not affect (from the logical and dynamical point of view) our scheme correct operation. In this last case, if following faults occur, either an error message is produced, or our scheme keeps on
8. Conclusions We have presented a possible modification to the internal structure of scan flip-flops which allows the on-line detection of DFs and CFs affecting their input data. The proposed solution allows to obtain, at the flip-flop output, together with the output datum, an indication denoting whether or not the provided datum is incorrect, because of an input crosstalk or delay fault. The proposed solution can be used for the scan flip-flop normal operation input and test input. A full-custom VLSI design of the proposed solution has been presented. However, standard cell based designs can be also easily conceived. The proposed solution features self-checking ability with respect to a wide set of possible internal faults, including node stuck-ats, transistor stuck-ons and stuck-opens, resistive bridgings, delays, crosstalks and transient faults.
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