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Schottky barrier height of sputtered TiN contacts on silicon
World Abstracts on Microelectronics and Reliability Mfg Technol. CHMT-7, 411 (1984). A thermal stress-free package make of a SiC (silicon carbide) substrate for flip-chip devices has been developed. The thermal expansion coefficent (TEC) of SiC is extremely close to that of silicon, and it has a higher thermal conductivity than BeO. The package was made by the sputtering of Cr-Cu-Cr, photoetching, flip-chip bonding, and attachment of the outer pins on the substrate. A thermal cycle test indicated that the package had characteristics superior to those of alumina packages. In
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addition measurement of the thermal resistance indicated 4.0°C/W for 0/f (junction-to-fin thermal resistance), and 5.7°C/W for Oja in an airflow of 4m/s. These values were about half of those of an alumina package. Moreover a thermal cycle test using a 66x66mm package and 48 x 48 mm silicon chip indicated that a SiC substrate might be usable for the package of a large-size large-scale integrated (LSI) chip. A more detailed description of.the package and the results of our studies are presented and discussed here.
7. SEMICONDUCTOR INTEGRATED CIRCUITS, DEVICES AND MATERIALS Effects of oxygen and internal gettering on donor formation. DINESH C. GUPTA and ROBERT B. SWAROOP. Solid St. Technol. 113 (August 1984). Thermal donors in silicon greatly influence CMOS parameters, especially if fabrication includes low temperature processing (400-500°C). The formation of thermal donors is directly proportional to the amount of initial oxygen present. It is also dependent on the amount of free oxygen available in silicon prior to low temperature processing. Czochralski crystal growth procedures make it difficult to grow silicon with the low oxygen content that is required to eliminate thermal donors. Internal gettering methods are therefore recommended. The creation of a negligible oxygen zone (known as the denuded zone) by precipitating interstitial oxygen into SiOx sites underneath the zone leaves little free oxygen for thermal donor formation. This technique has been tried successfully in CMOS processing. Observation of discrete donor-accept pair spectra in MBE grown GaAs. D. C. R.EYNOLDS,K. K. BAJAJ, C. W. LITTON, E. B. SMITH,W. T. MASSELINK,F. FISCHERand H. MORKOC. Solid St. Commun. 52, 685 (1984). We report the first observation of discrete donor-acceptor pair photoluminescence spectra in GaAs. Sixty sharp lines are observed in the region between 1.5110-1.5040eV. These are interpreted as discrete donor-acceptor pair lines resulting from preferential pairing. The pairs are believed to result from silicon on the gallium sublattice and carbon on the arsenic sublattice. Schottky barrier height of sputtered TiN contacts on silicon. M. FINETTI, 1. SUNI, M. BARTUR, T. BANWELL and M.-A. NICOLET. Solid-St. Electron. 27, 617 (1984). The Schottky barrier height of sputtered TiN on both p-and n-type silicon was determined by I-V and C-V measurements. The barrier height is found to increase on n-Si and to decrease on p-Si, upon thermal annealing. The experimental results are explained in terms of sputtering damage. This damage is modeled by donor-like traps whose concentration decays exponentiallYofrom the silicon surface. A characteristic length equal to 45 A accounts for the observed characteristics. The trap-free values of the barrier height were obtained by I-V measurements after sequential thermal annealing up to 600°C. These values are qSBn= 0.55V on n-type and ~bBp = 0.57 V on p-type silicon. Characterization of semiconductor materials and devices by surface analysis techniques. A. VANOOSTROM.Vacuum 34, 881 (1984). In this review we consider some major surface analysis techniques: Rutherford backscattering (RBS); Auger electron spectroscopy (AES); X-ray photoelectron spectroscopy (XPS); ion scattering spectrometry (ISS) and secondary ion mass spectrometry (SIMS). Combined with ion bombardment for in-depth profiling some of these techniques provide three-dimensional composition distributions in a thin film. New instrumental developments are smaller electron and ion beam sizes and the increased use of position sensitive detectors. Spatial resolution and
quantitative aspects are discussed; examples used are taken from semiconductor materials and device work.
A melting model for pulsed laser heating of silicon. J. M. COLE, P. HUMPHREYSand L. G. EARWAKER.Vacuum 34, 871 (1984). The laser melting of silicon has been modelled by computer solution of the heat equation. Best values of input data have been taken from the literature. An amorphous thermal conductivity significantly smaller than that of crystalline silicon and a melting point depression of amorphous silicon of 285 K with respect to crystalline silicon has been used in accordance with recent suggestions, the computer calculations are in good agreement with experimental results for both melting thresholds and melt depths. The model predicts that the maximum melt depths attained when pulses of constant energy density are applied, do not depend on the pulse duration for various amorphous and crystalline silicon combinations. The melting thresholds for both crystalline silicon and silicon with amorphous surface layers increase slightly with increasing pulse lengths. An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI. CHING-YUAN Wu and SHuI-YUANYANG.Solid-St. Electron. 27, 651 (1984). Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (
1171
addition measurement of the thermal resistance indicated 4.0°C/W for 0/f (junction-to-fin thermal resistance), and 5.7°C/W for Oja in an airflow of 4m/s. These values were about half of those of an alumina package. Moreover a thermal cycle test using a 66x66mm package and 48 x 48 mm silicon chip indicated that a SiC substrate might be usable for the package of a large-size large-scale integrated (LSI) chip. A more detailed description of.the package and the results of our studies are presented and discussed here.
7. SEMICONDUCTOR INTEGRATED CIRCUITS, DEVICES AND MATERIALS Effects of oxygen and internal gettering on donor formation. DINESH C. GUPTA and ROBERT B. SWAROOP. Solid St. Technol. 113 (August 1984). Thermal donors in silicon greatly influence CMOS parameters, especially if fabrication includes low temperature processing (400-500°C). The formation of thermal donors is directly proportional to the amount of initial oxygen present. It is also dependent on the amount of free oxygen available in silicon prior to low temperature processing. Czochralski crystal growth procedures make it difficult to grow silicon with the low oxygen content that is required to eliminate thermal donors. Internal gettering methods are therefore recommended. The creation of a negligible oxygen zone (known as the denuded zone) by precipitating interstitial oxygen into SiOx sites underneath the zone leaves little free oxygen for thermal donor formation. This technique has been tried successfully in CMOS processing. Observation of discrete donor-accept pair spectra in MBE grown GaAs. D. C. R.EYNOLDS,K. K. BAJAJ, C. W. LITTON, E. B. SMITH,W. T. MASSELINK,F. FISCHERand H. MORKOC. Solid St. Commun. 52, 685 (1984). We report the first observation of discrete donor-acceptor pair photoluminescence spectra in GaAs. Sixty sharp lines are observed in the region between 1.5110-1.5040eV. These are interpreted as discrete donor-acceptor pair lines resulting from preferential pairing. The pairs are believed to result from silicon on the gallium sublattice and carbon on the arsenic sublattice. Schottky barrier height of sputtered TiN contacts on silicon. M. FINETTI, 1. SUNI, M. BARTUR, T. BANWELL and M.-A. NICOLET. Solid-St. Electron. 27, 617 (1984). The Schottky barrier height of sputtered TiN on both p-and n-type silicon was determined by I-V and C-V measurements. The barrier height is found to increase on n-Si and to decrease on p-Si, upon thermal annealing. The experimental results are explained in terms of sputtering damage. This damage is modeled by donor-like traps whose concentration decays exponentiallYofrom the silicon surface. A characteristic length equal to 45 A accounts for the observed characteristics. The trap-free values of the barrier height were obtained by I-V measurements after sequential thermal annealing up to 600°C. These values are qSBn= 0.55V on n-type and ~bBp = 0.57 V on p-type silicon. Characterization of semiconductor materials and devices by surface analysis techniques. A. VANOOSTROM.Vacuum 34, 881 (1984). In this review we consider some major surface analysis techniques: Rutherford backscattering (RBS); Auger electron spectroscopy (AES); X-ray photoelectron spectroscopy (XPS); ion scattering spectrometry (ISS) and secondary ion mass spectrometry (SIMS). Combined with ion bombardment for in-depth profiling some of these techniques provide three-dimensional composition distributions in a thin film. New instrumental developments are smaller electron and ion beam sizes and the increased use of position sensitive detectors. Spatial resolution and
quantitative aspects are discussed; examples used are taken from semiconductor materials and device work.
A melting model for pulsed laser heating of silicon. J. M. COLE, P. HUMPHREYSand L. G. EARWAKER.Vacuum 34, 871 (1984). The laser melting of silicon has been modelled by computer solution of the heat equation. Best values of input data have been taken from the literature. An amorphous thermal conductivity significantly smaller than that of crystalline silicon and a melting point depression of amorphous silicon of 285 K with respect to crystalline silicon has been used in accordance with recent suggestions, the computer calculations are in good agreement with experimental results for both melting thresholds and melt depths. The model predicts that the maximum melt depths attained when pulses of constant energy density are applied, do not depend on the pulse duration for various amorphous and crystalline silicon combinations. The melting thresholds for both crystalline silicon and silicon with amorphous surface layers increase slightly with increasing pulse lengths. An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI. CHING-YUAN Wu and SHuI-YUANYANG.Solid-St. Electron. 27, 651 (1984). Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (