Second breakdown in high voltage MOS transistors

Second breakdown in high voltage MOS transistors

Solid-State Elecmnics. 1977, Vol. 20, pp. 875478. Pergamon Press. Printed in Great SECOND BREAKDOWN Britain IN HIGH VOLTAGE Surinder General El...

212KB Sizes 0 Downloads 298 Views

Solid-State Elecmnics.

1977, Vol. 20, pp. 875478.

Pergamon Press. Printed in Great

SECOND BREAKDOWN

Britain

IN HIGH VOLTAGE

Surinder General

Electric (Received

The characteristics it an attractive interest

in this device

In many cases,

has centered

conditions

description

conditions

conditioning

systems

cy and light weight

may be of a nature

Usually,

will be discussed current

regulators,

investigations

injection

is determined

of this phenomenon

process.

field that triggers

by the high concentration

of mobile

The conditions

current density,

jcrit and associated

is a

to

as

transisand

of the electric in the drain

for second breakdown

(1, 3).

To a first order

space charge necessary

to

is given by (1, 2):

ND and WD are the donor concentration la, EC is the critical velocity

described

space charge

necessary

approximation,

injection

efficien-

impact ionization,

The spatial distribution

and experimentally

the critical

power

the full voltage

in diodes and bipolar

both analytically

vs is the saturated

In numerous

the path is not long enough

to occur have been verified

trigger avalanche

of the MOSFET under

Even so, the device may fail due to a mechanism

by an avalanche

locus, the

from an "on" to "off" state that

the time taken to traverse

space, and the voltage drop in this region.

mences

switch.

in three parts,

etc., high operating

the full current, while maintaining

that it is an intense electric

seen in Figure

More recent

such that it

voltage

and a high voltage.

the transition

tors (2), suggest,

where

make

The V-I locus of the power switch in such circuits

It is during

to conduct

heat.

choppers,

Recent

field intensity

as a high voltage

and, the physics

process,

second breakdown.

is followed

usefulness

the necessary

of a high current density

are necessary.

is required

substantial

to produce

such as inverters,

its terminals.

produce

applications.

in MOS transistors

required

loop as given in (1).

across

and memory

locus of the transistor

of the second breakdown

simultaneous

the device

(MOS) transistor

of the device due to second breakdown.

viz., the circuit

square

Semiconductor

on its potential

The subject of second breakdown

physical

Metal-Oxide

for use in linear, digital

the voltage-current

leads to failure

Krishna

Company - Corporate Research & Development Schenectady, NY 12301 20 May 1977; in revised form 28 July 1977)

of a conventional

component

MOS TRANSISTORS

electric

of electrons

and the rise in current

through

and width

of the drain

space respectively,

field for impact ionization

in the high field.

the device 875

Once avalanche

is not controlled,

as

( w LO5 V/cm), and injection

it inevitably

com-

results

876

Communications

INVERSION LAYER

,lNVERSION LAYER

I

) REPLETION LAYER

Figure

la:

ELECTRON SPACE CHARGE

sistor,

+

DEPLETION LAYER

"V;

Figure

tran-

Cross section of a D-MOS

tor for superior capability,

0.1 pm (9)

the drain

adequately,

but were

the saturation

between drain

electric

interface

now repels

include

two dimensions,

(10).

In an effort

grated

circuits,

MOS structure Depletion

with a wide drain such structures, To account

Studies

in an increase D'

for mobile

the electric

space charge

current

=

"C e(y)

The current

in the bulk.

The

in

has been extended

the density

tc

effects in inteThe D-

of an Enhancement

and a

that, the short channel

capability,

may also be combined

The breakdown

been reported

the expression

to the

layer of the

been developed.

indicate

has recently

21 2L

region and

(8, 9), and hot electron

connection

in source drain current

PC ojds

(1).

(SCL) flow which

the analysis

have recently

of the E/D structure

space charge, we modify

carried

and increase

performance,

conditions

ir

(6, 7) by the

in the drain region.

Further,

as a hybrid

density

field normal

in the inversion

that could support a high voltage.

under electrostatic

the pinch-off

is, therefore,

transistor

la may be considered

region W

surface

field.

for mobile

(11) and V-MOS

(E/D) device.

length that results

electric

given by Eq.

region was described

as having Space-Charge-Limited

to account

the D-MOS

to explain

charge

terminal

to raise the power-speed

of Figure

mode

mobile

from the silicon

the longitudinal

second breakdown

the source region of the channel

In this situation,

region and the drain

space has been analyzed

turn influences

field.

in attempts

the pinch-off

that accumulates

the charge

the pinch-off

Later,

of a MOS transis-

d FJ 1 to 10 pm

the critical value

(4, 5) described

successful

(VD > VC).

of transverse

can exceed

physics

not quite

stage

silicon dioxide channel,

in MOS device

ELECTRON SPACE CHARGE

It will be shown that the current

of the transistor.

space of the MOS transistor

Early works

reversal

failure

I

Cross section

lb:

e(y) varies from 0.01 to

in the catastrophic

,

I

voltage

of

(12).

for channel

current

(2)

(5):

877

Communications

C ox

is the capacitance per unit area, L the length of the channel, and 6(y) accounts for any

spreading of the space charge as it is transported across the drain space. Investigations of Popa (9) show that the space charge density is only a function of gate voltage, and independent of drain voltage VD, and drain space length WD.

Choosing the minimum current den-

sity (which actually occurs at the drain contact) as prevailing over the entire length WD, reduces the problem to one dimension, and provides a conservative estimate of j,s. In the in the structure given with a lightly doped drain region, the breakdown voltage, V BR' absence of mobile charge:

'SBR "

(3)

Ec 'D

Combining Eqs. (1) and (2) where jds"

jcrit gives the breakdown voltage, VSBR, in the

presence of mobile charge:

V SBR "

If 'SBR < 'BR'

EL 6 c sivs jds -qvs%

the voltage switching of the MOS transistor is limited by second breakdown.

Consider a MOS transistor with the following parameters: SiO2 thickness = 0.6 pm, L = 10 pm, wD

14 = 50 pm, ND s 10 cmw3, VG = 10 volts, B(y) r 700 12 (9), pn

= 200 cm2/volt-sec. From

Eq. (2), jds z 7900 A/cm2, from Eq. (3) VBR = 500 V, and from Eq. (4) VSBR?

14V. Clearly

such a device would be severely limited in its ability to switch voltage (in the presence of full current) by second breakdown. In spite of the gross assumptions that, Ec is independent of the charge concentration,and the unmodulated drain resistivity is nearly intrinsic; it would take significant deviations from the value of B(y) used in the above example, before VSBR-+VBR' A large divergence of the current density jds, appears unlikely in the D-MOS and V-MOS structures because even though the mobile charge is repelled from the interface, as mentioned earlier, conduction is at or very near the silicon/silicondioxide surface. A superior structure, for the reduction in jds, and therefore an increase in the second breakdown voltage VSBR, is given in Figure lb. The voltage and the electric field are now present in the bulk, the distance 'd' determines the punch-throughvoltage between gate and drain, and also determines the drain current density jds. The dimensions of 'd' are of the order of microns compared to 0(y) w 0.01 to 0.1 microns in the conventional MOS transistor, and one may therefore expect a considerable improvement in the threshold for second breakdown.

The structure of Figure lb should have a power-speed performance comparable to the

D-MOS/V-MOS devices, with significant improvements, however, in packing density and second breakdown capability.

878

Communications References

(1) S. Krishna and P. L. Hower, Proc. IEEE, 6l, 393 (1973). (2) P. L. Hower and V.G.K. Reddi, IEEE Trans. Electron Dev.,ED_17, 322 (1970). (3) B. A. Beatty, S. Krishna and M. S. Adler, IEEE Trans. Electron Dev.,ED_23, 851 (1976) (4) H.K.J. Ihantola and J. L. Mall, Solid State Electronics, 1, 423 (1964). (5) S. R. Hofstein and F. P. Heiman, Proc. IEEE, 5l, 1190 (1963). (6) J. E. Schroeder and R. S. Muller, IEEE Trans. Electron Dev., ED_15, 954 (1968). (7) H. W. Loeb, R. Andrew and W. Love, Electronics Letters, 5, 352 (1968). (8) G. Merckel, J. Bore1 and N. Cupcia, IEEE Trans. Electron Dev., ED-19, 681 (1972). (9) A. Popa, IEEE Trans. Electron Dev., ED_19, 774 (1972). (10) G. A. Armstrong and J. A. Magowan, Solid State Electronics, 14, 723 (1971). (11) H. Masuda, T. Masuhara, M. Nagata and N. Hashmito, Proc. 4th Conf. on Solid State Devices, Tokyo, 1972. (12) M. J. Declercq and J. D. Plumner, IEEE Trans. Electron Dev., ED-23, 1 (1976).