- Email: [email protected]
Selective-area growth of pulse-doped InAs nanowires on Si and vertical transistor application
Journal of Crystal Growth 500 (2018) 58–62
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Selective-area growth of pulse-doped InAs nanowires on Si and vertical transistor application
T
⁎
Hironori Gamo , Katsuhiro Tomioka Research Center for Integrated Quantum Electronics (RCIQE), Graduate School of Information Science and Technology, Hokkaido University, North 14 West 9, Sapporo 060-0814, Japan
A R T I C LE I N FO
A B S T R A C T
Communicated by Yasuyuki Miyamoto
III-V compound semiconductors are promising channel materials for the future low-power and high-performance transistor because of their high electron/hole mobility. Here, we report on the integration of vertical InAs nanowire (NW)-channels on Si by selective-area metalorganic vapor phase epitaxy (MOVPE) with a pulse doping technique and demonstration of an InAs NW vertical surrounding-gate transistors. The device had a small subthreshold slope of 68 mV/decade, a normalized transconductance of 0.25 μS/μm, and on/off ratio of around 107. The axial junction with the pulse doping effectively suppressed off-state leakage current resulting in good electrostatic gate control.
Keywords: A1. Nanostructures A3. Metalorganic vapor phase epitaxy A3. Selective epitaxy B1. Nanomaterials B3. Field effect transistors
1. Introduction Sillicon-based integrated circuits are facing growing problems with size-scaling of field-effect transistors (FETs), such as increased off-state leakage current and power density per chip. Fast channel materials are expected to be alternatives for achieving FETs that have high Ion with low off-state leakage current under low bias [1–8]. Meanwhile, the vertical surrounding-gate architecture realizes high packing density and good electrostatic gate control [6,9]. Vertical III-V compound semiconductor nanowires (NWs) directly grown on Si platforms are, therefore, promising channel materials because they have higher electron/ hole mobilites compared with Si and can be used to implement the vertical surrounding-gate architecture. In addition, NWs can relax stress originating from the lattice mismatch because of their small footprint [10]. We recently, demonstrated direct integration of vertical InAs NWs on Si by selective-area metalorganic vapor phase epitaxy (SA-MOVPE) [11–13] and vertical surrounding-gate transistors (VSGTs) [3]. Improvements to the electrostatic characteristics of the InAs NW channels, especially the subthreshold slope (SS) and off-state leakage current, are still inherent challenges because the InAs has a narrow band gap and high electron mobility that would result in a very high off-leakage current. The dominant contribution to the off-state leakage is from source-drain band-to-band tunneling. In this study, we investigated the effect on the leakage current of adding Zn and Sn pulsed-doped layers to InAs NW vertical surrounding-gate FETs (VSGTs) on Si. We observed
⁎
Corresponding author. E-mail address: [email protected] (H. Gamo).
https://doi.org/10.1016/j.jcrysgro.2018.07.035
Available online 06 August 2018 0022-0248/ © 2018 Elsevier B.V. All rights reserved.
a considerable improvement in the subthreshold slope (SS) compared with undoped-InAs NW-channel VSGTs [3]. 2. Experimental procedure InAs NWs were grown on n-type Si(1 1 1) (resistivity of 1000 Ω·cm). First, 20-nm-thick SiO2 film was formed on the substrates by thermal oxidation. Periodical mask openings were formed using electron beam lithography and dry and wet etchings. RCA cleaning was used to improve the surface quality of the SiO2 film. Next, InAs NWs were selectively grown on the partially masked substrate in a horizontal MOVPE system at a working pressure of 0.1 atm. Trimethylindium (TMIn) and arsine (AsH3) were supplied as the source precursors. Diethlyzinc (DEZn) was used as the p-type dopant source, while monosilane (SiH4) and tetraethlytin (TESn) were used as the n-type dopant sources. The partial pressures of TMIn and AsH3 were respectively 9.7 × 10−7 and 2.5 × 10−4. The growth temperature was 550 °C, and the V/III ratio was 256 [11–14]. The Zn-pulse-doped layer was grown for 5 min, followed by Si-doped InAs growth for 3 min and growth of a Sn-pulsedoped layer for 5 min. We fabricated InAs NW-VSGT with high-k/metal surrounding gate [1,3,8]. After the growth, atomic layer deposition (ALD) was used to form a 10-nm-thick Hf0.8Al0.2O layer on the whole surface of the NWs. Second, gate metal (tungsten, W) was formed by radio frequency sputtering and contact pads were made by photolithography and wet etching. The NWs were then covered with benzocyclobutene (BCB)
Journal of Crystal Growth 500 (2018) 58–62
H. Gamo, K. Tomioka
Fig. 1. (a) Schematic illustrations of gas-flow and temperature sequence for InAs nanowire growth on Si. (b) Diagram of Zn- and Sn-pulse doping technique. DEZn was supplied for 2 s during undoped InAs growth for 10 s and TESn was supplied for 1 s during undoped InAs growth for 6 s. This Zn- and Sn-pulse doping sequence is repeated 30 and 50 times, respectively. (c) 30° tilted SEM image of the NW array.
Fig. 2. (a) Schematic cross-sectional structure of NW-VSGT. (b) Transfer characteristics. The measured current is divided by the number of NWs and normalized with the NW circumference. (c) Output characteristics. The gate voltage is changed from −1 V to 1 V in steps of 0.25 V. (d) Normalized transconductance for VDS = 0.50 V. Transfer characteristics for VDS = 0.5 V. Inset: The threshold voltage VT is estimated to be 0.29 V by using a linear extrapolation (red line). (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
InAs NW-VSGTs were annealed at 350 °C in N2 for Ohmic contacts in the source and drain regions.
formed by spin-coating and etched back to the desired thickness by reactive ion etching (RIE). Next, an isolation layer between gate and drain was formed by BCB. Drain and source metals were evaporated on the top of the NWs and back side of the substrate. The drain and source metals were Ni/Ge/Au/Ni/Au and Ni/Au, respectively. Finally, the 59
Journal of Crystal Growth 500 (2018) 58–62
H. Gamo, K. Tomioka
Fig. 3. (a) Subthreshold swing (SS). The minimum SS is 68 mV/decade for VDS = 0.50 V. (b) Gate current for VDS = 0.5 V. (c) Comparison of the SS versus off-state current, Ioff for VDS = 0.5 V. The green dots indicate off-state current without normalization. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
Fig. 4. (a) TEM image of HfAlO-covered InAs NWs on Si. (b) High-resolution TEM image of the InAs/HfAlO interface (red dashed line in Fig. 4(a)). Twins were introduced with a 1–4 monolayer period. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
3. Results and discussion
{−1 1 0} vertical facets. Carrier transport would occur on the {−1 1 0} surfaces. InAs is unintentionally doped by carbon, with typical carrier concentrations of 1016–1017 cm−3 [15]. The Zn-pulsed doping was used to compensate for the unintentional carbon dopants in the InAs NWs, while the Sn-pulsed doping was used to form heavily doped n-type InAs NWs and at the same time maintain the uniform shapes of the NW channels [15,16]. The InAs NW channel made with Zn-pulsed doping should shift the threshold voltage, while the n+ contact layer made with Sn-pulsed doping would result in a low contact resistance.
A schematic illustration of the growth sequence for pulse-doped InAs NWs and an SEM image of the NWs are shown in Fig. 1(a) and (b). The NW were aligned vertically relative to the 〈1 1 1〉 direction by using AsH3 surface treatment and pulse growth as in previous reports [14]. This indicated Si(1 1 1) changed to having a (1 1 1)B polar nature. The diameter and height of the pulse-doped NWs were 120 nm and 800 nm, respectively. The InAs NWs had hexagonal pillar shapes with 60
Journal of Crystal Growth 500 (2018) 58–62
H. Gamo, K. Tomioka
compared with undoped-InAs NW-VSGTs [3], Ion was small in spite of an n+ contact layer forming. This indicates that the series resistance was high because of the channel resistance. Moreover, the twins in the NW act as scattering centers which degrade carrier mobility and Gm. A possible approach to enhancing Ion is modulation-doping using a coremultishell structure.
Regarding pulse doping, DEZn was supplied for 2 s during the 10 s undoped InAs growth period, and TESn was supplied for 1 s during the 6 s undoped InAs growth. The pulsed doping procedure is illustrated in Fig. 1(c). The resulting NWs grew vertically on Si without any lateral growth, similarly to the undoped-InAs NWs [16]. The heights of the Znpulse-doped layer, Si-doped layer, and Sn-pulse-doped layer were 300 nm, 200 nm, and 300 nm, respectively. The segment heights were estimated from the growth rate of the NW. Fig. 2 shows the device characteristics of a fabricated InAs NWVSGT. The measured current and Gm were divided by the number of NWs and normalized with the NW circumference. The gate length (LG) and channel diameter were 200 and 120 nm, respectively. The device exhibited n-type enhancement-mode transistor characteristics with a threshold voltage of 0.29 V [Fig. 2(b) and (c)]. The threshold voltage VT was determined by linear extrapolation, as shown in the inset of Fig. 2(d). By assuming that the Schottky barrier height of the InAs NWchannel is approximately equal to the built-in voltage (Vbi), the carrier concentration (ND) can roughly be estimated to be 6.8 × 1016 cm−3 from the measured VT and Vbi. The effective carrier concentration decreased as a result of the Zn pulsed doping. The undoped InAs NWVSGT showed an off-leakage current of ∼10−9 A/μm at VDS = 1.00 V [3]. On the other hand, the NW with axial junction showed an off-state leakage current of ∼10−13 A/μm at VDS = 1.00 V. The off-state leakage current between the source and gate was considerably decreased because the Zn-pulsed doping was formed junction in the NW channel. We believe that the reduction in off-state leakage current originated from isolation of EF between the source and gate. This phenomenon suppresses the band-to-band tunneling causing off-state leakage. The InAs NW-VSGT had a minimum subthreshold slope [SS = dVG/d(log IDS)] of 68 mV/decade at VDS = 0.50 V, as shown in Fig. 3(a). The minimum SS was below 70 mV/decade with increasing VDS in Fig. 3(a). The draininduced barrier lowering (DIBL) was estimated to be 62 mV/V. The gate leakage current (IG) was on the order of 10−14 A/μm with a variation of VG under VDS = 0.50 V [Fig. 3(b)]. Compared with undoped InAs NWVSGTs [3], the SS of the doped NW channel considerably improved. Fig. 3(c) shows plots of minimum SS as a function of off-state leakage current for recent reports regarding III-V channels with multi-gate structures. Compared with the other reports, this work has a very small SS with a small off-state leakage current. Especially in the SGT structure using InAs NW-channels [4,17–22], the InAs NWs reported here exhibit the smallest SS. Although the InAs NW with the axial junction had the smallest SS, the SS was still higher than its physical limit (60 mV/decade at RT), which indicates the NWs had a large diameter and high interface state density (Dit) between the InAs NWs and high-k dielectric. A rough approximation of Dit from the SS showed it to be 4.6 × 1012 cm−2 eV−1. Fig. 4 shows TEM images of the HfAlO-covered InAs NWs on Si. In Fig. 4(b), the HfAlO/InAs {−1 1 0} facet has an atomically flat surface. On the other hand, the NW contains a number of twins with a period of 1–4 monolayers. Although the {−1 1 0} facet has a zigzag structure across the twin, this surface roughness converges with the period; that is, an atomically smooth surface is obtained. This smooth surface helps to lower the SS, and the cause is assumed to be the zigzag structure. The zigzag surface in Fig. 4(b) is composed of (1 1 1)A and (1 1 1)B microfacets. Recent report regarding InGaAs/Al2O3 interfaces [23] have revealed that (1 1 1)A/oxides interfaces are superior to (1 1 1)B and (1 0 0) surfaces. In our InAs NW channel, half of the whole { −1 1 0} facet [(1 1 1)A/B mixed facet] contained (1 1 1)A microfacets. Accordingly, this specific crystal phase in the InAs NW, which originated from a number of twins [shown in Fig. 4(b)], inherently formed a good interface. Surface roughness is the main reason for scattering. A possible approach to minimizing Dit is to make a core/shell structure during in situ MOVPE growth for passivation. Finally, it should be noted that lowering of the effective carrier concentration by the compensation effect increases the channel series resistance. Although the pulse-doped InAs NW-VSGT had a good Ion/Ioff ratio of around 105 at VDS = 1.00 V
4. Summary The InAs NWs were grown by SA-MOVPE. The InAs NWs included Zn and Sn pulse-doped layers. The pulse-doped NWs grew vertically on Si without any growth in the lateral direction, and a hexagonal pillar shape was maintained, similarly to undoped-InAs NWs. We demonstrated an InAs NW-VSGT made with pulse doping technique. The device showed SS = 68 mV/decade, Gm = 0.25 μS/μm at VDS = 0.50 V, and an off-leakage current of ∼1013 at VDS = 1.00 V. The SS and leakage current were greatly improved by the introduction of the pulse doped layers. In addition, the device operated as a normally off transistor because of the formation of a pseudointrinsic InAs channel by using the Zn-pulse doping technique. Acknowledgements This work was financially supported by a Grant-in-Aid for Young Scientists (A) (KAKEN Grant Number 161-106080) provided by the Japan Society for the Promotion of Science (JSPS). The authors would like to thank Professor Junichi Motohisa, Mr. Akinobu Yoshida, and Kohei Chiba for their support with the experiments. References [1] K. Tomioka, M. Yoshimura, T. Fukui, A III–V nanowire channel on silicon for highperformance vertical transistors, Nature 488 (2012) 189. [2] O. Kilpi, J. Sbensson, J. Wu, A.R. Persson, R. Wallenberg, E. Lind, L. Wernersson, Vertical InAs/InGaAs heterostructure metal-oxide-semiconductor field-effect transistors on Si, Nano Lett. 17 (2017) 6006. [3] T. Tanaka, K. Tomioka, S. Hara, J. Motohisa, E. Sano, T. Fukui, Vertical surrounding gate transistors using single InAs nanowires grown on Si substrates, Appl. Phys. Exp. 18 (2009) 025003. [4] K. Tomioka, F. Ishisaka, T. Fukui, Selective-area growth of InAs nanowires on Ge and vertical transistor application, Nano Lett. 15 (2015) 7253. [5] C. Rehnstedt, T. Martensson, C. Thelander, L. Samuelson, L. Wernesson, Vertical InAs nanowire wrap gate transistors on Si substrates, IEEE TED 55 (2008) 3037. [6] H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, F. Masuoka, Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s, IEEE TED 38 (1991) 573. [7] T. Bryllert, L. Wernersson, L.E. Froberg, L. Samuelson, Vertical high-mobility wrapgated InAs nanowire transistor, IEEE EDL 27 (2006) 323. [8] C. Thelander, L.E. Froberg, C. Rehnstedt, L. Samuelson, L. Wernersson, Vertical enhancement-mode InAs nanowire field-effect transistor with 50-nm wrap, Gate 29 (2008) 206. [9] D. Yakimets, G. Eneman, P. Schuddinck, T.H. Bao, M.G. Bardon, P. Raghavan, A. Veloso, N. Collaert, A. Mercha, D. Verkest, A.V. Thaean, K.D. Meyer, Vertical GAAFETs for the ultimate CMOS scaling, IEEE TED 62 (2015) 1433. [10] F. Glas, Critical dimensions for the plastic relaxation of strained axial heterostructures in free-standing nanowires, Phys. Rev. 74 (2006) 121302. [11] K. Tomioka, P. Mohan, J. Noborisaka, S. Hara, J. Motohisa, T. Fukui, Growth of highly uniform InAs nanowire arrays by selective-area MOVPE, Crys. Growth 298 (2007) 644. [12] K. Tomioka, K. Ikegiri, T. Tanaka, J. Motohisa, S. Hara, K. Hiruma, T. Fukui, Selective-area growth of III-V nanowires and their applications, J. Mater. Res. 26 (2011) 2127. [13] K. Tomioka, T. Tanaka, S. Hara, K. Hiruma, T. Fukui, III-V nanowires on Si substrate: selective-area growth and device applications, IEEE JSTQE 17 (2011) 1112. [14] K. Tomioka, J. Motohisa, S. Hara, T. Fukui, Control of InAs nanowire growth directions on Si, Nano Lett. 8 (2008) 3475. [15] K. Tomioka, M. Yoshimura, T. Fukui, Sub 60 mV/decade switch using an InAs nanowire-Si heterojunction and turn-on voltage shift with a pulsed doping, Nano Lett. 13 (2013) 5822. [16] E. Nakai, M. Chen, M. Yoshimura, K. Tomioka, T. Fukui, InGaAs axial-junction nanowire-array solar cells, Jpn. J. Appl. Phys. 54 (2015) 015201. [17] G. Doornbos, M. Holland, G. Vellianitis, M.J.H. Van Dal, B. Duriez, R. Oxland, A. Afzalian, T. Chen, G. Hsieh, M. Passlack, Y. Yeo, High-performance InAs gate-allaround nanowire MOSFETs on 300 mm Si substrates, IEEE JEDS 4 (2016) 253. [18] M. Berg, O.-P. Kilpi, K.-M. Persson, J. Svensson, M. Hellenbrand, E. Lind, L.E. Wernersson, Electrical characterization and modeling of gate-last vertical InAs
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= 0.5 V, IEEE DRC, (2012) 70th Annual 195. [22] O.-P. Kilpi, J. Wu, J. Svensson, E. Lind, L.-E. Wernersson, Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μA/μm at Ioff = 100 nA/μm and VD = 0.5 V, IEEE VLSIT 10 (2017) 36. [23] M. Yokoyama, R. Suzuki, N. Taoka, M. Takenaka, S. Takagi, Impact of surface orientation on (100), (111)A, and (111)B InGaAs surfaces with In content of 0.53 and 0.70 and on their Al2O3/InGaAs metal-oxide-semiconductor interface properties, Appl. Phys. Lett. 109 (2016) 182111.
nanowire MOSFETs on Si, IEEE EDL 37 (2016) 966. [19] A.W. Dey, C. Thelander, E. Lind, K.A. Dick, B.M. Borg, M. Borgstrom, P. Nilsson, L.E. Wernersson, High-performance InAs nanowire MOFETs, IEEE EDL 33 (2012) 791. [20] C. Thelander, C. Rehnstedt, L.E. Froberg, E. Lind, T. Martensson, P. Caroff, T. Lowgren, B.J. Ohlsson, L. Samuelson, L.-E. Wernersson, Development of a vertical wrap-gated InAs FET, IEEE TED 55 (2008) 3030. [21] K.-M. P, M. Berg, M. Brog, J. Wu, H. Sjoland, K. Lind, L.-E. Wernersson, Vertical InAs Nanowire MOSFETs with IDS = 1.34 mA/μm and gm = 1.19 mS/μm at VDS
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Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Selective-area growth of pulse-doped InAs nanowires on Si and vertical transistor application
T
⁎
Hironori Gamo , Katsuhiro Tomioka Research Center for Integrated Quantum Electronics (RCIQE), Graduate School of Information Science and Technology, Hokkaido University, North 14 West 9, Sapporo 060-0814, Japan
A R T I C LE I N FO
A B S T R A C T
Communicated by Yasuyuki Miyamoto
III-V compound semiconductors are promising channel materials for the future low-power and high-performance transistor because of their high electron/hole mobility. Here, we report on the integration of vertical InAs nanowire (NW)-channels on Si by selective-area metalorganic vapor phase epitaxy (MOVPE) with a pulse doping technique and demonstration of an InAs NW vertical surrounding-gate transistors. The device had a small subthreshold slope of 68 mV/decade, a normalized transconductance of 0.25 μS/μm, and on/off ratio of around 107. The axial junction with the pulse doping effectively suppressed off-state leakage current resulting in good electrostatic gate control.
Keywords: A1. Nanostructures A3. Metalorganic vapor phase epitaxy A3. Selective epitaxy B1. Nanomaterials B3. Field effect transistors
1. Introduction Sillicon-based integrated circuits are facing growing problems with size-scaling of field-effect transistors (FETs), such as increased off-state leakage current and power density per chip. Fast channel materials are expected to be alternatives for achieving FETs that have high Ion with low off-state leakage current under low bias [1–8]. Meanwhile, the vertical surrounding-gate architecture realizes high packing density and good electrostatic gate control [6,9]. Vertical III-V compound semiconductor nanowires (NWs) directly grown on Si platforms are, therefore, promising channel materials because they have higher electron/ hole mobilites compared with Si and can be used to implement the vertical surrounding-gate architecture. In addition, NWs can relax stress originating from the lattice mismatch because of their small footprint [10]. We recently, demonstrated direct integration of vertical InAs NWs on Si by selective-area metalorganic vapor phase epitaxy (SA-MOVPE) [11–13] and vertical surrounding-gate transistors (VSGTs) [3]. Improvements to the electrostatic characteristics of the InAs NW channels, especially the subthreshold slope (SS) and off-state leakage current, are still inherent challenges because the InAs has a narrow band gap and high electron mobility that would result in a very high off-leakage current. The dominant contribution to the off-state leakage is from source-drain band-to-band tunneling. In this study, we investigated the effect on the leakage current of adding Zn and Sn pulsed-doped layers to InAs NW vertical surrounding-gate FETs (VSGTs) on Si. We observed
⁎
Corresponding author. E-mail address: [email protected] (H. Gamo).
https://doi.org/10.1016/j.jcrysgro.2018.07.035
Available online 06 August 2018 0022-0248/ © 2018 Elsevier B.V. All rights reserved.
a considerable improvement in the subthreshold slope (SS) compared with undoped-InAs NW-channel VSGTs [3]. 2. Experimental procedure InAs NWs were grown on n-type Si(1 1 1) (resistivity of 1000 Ω·cm). First, 20-nm-thick SiO2 film was formed on the substrates by thermal oxidation. Periodical mask openings were formed using electron beam lithography and dry and wet etchings. RCA cleaning was used to improve the surface quality of the SiO2 film. Next, InAs NWs were selectively grown on the partially masked substrate in a horizontal MOVPE system at a working pressure of 0.1 atm. Trimethylindium (TMIn) and arsine (AsH3) were supplied as the source precursors. Diethlyzinc (DEZn) was used as the p-type dopant source, while monosilane (SiH4) and tetraethlytin (TESn) were used as the n-type dopant sources. The partial pressures of TMIn and AsH3 were respectively 9.7 × 10−7 and 2.5 × 10−4. The growth temperature was 550 °C, and the V/III ratio was 256 [11–14]. The Zn-pulse-doped layer was grown for 5 min, followed by Si-doped InAs growth for 3 min and growth of a Sn-pulsedoped layer for 5 min. We fabricated InAs NW-VSGT with high-k/metal surrounding gate [1,3,8]. After the growth, atomic layer deposition (ALD) was used to form a 10-nm-thick Hf0.8Al0.2O layer on the whole surface of the NWs. Second, gate metal (tungsten, W) was formed by radio frequency sputtering and contact pads were made by photolithography and wet etching. The NWs were then covered with benzocyclobutene (BCB)
Journal of Crystal Growth 500 (2018) 58–62
H. Gamo, K. Tomioka
Fig. 1. (a) Schematic illustrations of gas-flow and temperature sequence for InAs nanowire growth on Si. (b) Diagram of Zn- and Sn-pulse doping technique. DEZn was supplied for 2 s during undoped InAs growth for 10 s and TESn was supplied for 1 s during undoped InAs growth for 6 s. This Zn- and Sn-pulse doping sequence is repeated 30 and 50 times, respectively. (c) 30° tilted SEM image of the NW array.
Fig. 2. (a) Schematic cross-sectional structure of NW-VSGT. (b) Transfer characteristics. The measured current is divided by the number of NWs and normalized with the NW circumference. (c) Output characteristics. The gate voltage is changed from −1 V to 1 V in steps of 0.25 V. (d) Normalized transconductance for VDS = 0.50 V. Transfer characteristics for VDS = 0.5 V. Inset: The threshold voltage VT is estimated to be 0.29 V by using a linear extrapolation (red line). (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
InAs NW-VSGTs were annealed at 350 °C in N2 for Ohmic contacts in the source and drain regions.
formed by spin-coating and etched back to the desired thickness by reactive ion etching (RIE). Next, an isolation layer between gate and drain was formed by BCB. Drain and source metals were evaporated on the top of the NWs and back side of the substrate. The drain and source metals were Ni/Ge/Au/Ni/Au and Ni/Au, respectively. Finally, the 59
Journal of Crystal Growth 500 (2018) 58–62
H. Gamo, K. Tomioka
Fig. 3. (a) Subthreshold swing (SS). The minimum SS is 68 mV/decade for VDS = 0.50 V. (b) Gate current for VDS = 0.5 V. (c) Comparison of the SS versus off-state current, Ioff for VDS = 0.5 V. The green dots indicate off-state current without normalization. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
Fig. 4. (a) TEM image of HfAlO-covered InAs NWs on Si. (b) High-resolution TEM image of the InAs/HfAlO interface (red dashed line in Fig. 4(a)). Twins were introduced with a 1–4 monolayer period. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
3. Results and discussion
{−1 1 0} vertical facets. Carrier transport would occur on the {−1 1 0} surfaces. InAs is unintentionally doped by carbon, with typical carrier concentrations of 1016–1017 cm−3 [15]. The Zn-pulsed doping was used to compensate for the unintentional carbon dopants in the InAs NWs, while the Sn-pulsed doping was used to form heavily doped n-type InAs NWs and at the same time maintain the uniform shapes of the NW channels [15,16]. The InAs NW channel made with Zn-pulsed doping should shift the threshold voltage, while the n+ contact layer made with Sn-pulsed doping would result in a low contact resistance.
A schematic illustration of the growth sequence for pulse-doped InAs NWs and an SEM image of the NWs are shown in Fig. 1(a) and (b). The NW were aligned vertically relative to the 〈1 1 1〉 direction by using AsH3 surface treatment and pulse growth as in previous reports [14]. This indicated Si(1 1 1) changed to having a (1 1 1)B polar nature. The diameter and height of the pulse-doped NWs were 120 nm and 800 nm, respectively. The InAs NWs had hexagonal pillar shapes with 60
Journal of Crystal Growth 500 (2018) 58–62
H. Gamo, K. Tomioka
compared with undoped-InAs NW-VSGTs [3], Ion was small in spite of an n+ contact layer forming. This indicates that the series resistance was high because of the channel resistance. Moreover, the twins in the NW act as scattering centers which degrade carrier mobility and Gm. A possible approach to enhancing Ion is modulation-doping using a coremultishell structure.
Regarding pulse doping, DEZn was supplied for 2 s during the 10 s undoped InAs growth period, and TESn was supplied for 1 s during the 6 s undoped InAs growth. The pulsed doping procedure is illustrated in Fig. 1(c). The resulting NWs grew vertically on Si without any lateral growth, similarly to the undoped-InAs NWs [16]. The heights of the Znpulse-doped layer, Si-doped layer, and Sn-pulse-doped layer were 300 nm, 200 nm, and 300 nm, respectively. The segment heights were estimated from the growth rate of the NW. Fig. 2 shows the device characteristics of a fabricated InAs NWVSGT. The measured current and Gm were divided by the number of NWs and normalized with the NW circumference. The gate length (LG) and channel diameter were 200 and 120 nm, respectively. The device exhibited n-type enhancement-mode transistor characteristics with a threshold voltage of 0.29 V [Fig. 2(b) and (c)]. The threshold voltage VT was determined by linear extrapolation, as shown in the inset of Fig. 2(d). By assuming that the Schottky barrier height of the InAs NWchannel is approximately equal to the built-in voltage (Vbi), the carrier concentration (ND) can roughly be estimated to be 6.8 × 1016 cm−3 from the measured VT and Vbi. The effective carrier concentration decreased as a result of the Zn pulsed doping. The undoped InAs NWVSGT showed an off-leakage current of ∼10−9 A/μm at VDS = 1.00 V [3]. On the other hand, the NW with axial junction showed an off-state leakage current of ∼10−13 A/μm at VDS = 1.00 V. The off-state leakage current between the source and gate was considerably decreased because the Zn-pulsed doping was formed junction in the NW channel. We believe that the reduction in off-state leakage current originated from isolation of EF between the source and gate. This phenomenon suppresses the band-to-band tunneling causing off-state leakage. The InAs NW-VSGT had a minimum subthreshold slope [SS = dVG/d(log IDS)] of 68 mV/decade at VDS = 0.50 V, as shown in Fig. 3(a). The minimum SS was below 70 mV/decade with increasing VDS in Fig. 3(a). The draininduced barrier lowering (DIBL) was estimated to be 62 mV/V. The gate leakage current (IG) was on the order of 10−14 A/μm with a variation of VG under VDS = 0.50 V [Fig. 3(b)]. Compared with undoped InAs NWVSGTs [3], the SS of the doped NW channel considerably improved. Fig. 3(c) shows plots of minimum SS as a function of off-state leakage current for recent reports regarding III-V channels with multi-gate structures. Compared with the other reports, this work has a very small SS with a small off-state leakage current. Especially in the SGT structure using InAs NW-channels [4,17–22], the InAs NWs reported here exhibit the smallest SS. Although the InAs NW with the axial junction had the smallest SS, the SS was still higher than its physical limit (60 mV/decade at RT), which indicates the NWs had a large diameter and high interface state density (Dit) between the InAs NWs and high-k dielectric. A rough approximation of Dit from the SS showed it to be 4.6 × 1012 cm−2 eV−1. Fig. 4 shows TEM images of the HfAlO-covered InAs NWs on Si. In Fig. 4(b), the HfAlO/InAs {−1 1 0} facet has an atomically flat surface. On the other hand, the NW contains a number of twins with a period of 1–4 monolayers. Although the {−1 1 0} facet has a zigzag structure across the twin, this surface roughness converges with the period; that is, an atomically smooth surface is obtained. This smooth surface helps to lower the SS, and the cause is assumed to be the zigzag structure. The zigzag surface in Fig. 4(b) is composed of (1 1 1)A and (1 1 1)B microfacets. Recent report regarding InGaAs/Al2O3 interfaces [23] have revealed that (1 1 1)A/oxides interfaces are superior to (1 1 1)B and (1 0 0) surfaces. In our InAs NW channel, half of the whole { −1 1 0} facet [(1 1 1)A/B mixed facet] contained (1 1 1)A microfacets. Accordingly, this specific crystal phase in the InAs NW, which originated from a number of twins [shown in Fig. 4(b)], inherently formed a good interface. Surface roughness is the main reason for scattering. A possible approach to minimizing Dit is to make a core/shell structure during in situ MOVPE growth for passivation. Finally, it should be noted that lowering of the effective carrier concentration by the compensation effect increases the channel series resistance. Although the pulse-doped InAs NW-VSGT had a good Ion/Ioff ratio of around 105 at VDS = 1.00 V
4. Summary The InAs NWs were grown by SA-MOVPE. The InAs NWs included Zn and Sn pulse-doped layers. The pulse-doped NWs grew vertically on Si without any growth in the lateral direction, and a hexagonal pillar shape was maintained, similarly to undoped-InAs NWs. We demonstrated an InAs NW-VSGT made with pulse doping technique. The device showed SS = 68 mV/decade, Gm = 0.25 μS/μm at VDS = 0.50 V, and an off-leakage current of ∼1013 at VDS = 1.00 V. The SS and leakage current were greatly improved by the introduction of the pulse doped layers. In addition, the device operated as a normally off transistor because of the formation of a pseudointrinsic InAs channel by using the Zn-pulse doping technique. Acknowledgements This work was financially supported by a Grant-in-Aid for Young Scientists (A) (KAKEN Grant Number 161-106080) provided by the Japan Society for the Promotion of Science (JSPS). The authors would like to thank Professor Junichi Motohisa, Mr. Akinobu Yoshida, and Kohei Chiba for their support with the experiments. References [1] K. Tomioka, M. Yoshimura, T. Fukui, A III–V nanowire channel on silicon for highperformance vertical transistors, Nature 488 (2012) 189. [2] O. Kilpi, J. Sbensson, J. Wu, A.R. Persson, R. Wallenberg, E. Lind, L. Wernersson, Vertical InAs/InGaAs heterostructure metal-oxide-semiconductor field-effect transistors on Si, Nano Lett. 17 (2017) 6006. [3] T. Tanaka, K. Tomioka, S. Hara, J. Motohisa, E. Sano, T. Fukui, Vertical surrounding gate transistors using single InAs nanowires grown on Si substrates, Appl. Phys. Exp. 18 (2009) 025003. [4] K. Tomioka, F. Ishisaka, T. Fukui, Selective-area growth of InAs nanowires on Ge and vertical transistor application, Nano Lett. 15 (2015) 7253. [5] C. Rehnstedt, T. Martensson, C. Thelander, L. Samuelson, L. Wernesson, Vertical InAs nanowire wrap gate transistors on Si substrates, IEEE TED 55 (2008) 3037. [6] H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, F. Masuoka, Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s, IEEE TED 38 (1991) 573. [7] T. Bryllert, L. Wernersson, L.E. Froberg, L. Samuelson, Vertical high-mobility wrapgated InAs nanowire transistor, IEEE EDL 27 (2006) 323. [8] C. Thelander, L.E. Froberg, C. Rehnstedt, L. Samuelson, L. Wernersson, Vertical enhancement-mode InAs nanowire field-effect transistor with 50-nm wrap, Gate 29 (2008) 206. [9] D. Yakimets, G. Eneman, P. Schuddinck, T.H. Bao, M.G. Bardon, P. Raghavan, A. Veloso, N. Collaert, A. Mercha, D. Verkest, A.V. Thaean, K.D. Meyer, Vertical GAAFETs for the ultimate CMOS scaling, IEEE TED 62 (2015) 1433. [10] F. Glas, Critical dimensions for the plastic relaxation of strained axial heterostructures in free-standing nanowires, Phys. Rev. 74 (2006) 121302. [11] K. Tomioka, P. Mohan, J. Noborisaka, S. Hara, J. Motohisa, T. Fukui, Growth of highly uniform InAs nanowire arrays by selective-area MOVPE, Crys. Growth 298 (2007) 644. [12] K. Tomioka, K. Ikegiri, T. Tanaka, J. Motohisa, S. Hara, K. Hiruma, T. Fukui, Selective-area growth of III-V nanowires and their applications, J. Mater. Res. 26 (2011) 2127. [13] K. Tomioka, T. Tanaka, S. Hara, K. Hiruma, T. Fukui, III-V nanowires on Si substrate: selective-area growth and device applications, IEEE JSTQE 17 (2011) 1112. [14] K. Tomioka, J. Motohisa, S. Hara, T. Fukui, Control of InAs nanowire growth directions on Si, Nano Lett. 8 (2008) 3475. [15] K. Tomioka, M. Yoshimura, T. Fukui, Sub 60 mV/decade switch using an InAs nanowire-Si heterojunction and turn-on voltage shift with a pulsed doping, Nano Lett. 13 (2013) 5822. [16] E. Nakai, M. Chen, M. Yoshimura, K. Tomioka, T. Fukui, InGaAs axial-junction nanowire-array solar cells, Jpn. J. Appl. Phys. 54 (2015) 015201. [17] G. Doornbos, M. Holland, G. Vellianitis, M.J.H. Van Dal, B. Duriez, R. Oxland, A. Afzalian, T. Chen, G. Hsieh, M. Passlack, Y. Yeo, High-performance InAs gate-allaround nanowire MOSFETs on 300 mm Si substrates, IEEE JEDS 4 (2016) 253. [18] M. Berg, O.-P. Kilpi, K.-M. Persson, J. Svensson, M. Hellenbrand, E. Lind, L.E. Wernersson, Electrical characterization and modeling of gate-last vertical InAs
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