- Email: [email protected]
Selective deposition of TiSi2 on ultra-thin silicon-on-insulator (SOI) wafers
Thin Solid Films 332 (1998) 412±417
Selective deposition of TiSi2 on ultra-thin silicon-on-insulator (SOI) wafers Jer-shen Maa*, Bruce Ulrich, Sheng Teng Hsu, Greg Stecker Sharp Microelectronics Technology, Camas, WA 98684, USA
Abstract Ê was demonstrated using a gas mixture of TiCl4, SiH4, SiH2Cl2, and Chemical vapor deposition of TiSi2 ®lm on silicon ®lm as thin as 97 A Ê evaporated Si ®lm and on SOI ®lms with 220±450 A Ê Si. On SOI ®lm, transition of H2. Selective deposition was observed on 97±180 A Ê after a silicide to low resistance phase occurred at 26±28 s of deposition, as indicated by the resistance change. Silicide ®lm was 650±700 A 35-s deposition. The Auger depth pro®le showed uniform ®lm composition. Silicide ®lm was also selectively deposited on polysilicon lines formed on SOI wafer. Transition to low resistance phase occurred also at 26±28 s in both 0.5 and 5 mm polysilicon lines. Silicide ®lms formed on SOI structure were stable at 8508C. Films formed on polysilicon lines showed resistance increase when the deposition time was shorter. Phosphorus and BF2 implantation caused resistance increase in CVD silicide ®lms. A subsequent RTA anneal restored the resistance to a value lower than 5 V/sq. q 1998 Elsevier Science S.A. All rights reserved.
1. Introduction Titanium silicide technology has been applied to the fabrication of silicon-on-insulator (SOI) MOS transistors to reduce series resistance and gate sheet resistance [1±3]. Using a selective process known as self-aligned silicide (salicide) process, titanium silicide is formed only on active areas and polysilicon surface. It is known that titanium salicide process faces more challenges with the shrinkage of device dimensions. First, the process window becomes very narrow, careful process control is needed in all the steps of the salicide process, including titanium sputtering, rapid thermal annealing (RTA), and selective wet etch steps [4,5]. The process becomes more complex to induce phase transformation to low resistance C54 phase for silicide formed on very narrow polysilicon line [5,6]. The control of silicide thickness becomes more dif®cult when reaction rate on N 1 and P 1 silicon is different [7]. There are also problems associated with the process of SOI wafers. In particular silicide thickness is now limited by the thickness of SOI ®lm. A thicker titanium silicide ®lm can not be formed on a wafer which has an ultra-thin SOI structure. In this case the silicide ®lm tends to have a higher sheet resistance and poor thermal stability. In view of these, searching for an alternative silicidation technique becomes more important. * Corresponding author Tel.:11 360 834 8760; fax:11 360 834 8689; email: [email protected].
Selective deposition of TiSi2 on bulk Si wafers by lowpressure chemical vapor deposition (LPCVD) has been reported previously [8±10]. It is an one-step process, which is favorable in view of process cost. But more importantly, in CVD process the silicide thickness is no longer limited by the silicon thickness of the SOI ®lm. Also, the substrate doping does not have a strong effect on silicide growth. Formation of C54 phase occurs during deposition; it is not affected by polysilicon line-width. It is known that substrate silicon can be consumed during the CVD deposition process [8]. Risk of junction leakage does exist when processing devices with ultra shallow junctions. Reduction or elimination of silicon consumption has been reported by several laboratories [9,11]. Oftentimes when Si is not consumed, a thin Si layer was observed at silicide/Si interface [11]. However one still can not ensure a risk-free production process. The reason is that Si consumption or deposition depends also on the total exposed area of Si, a best condition established for one particular pattern may still cause a slight Si consumption in wafers which have a different pattern [12]. The silicide/silicon interface is also dif®cult to control. Interface roughness occurs during the nucleation and growth stage, a smooth interface requires higher nucleation density, which may not be easily achievable [13,14]. The process of SOI devices, however, is immune to the above problems. In a SOI MOSFET device, the junction area is not under the silicide/silicon interface as the bulk devices [15]. Therefore the junction should not be affected
0040-6090/98/$ - see front matter q 1998 Elsevier Science S.A. All rights reserved. PII S0040-609 0(98)01015-3
J. Maa et al. / Thin Solid Films 332 (1998) 412±417
Fig. 1. Silicide thickness and Si consumption (2) or accumulation (1) at 7% (dashed line) and 8% (solid line) of maximum TiCl4 ¯ow, corresponding to about 0.34 and 0.54 sccm. The ®gure shows an increase of silicide thickness with TiCl4 ¯ow rate and a positive build-up of silicon at the interface.
by a slight Si consumption or by roughness occurred at the silicide/silicon interface. The purpose of this work is to demonstrate the formation of titanium silicide on ultra-thin silicon ®lm and on SOI and polysilicon structure. Thermal stability of silicide ®lms formed on SOI and polysilicon structure will be determined. The effect of ion implantation and subsequent annealing on silicide will also be studied. 2. Experimental Ê Si ®lm and 1800±2000 A Ê buried SOI wafers with 2200-A oxide layers were obtained from IBIS Technology Corp. The Si ®lm was thinned down to a ®nal thickness of 200± Ê . This was done by converting most Si to silicon 500 A dioxide through thermal oxidation and removing the oxide layer by a HF etch step. These wafers were then processed through CMOS process steps, the ®nal structure consisted of silicon islands as active regions and polysilicon gates running over the active region and buried oxide [16]. The Ê . There was a plasma thickness of polysilicon was 3500 A etch step to form spacers along the sidewall of the polysilicon lines. At this step both the active SOI regions and the polysilicon lines were exposed to C3F8 plasma. The wafers were then cleaned in SC-1 and SC-2 solution, and dipped in dilute HF solution before loading into the load-lock chamber of the CVD system. Bulk Si test wafers were prepared to measure the depth of Si consumption or the thickness of Si ®lm deposited at the interface. These were p-type (100) wafers. These wafers were ®rst coated with PECVD oxide. After photo step, the
413
window areas were opened by wet etch in HF solution. The clean steps before loading was same as SOI wafers. Wafers with ultra-thin Si ®lms were prepared by ®rst Ê of Si from an electron-beam system evaporating 97±180 A on oxidized Si wafers. All the subsequent steps, such as oxide coating, etching, and ®nal clean were same as that of bulk Si test wafers. All SOI wafers, bulk Si test wafer and wafers with ultrathin Si, were patterned using the same mask set; therefore all had the same feature dimensions and the same density of exposed Si area or window area. CVD TiSi2 deposition was carried out in an AG Integral One rapid thermal chemical vapor deposition (RTCVD) system. The deposition chamber was a single piece electropolished stainless steel reaction chamber. The chamber wall was water cooled and covered with quartz liner to protect wafer from metal surfaces. Wafer was supported by a quartz susceptor, which rotated at 23 rev./min during deposition. The background pressure of the deposition chamber was around 5 £ 1028 Torr. The wafer was heated from the top by tungsten halogen lamps through a thick quartz window. The deposition temperature was maintained around 7808C. Processing gases were introduced from upper part of the chamber and distributed to the wafer surface through a perforated quartz plate, which acted as a showerhead. Process gases consisted of TiCl4, SiH4, SiH2Cl2, and H2. The ¯ow rate of SiH4, SiH2Cl2 and H2 were maintained at 61, 5, and 1500 sccm, respectively. The TiCl4 ¯ow was controlled by a MKS vapor source mass ¯ow controller. It was maintained either at 7 or 8% of its maximum ¯ow range, corresponding to about 0.34 or 0.54 sccm of TiCl4 after subtracting the zero drift which varied slightly from time to time. The pressure was around 300 mTorr. After deposition, wafers were characterized by SEM, TEM, Auger electron spectroscopy, and sheet resistance measurement. Step height was measured to determine the silicide ®lm thickness and the consumption of substrate Si or the deposition of Si at the silicide/Si interface. Step height was measured before and after the removal of silicide and oxide layer. This was performed only on bulk Si test wafer. Step height in SOI wafer was dif®cult to measure because HF also attacked the buried oxide layer.
3. Results and discussion 3.1. Si consumption or deposition A series of CVD experiments were performed to deposit titanium silicide on bulk Si test wafers. The purpose is to establish the deposition condition for the ultra-thin Si and SOI wafers. Thickness of silicide and the amount of Si consumed from or accumulated onto the substrate were measured. The results are shown in Fig. 1. The thickness of silicide and Si deposited from gas chemistry with about 0.54 sccm TiCl4 or 8% of maximum ¯ow is shown by the
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The possible disadvantages were: (1) silicide resistance was higher, (2) the interface became rougher, (3) the time for the C49±C54 phase transition became longer, and (4) the contact resistance might be higher. Because of these considerations, the TiCl4 ¯ow rate for SOI wafers was maintained at 8% of the maximum ¯ow or about 0.54 sccm. 3.2. Deposition on ultra-thin Si ®lm
Ê Si Fig. 2. Sheet resistance of CVD titanium silicide ®lms deposited on 97-A Ê Si ®lm and bulk Si wafer. The ®gure shows that the sheet ®lm, 180-A resistance of silicide ®lm deposited on bulk Si is lower than that formed on very thin Si ®lm.
solid lines. Only positive built-up of Si at the silicide/Si interface was observed, the Si thickness was found to decrease slightly with deposition time. The thickness of silicide and Si deposited at 7% TiCl4 ¯ow or about 0.34 sccm is represented by the dashed line. A positive buildup of Si was observed, but the Si thickness was found to remain unchanged with deposition time. The advantage of deposition at very low ¯ow rate of TiCl4 was to maintain a positive build-up of Si at the interface.
Ê Fig. 3. Sheet resistance of CVD titanium silicide ®lms deposited on 220-A SOI ®lm. Solid line is as-deposited value. Dashed lines are values after RTA annealing at 8508 for 10, 20 and 30 min. The ®gure shows a decrease of sheet resistance with deposition time. The sheet resistance changes very slightly by annealing.
The uniformity of the Si ®lm in SOI wafers may not be constant, therefore it is dif®cult to thin the Si of the SOI Ê . Wafers with ultra-thin Si were wafer to less than 100 A obtained by vapor deposition; the preparation procedure was described in Section 2. Selective deposition of titanium silicide was demonÊ Si ®lm. Sheet resisstrated on wafers with 97- and 180-A tances less than 5 V/sq were achieved with less than 60 s of deposition time. Fig. 2 shows that the sheet resistance of Ê Si was very silicide ®lms formed on 97- Si and on 180-A Ê Si similar. The thickness of silicide ®lm deposited on 180-A Ê after 44 s was about 780 A. This was measured by crosssectional SEM. The thickness of silicide deposited under the Ê. same condition on bulk Si test wafers was about 1000 A The difference can be due to the effect of Si thickness or the difference of Si surface condition. This work indicated that silicide deposition on ultra-thin SOI wafers was very feasible. It also indicated that silicide thickness on SOI wafer could be thinner than that on Bulk Si test wafers. 3.3. Deposition on SOI ®lm and on polysilicon lines CVD silicide ®lm was deposited on SOI and on polysilicon structures. The deposition time varied from 24 to 36 s.
Ê Fig. 4. Sheet resistance of CVD titanium silicide ®lms deposited on 450-A SOI ®lm. Solid line is as-deposited value. Dashed lines are values after RTA annealing at 8508 for 10, 20 and 30 min. The ®gure shows a decrease of sheet resistance with deposition time. The sheet resistance increases slightly at shorter deposition time.
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Ê Fig. 5. Sheet resistance of CVD titanium silicide ®lms deposited on 3500-A thick polysilicon lines. The polysilicon line-width is 5 and 0.5 mm. The ®gure shows a decrease of sheet resistance with deposition time. The results on 5 and 0.5 mm lines are very similar.
Ê Fig. 6. Sheet resistance of CVD titanium silicide ®lms deposited on 3500-A polysilicon lines. Polysilicon line-width is 0.5 mm. Solid line is as-deposited value. Dashed lines are values after RTA annealing at 8508 for 10, 20 and 30 min. the ®gure shows decrease of sheet resistance with deposition time. Subsequent annealing causes an increase in sheet resistance.
The sheet resistance measured after deposition is shown as solid lines from Fig. 3±6. Fig. 3 and Fig. 4 are results of silicide ®lms deposited on SOI structures with 220- and 450Ê Si ®lms. Fig. 5 and Fig. 6 are the results of the ®lms A deposited on 5 and 0.5 mm polysilicon lines. The sheet resistance was found to decrease with deposition time. After 26±28 s the slope of the resistance curves became constant. This was observed in both SOI and polysilicon cases, most likely due to the complete transition into C54 phase. Fig. 5 is the result from polysilicon lines. The ®lm resistance deposited on 0.5 and 5 mm polysilicon lines was almost the same. One can therefore say that the time to form C54 phase during CVD deposition of titanium silicide is not a factor of polysilicon line-width.
Fig. 7 show SEM micrographs of a SOI structure after silicide deposition. It shows a 0.3-mm polysilicon line and a source/drain structure. The background area is buried oxide. Ê before The Si thickness on the source/drain area was 220 A silicide deposition. The silicide deposition was very selective; bridging or residue across the oxide spacer was not detected by electrical measurement. Fig. 8 is an Auger Ê SOI depth pro®le of the silicide ®lm deposited on a 220-A structure. The composition is constant throughout the depth of the ®lm. The silicide thickness of a few samples was measured by cross-sectional TEM and SEM. After a 35-s deposition, the Ê , the silithickness of silicide on SOI was about 650±700 A Ê. cide on polysilicon was about 900±1000 A
Fig. 7. SEM micrographs of CVD TiSi2 deposited on gate and source/drain or SOI wafer. The deposition time was 30 s. (a) Top view of gate line going across Ê Si before silicide deposition. (b) Silicide ®lms formed on polysilicon (top line structure connected to a the source/drain structure. Source and drain are 220-A polysilicon pad) and on Si of the source/drain structure.
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Ê SOI; deposition time was 35 s. The ®gure shows a uniform disilicide ®lm extended Fig. 8. Auger depth pro®le of CVD silicide which was deposited on 220-A to the oxide surface.
3.4. Thermal stability of CVD titanium silicide Titanium silicide ®lms were annealed in N2 ambient at 8508C in a RTA system. The wafer was removed from the RTA unit after every 10-min annealing to measure its sheet resistance. The results are also shown in Fig.3,4 and Fig. 6. Fig. 3 and Fig. 4 are results obtained from silicide ®lms deposited on SOI structures. Titanium silicide ®lms deposÊ SOI and on 450-A Ê SOI were quite stable after ited on 220-A 8508C, 30-min annealing. Fig. 6 was from silicide ®lms
Fig. 9. Sheet resistance of CVD titanium silicide ®lms after phosphorus implantation and RTA anneal. The ®gure shows the high sheet resistance after implantation and the decrease of sheet resistance by subsequent consecutive annealing.
deposited on 0.5-mm polysilicon structures. Increase of sheet resistance is observed, which depends on silicide deposition time and annealing time. If the deposition time is longer than 35 s, the silicide ®lm is found to be quite stable at 8508C. 3.5. Effect of ion implantation SOI wafers with silicided SOI and polysilicon structure were implanted with phosphorus or BF2 at energy of 60 keV
Fig. 10. Sheet resistance of CVD titanium silicide ®lms after BF2 implantation and RTA anneal. The ®gure shows the high sheet resistance after implantation and the decrease of sheet resistance by subsequent annealing.
J. Maa et al. / Thin Solid Films 332 (1998) 412±417
with a dose of 5 £ 1015 ions/cm 2. Ion implantation was found to cause an increase in silicide sheet resistance. Silicide ®lm deposited on SOI structures showed a far greater increase. A subsequent anneal restored the resistance to a low value. The results are shown in Fig. 9 and Fig. 10. Annealing was performed in N2 ambient in a RTA system. The annealing time was 30 s. Wafer was intermittently removed from the annealing chamber after each annealing step to measure silicide sheet resistance, then returned to the system for annealing at a higher temperature. The temperature increment was 508C. A consistent decrease of sheet resistance with the increase of annealing temperature is observed, especially in the linear region. Once the temperature reaches about 650±7008C, a sudden drop of resistance is observed, probably caused by the restoring of the C54 phase. Silicide deposited on SOI structure shows a greater drop than that deposited on polysilicon ®lm. 4. Summary Previously many laboratories have reported the results of chemical vapor deposition of titanium silicide on bulk silicon wafers. This is the ®rst time this technique is applied to Ê . Selective SOI wafers and to silicon ®lm less than 100 A chemical vapor deposition of titanium silicide on Si ®lm Ê was demonstrated. Deposiwith thickness less than 100 A Ê SOI struction was also demonstrated on 220- and 450-A tures and on polysilicon lines. The titanium silicide ®lms deposited on thin Si and SOI ®lms were thinner than the silicide ®lms deposited on bulk Si wafers and on polysilicon lines. Silicide ®lms deposited on SOI structures were stable at 8508C. Films deposited on polysilicon showed resistance increases at 8508C. Films were stable if the deposition time was longer than 35 s. Phosphorus and BF2 implantation
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caused resistance to increase; the increase on SOI structure was the highest, followed by that on 5-mm polysilicon structures. The increase from 0.5-mm polysilicon structure was the lowest. Subsequent RTA annealing at temperatures around 650±7008C restored the sheet resistance to a low value. From the results of this work it is clear that selective CVD technique can be applied to SOI technology even with very thin silicon ®lm. References [1] J.-S. Maa, Proc. 11th VLSI Multilevel Interconnection Conf., Santa Clara, CA, 1994, p. 484. [2] J. Chen, J.-P. Colinge, D. Flandre, R. Gillon, J.P. Raskin, D. Vanhoenacker, J. Electrochem. Soc. 144 (1997) 2437. [3] K. Azuma, A. Kishi, M. Tanigawa, et al., Proc. 1995 Int. SOI Conf., p. 30. [4] L.P. Hobbs, K. Maex, Appl. Surf. Sci. 53 (1991) 321. [5] R.W. Mann, L.A. Clevenger, J. Electrochem. Soc. 141 (1994) 1347. [6] J. Lasky, J. Nakos, O. Cain, P. Geiss, IEEE Trans. Electron Devices 38 (1991) 2629. [7] H.K. Park, J. Sachitano, M. McPherson, T. Yamaguchi, G. Lehman, J. Vac. Sci. Technol. A 2 (1984) 264. [8] V. Ilderem, R. Reif, J. Electrochem. Soc. 135 (1988) 2590. [9] J.L. Regolini, D. Bensahel, G. Bomchil, J. Mercier, Appl. Surf. Sci. 38 (1989) 408. [10] A. Bouteville, A. Royer, J.C. Remy, J. Electrochem. Soc. 134 (1987) 2080. [11] A. Bouteville, C. Attuyt, J.C. Remy, Appl. Surf. Sci. 53 (1991) 11. [12] D.B. Gladden, C.E. Weintraub, M.C. Ozuturk, Mater. Res. Soc. Symp. Proc, Vol. 402 p. (1996) 295. [13] K. Saito, T. Amazawa, Y. Arita, J. Electrochem. Soc. 140 (1993) 513. [14] J. Engqvist, U. Jansson, J. Lu, J.-O. Carlsson, J. Vac. Sci. Technol. A 12 (1994) 161. [15] J.-P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, , Kluwer Academic, Boston,MA, 1997 p. 123. [16] J.-S. Maa, S.T. Hsu, B. Ulrich, C.H. Peng, Thin Solid Films 308/309 (1997) 570.
Selective deposition of TiSi2 on ultra-thin silicon-on-insulator (SOI) wafers Jer-shen Maa*, Bruce Ulrich, Sheng Teng Hsu, Greg Stecker Sharp Microelectronics Technology, Camas, WA 98684, USA
Abstract Ê was demonstrated using a gas mixture of TiCl4, SiH4, SiH2Cl2, and Chemical vapor deposition of TiSi2 ®lm on silicon ®lm as thin as 97 A Ê evaporated Si ®lm and on SOI ®lms with 220±450 A Ê Si. On SOI ®lm, transition of H2. Selective deposition was observed on 97±180 A Ê after a silicide to low resistance phase occurred at 26±28 s of deposition, as indicated by the resistance change. Silicide ®lm was 650±700 A 35-s deposition. The Auger depth pro®le showed uniform ®lm composition. Silicide ®lm was also selectively deposited on polysilicon lines formed on SOI wafer. Transition to low resistance phase occurred also at 26±28 s in both 0.5 and 5 mm polysilicon lines. Silicide ®lms formed on SOI structure were stable at 8508C. Films formed on polysilicon lines showed resistance increase when the deposition time was shorter. Phosphorus and BF2 implantation caused resistance increase in CVD silicide ®lms. A subsequent RTA anneal restored the resistance to a value lower than 5 V/sq. q 1998 Elsevier Science S.A. All rights reserved.
1. Introduction Titanium silicide technology has been applied to the fabrication of silicon-on-insulator (SOI) MOS transistors to reduce series resistance and gate sheet resistance [1±3]. Using a selective process known as self-aligned silicide (salicide) process, titanium silicide is formed only on active areas and polysilicon surface. It is known that titanium salicide process faces more challenges with the shrinkage of device dimensions. First, the process window becomes very narrow, careful process control is needed in all the steps of the salicide process, including titanium sputtering, rapid thermal annealing (RTA), and selective wet etch steps [4,5]. The process becomes more complex to induce phase transformation to low resistance C54 phase for silicide formed on very narrow polysilicon line [5,6]. The control of silicide thickness becomes more dif®cult when reaction rate on N 1 and P 1 silicon is different [7]. There are also problems associated with the process of SOI wafers. In particular silicide thickness is now limited by the thickness of SOI ®lm. A thicker titanium silicide ®lm can not be formed on a wafer which has an ultra-thin SOI structure. In this case the silicide ®lm tends to have a higher sheet resistance and poor thermal stability. In view of these, searching for an alternative silicidation technique becomes more important. * Corresponding author Tel.:11 360 834 8760; fax:11 360 834 8689; email: [email protected].
Selective deposition of TiSi2 on bulk Si wafers by lowpressure chemical vapor deposition (LPCVD) has been reported previously [8±10]. It is an one-step process, which is favorable in view of process cost. But more importantly, in CVD process the silicide thickness is no longer limited by the silicon thickness of the SOI ®lm. Also, the substrate doping does not have a strong effect on silicide growth. Formation of C54 phase occurs during deposition; it is not affected by polysilicon line-width. It is known that substrate silicon can be consumed during the CVD deposition process [8]. Risk of junction leakage does exist when processing devices with ultra shallow junctions. Reduction or elimination of silicon consumption has been reported by several laboratories [9,11]. Oftentimes when Si is not consumed, a thin Si layer was observed at silicide/Si interface [11]. However one still can not ensure a risk-free production process. The reason is that Si consumption or deposition depends also on the total exposed area of Si, a best condition established for one particular pattern may still cause a slight Si consumption in wafers which have a different pattern [12]. The silicide/silicon interface is also dif®cult to control. Interface roughness occurs during the nucleation and growth stage, a smooth interface requires higher nucleation density, which may not be easily achievable [13,14]. The process of SOI devices, however, is immune to the above problems. In a SOI MOSFET device, the junction area is not under the silicide/silicon interface as the bulk devices [15]. Therefore the junction should not be affected
0040-6090/98/$ - see front matter q 1998 Elsevier Science S.A. All rights reserved. PII S0040-609 0(98)01015-3
J. Maa et al. / Thin Solid Films 332 (1998) 412±417
Fig. 1. Silicide thickness and Si consumption (2) or accumulation (1) at 7% (dashed line) and 8% (solid line) of maximum TiCl4 ¯ow, corresponding to about 0.34 and 0.54 sccm. The ®gure shows an increase of silicide thickness with TiCl4 ¯ow rate and a positive build-up of silicon at the interface.
by a slight Si consumption or by roughness occurred at the silicide/silicon interface. The purpose of this work is to demonstrate the formation of titanium silicide on ultra-thin silicon ®lm and on SOI and polysilicon structure. Thermal stability of silicide ®lms formed on SOI and polysilicon structure will be determined. The effect of ion implantation and subsequent annealing on silicide will also be studied. 2. Experimental Ê Si ®lm and 1800±2000 A Ê buried SOI wafers with 2200-A oxide layers were obtained from IBIS Technology Corp. The Si ®lm was thinned down to a ®nal thickness of 200± Ê . This was done by converting most Si to silicon 500 A dioxide through thermal oxidation and removing the oxide layer by a HF etch step. These wafers were then processed through CMOS process steps, the ®nal structure consisted of silicon islands as active regions and polysilicon gates running over the active region and buried oxide [16]. The Ê . There was a plasma thickness of polysilicon was 3500 A etch step to form spacers along the sidewall of the polysilicon lines. At this step both the active SOI regions and the polysilicon lines were exposed to C3F8 plasma. The wafers were then cleaned in SC-1 and SC-2 solution, and dipped in dilute HF solution before loading into the load-lock chamber of the CVD system. Bulk Si test wafers were prepared to measure the depth of Si consumption or the thickness of Si ®lm deposited at the interface. These were p-type (100) wafers. These wafers were ®rst coated with PECVD oxide. After photo step, the
413
window areas were opened by wet etch in HF solution. The clean steps before loading was same as SOI wafers. Wafers with ultra-thin Si ®lms were prepared by ®rst Ê of Si from an electron-beam system evaporating 97±180 A on oxidized Si wafers. All the subsequent steps, such as oxide coating, etching, and ®nal clean were same as that of bulk Si test wafers. All SOI wafers, bulk Si test wafer and wafers with ultrathin Si, were patterned using the same mask set; therefore all had the same feature dimensions and the same density of exposed Si area or window area. CVD TiSi2 deposition was carried out in an AG Integral One rapid thermal chemical vapor deposition (RTCVD) system. The deposition chamber was a single piece electropolished stainless steel reaction chamber. The chamber wall was water cooled and covered with quartz liner to protect wafer from metal surfaces. Wafer was supported by a quartz susceptor, which rotated at 23 rev./min during deposition. The background pressure of the deposition chamber was around 5 £ 1028 Torr. The wafer was heated from the top by tungsten halogen lamps through a thick quartz window. The deposition temperature was maintained around 7808C. Processing gases were introduced from upper part of the chamber and distributed to the wafer surface through a perforated quartz plate, which acted as a showerhead. Process gases consisted of TiCl4, SiH4, SiH2Cl2, and H2. The ¯ow rate of SiH4, SiH2Cl2 and H2 were maintained at 61, 5, and 1500 sccm, respectively. The TiCl4 ¯ow was controlled by a MKS vapor source mass ¯ow controller. It was maintained either at 7 or 8% of its maximum ¯ow range, corresponding to about 0.34 or 0.54 sccm of TiCl4 after subtracting the zero drift which varied slightly from time to time. The pressure was around 300 mTorr. After deposition, wafers were characterized by SEM, TEM, Auger electron spectroscopy, and sheet resistance measurement. Step height was measured to determine the silicide ®lm thickness and the consumption of substrate Si or the deposition of Si at the silicide/Si interface. Step height was measured before and after the removal of silicide and oxide layer. This was performed only on bulk Si test wafer. Step height in SOI wafer was dif®cult to measure because HF also attacked the buried oxide layer.
3. Results and discussion 3.1. Si consumption or deposition A series of CVD experiments were performed to deposit titanium silicide on bulk Si test wafers. The purpose is to establish the deposition condition for the ultra-thin Si and SOI wafers. Thickness of silicide and the amount of Si consumed from or accumulated onto the substrate were measured. The results are shown in Fig. 1. The thickness of silicide and Si deposited from gas chemistry with about 0.54 sccm TiCl4 or 8% of maximum ¯ow is shown by the
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The possible disadvantages were: (1) silicide resistance was higher, (2) the interface became rougher, (3) the time for the C49±C54 phase transition became longer, and (4) the contact resistance might be higher. Because of these considerations, the TiCl4 ¯ow rate for SOI wafers was maintained at 8% of the maximum ¯ow or about 0.54 sccm. 3.2. Deposition on ultra-thin Si ®lm
Ê Si Fig. 2. Sheet resistance of CVD titanium silicide ®lms deposited on 97-A Ê Si ®lm and bulk Si wafer. The ®gure shows that the sheet ®lm, 180-A resistance of silicide ®lm deposited on bulk Si is lower than that formed on very thin Si ®lm.
solid lines. Only positive built-up of Si at the silicide/Si interface was observed, the Si thickness was found to decrease slightly with deposition time. The thickness of silicide and Si deposited at 7% TiCl4 ¯ow or about 0.34 sccm is represented by the dashed line. A positive buildup of Si was observed, but the Si thickness was found to remain unchanged with deposition time. The advantage of deposition at very low ¯ow rate of TiCl4 was to maintain a positive build-up of Si at the interface.
Ê Fig. 3. Sheet resistance of CVD titanium silicide ®lms deposited on 220-A SOI ®lm. Solid line is as-deposited value. Dashed lines are values after RTA annealing at 8508 for 10, 20 and 30 min. The ®gure shows a decrease of sheet resistance with deposition time. The sheet resistance changes very slightly by annealing.
The uniformity of the Si ®lm in SOI wafers may not be constant, therefore it is dif®cult to thin the Si of the SOI Ê . Wafers with ultra-thin Si were wafer to less than 100 A obtained by vapor deposition; the preparation procedure was described in Section 2. Selective deposition of titanium silicide was demonÊ Si ®lm. Sheet resisstrated on wafers with 97- and 180-A tances less than 5 V/sq were achieved with less than 60 s of deposition time. Fig. 2 shows that the sheet resistance of Ê Si was very silicide ®lms formed on 97- Si and on 180-A Ê Si similar. The thickness of silicide ®lm deposited on 180-A Ê after 44 s was about 780 A. This was measured by crosssectional SEM. The thickness of silicide deposited under the Ê. same condition on bulk Si test wafers was about 1000 A The difference can be due to the effect of Si thickness or the difference of Si surface condition. This work indicated that silicide deposition on ultra-thin SOI wafers was very feasible. It also indicated that silicide thickness on SOI wafer could be thinner than that on Bulk Si test wafers. 3.3. Deposition on SOI ®lm and on polysilicon lines CVD silicide ®lm was deposited on SOI and on polysilicon structures. The deposition time varied from 24 to 36 s.
Ê Fig. 4. Sheet resistance of CVD titanium silicide ®lms deposited on 450-A SOI ®lm. Solid line is as-deposited value. Dashed lines are values after RTA annealing at 8508 for 10, 20 and 30 min. The ®gure shows a decrease of sheet resistance with deposition time. The sheet resistance increases slightly at shorter deposition time.
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Ê Fig. 5. Sheet resistance of CVD titanium silicide ®lms deposited on 3500-A thick polysilicon lines. The polysilicon line-width is 5 and 0.5 mm. The ®gure shows a decrease of sheet resistance with deposition time. The results on 5 and 0.5 mm lines are very similar.
Ê Fig. 6. Sheet resistance of CVD titanium silicide ®lms deposited on 3500-A polysilicon lines. Polysilicon line-width is 0.5 mm. Solid line is as-deposited value. Dashed lines are values after RTA annealing at 8508 for 10, 20 and 30 min. the ®gure shows decrease of sheet resistance with deposition time. Subsequent annealing causes an increase in sheet resistance.
The sheet resistance measured after deposition is shown as solid lines from Fig. 3±6. Fig. 3 and Fig. 4 are results of silicide ®lms deposited on SOI structures with 220- and 450Ê Si ®lms. Fig. 5 and Fig. 6 are the results of the ®lms A deposited on 5 and 0.5 mm polysilicon lines. The sheet resistance was found to decrease with deposition time. After 26±28 s the slope of the resistance curves became constant. This was observed in both SOI and polysilicon cases, most likely due to the complete transition into C54 phase. Fig. 5 is the result from polysilicon lines. The ®lm resistance deposited on 0.5 and 5 mm polysilicon lines was almost the same. One can therefore say that the time to form C54 phase during CVD deposition of titanium silicide is not a factor of polysilicon line-width.
Fig. 7 show SEM micrographs of a SOI structure after silicide deposition. It shows a 0.3-mm polysilicon line and a source/drain structure. The background area is buried oxide. Ê before The Si thickness on the source/drain area was 220 A silicide deposition. The silicide deposition was very selective; bridging or residue across the oxide spacer was not detected by electrical measurement. Fig. 8 is an Auger Ê SOI depth pro®le of the silicide ®lm deposited on a 220-A structure. The composition is constant throughout the depth of the ®lm. The silicide thickness of a few samples was measured by cross-sectional TEM and SEM. After a 35-s deposition, the Ê , the silithickness of silicide on SOI was about 650±700 A Ê. cide on polysilicon was about 900±1000 A
Fig. 7. SEM micrographs of CVD TiSi2 deposited on gate and source/drain or SOI wafer. The deposition time was 30 s. (a) Top view of gate line going across Ê Si before silicide deposition. (b) Silicide ®lms formed on polysilicon (top line structure connected to a the source/drain structure. Source and drain are 220-A polysilicon pad) and on Si of the source/drain structure.
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Ê SOI; deposition time was 35 s. The ®gure shows a uniform disilicide ®lm extended Fig. 8. Auger depth pro®le of CVD silicide which was deposited on 220-A to the oxide surface.
3.4. Thermal stability of CVD titanium silicide Titanium silicide ®lms were annealed in N2 ambient at 8508C in a RTA system. The wafer was removed from the RTA unit after every 10-min annealing to measure its sheet resistance. The results are also shown in Fig.3,4 and Fig. 6. Fig. 3 and Fig. 4 are results obtained from silicide ®lms deposited on SOI structures. Titanium silicide ®lms deposÊ SOI and on 450-A Ê SOI were quite stable after ited on 220-A 8508C, 30-min annealing. Fig. 6 was from silicide ®lms
Fig. 9. Sheet resistance of CVD titanium silicide ®lms after phosphorus implantation and RTA anneal. The ®gure shows the high sheet resistance after implantation and the decrease of sheet resistance by subsequent consecutive annealing.
deposited on 0.5-mm polysilicon structures. Increase of sheet resistance is observed, which depends on silicide deposition time and annealing time. If the deposition time is longer than 35 s, the silicide ®lm is found to be quite stable at 8508C. 3.5. Effect of ion implantation SOI wafers with silicided SOI and polysilicon structure were implanted with phosphorus or BF2 at energy of 60 keV
Fig. 10. Sheet resistance of CVD titanium silicide ®lms after BF2 implantation and RTA anneal. The ®gure shows the high sheet resistance after implantation and the decrease of sheet resistance by subsequent annealing.
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with a dose of 5 £ 1015 ions/cm 2. Ion implantation was found to cause an increase in silicide sheet resistance. Silicide ®lm deposited on SOI structures showed a far greater increase. A subsequent anneal restored the resistance to a low value. The results are shown in Fig. 9 and Fig. 10. Annealing was performed in N2 ambient in a RTA system. The annealing time was 30 s. Wafer was intermittently removed from the annealing chamber after each annealing step to measure silicide sheet resistance, then returned to the system for annealing at a higher temperature. The temperature increment was 508C. A consistent decrease of sheet resistance with the increase of annealing temperature is observed, especially in the linear region. Once the temperature reaches about 650±7008C, a sudden drop of resistance is observed, probably caused by the restoring of the C54 phase. Silicide deposited on SOI structure shows a greater drop than that deposited on polysilicon ®lm. 4. Summary Previously many laboratories have reported the results of chemical vapor deposition of titanium silicide on bulk silicon wafers. This is the ®rst time this technique is applied to Ê . Selective SOI wafers and to silicon ®lm less than 100 A chemical vapor deposition of titanium silicide on Si ®lm Ê was demonstrated. Deposiwith thickness less than 100 A Ê SOI struction was also demonstrated on 220- and 450-A tures and on polysilicon lines. The titanium silicide ®lms deposited on thin Si and SOI ®lms were thinner than the silicide ®lms deposited on bulk Si wafers and on polysilicon lines. Silicide ®lms deposited on SOI structures were stable at 8508C. Films deposited on polysilicon showed resistance increases at 8508C. Films were stable if the deposition time was longer than 35 s. Phosphorus and BF2 implantation
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caused resistance to increase; the increase on SOI structure was the highest, followed by that on 5-mm polysilicon structures. The increase from 0.5-mm polysilicon structure was the lowest. Subsequent RTA annealing at temperatures around 650±7008C restored the sheet resistance to a low value. From the results of this work it is clear that selective CVD technique can be applied to SOI technology even with very thin silicon ®lm. References [1] J.-S. Maa, Proc. 11th VLSI Multilevel Interconnection Conf., Santa Clara, CA, 1994, p. 484. [2] J. Chen, J.-P. Colinge, D. Flandre, R. Gillon, J.P. Raskin, D. Vanhoenacker, J. Electrochem. Soc. 144 (1997) 2437. [3] K. Azuma, A. Kishi, M. Tanigawa, et al., Proc. 1995 Int. SOI Conf., p. 30. [4] L.P. Hobbs, K. Maex, Appl. Surf. Sci. 53 (1991) 321. [5] R.W. Mann, L.A. Clevenger, J. Electrochem. Soc. 141 (1994) 1347. [6] J. Lasky, J. Nakos, O. Cain, P. Geiss, IEEE Trans. Electron Devices 38 (1991) 2629. [7] H.K. Park, J. Sachitano, M. McPherson, T. Yamaguchi, G. Lehman, J. Vac. Sci. Technol. A 2 (1984) 264. [8] V. Ilderem, R. Reif, J. Electrochem. Soc. 135 (1988) 2590. [9] J.L. Regolini, D. Bensahel, G. Bomchil, J. Mercier, Appl. Surf. Sci. 38 (1989) 408. [10] A. Bouteville, A. Royer, J.C. Remy, J. Electrochem. Soc. 134 (1987) 2080. [11] A. Bouteville, C. Attuyt, J.C. Remy, Appl. Surf. Sci. 53 (1991) 11. [12] D.B. Gladden, C.E. Weintraub, M.C. Ozuturk, Mater. Res. Soc. Symp. Proc, Vol. 402 p. (1996) 295. [13] K. Saito, T. Amazawa, Y. Arita, J. Electrochem. Soc. 140 (1993) 513. [14] J. Engqvist, U. Jansson, J. Lu, J.-O. Carlsson, J. Vac. Sci. Technol. A 12 (1994) 161. [15] J.-P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, , Kluwer Academic, Boston,MA, 1997 p. 123. [16] J.-S. Maa, S.T. Hsu, B. Ulrich, C.H. Peng, Thin Solid Films 308/309 (1997) 570.