Selective growth of GaAs quantum dots on the triangle nanocavities bounded by SiO2 mask on Si substrate by MBE

Selective growth of GaAs quantum dots on the triangle nanocavities bounded by SiO2 mask on Si substrate by MBE

ARTICLE IN PRESS Journal of Crystal Growth 268 (2004) 369–374 Selective growth of GaAs quantum dots on the triangle nanocavities bounded by SiO2 mas...

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ARTICLE IN PRESS

Journal of Crystal Growth 268 (2004) 369–374

Selective growth of GaAs quantum dots on the triangle nanocavities bounded by SiO2 mask on Si substrate by MBE Y.B. Zhenga,c, S.J. Chuab,c,*, C.H.A. Huana,c, Z.L. Miaoc a

Surface Science Laboratory, Department of Physics, National University of Singapore, 2 Science Drive 3, Singapore 117542, Singapore b Department of Electrical and Computer Engineering, Center for Optoelectronics, National University of Singapore, 4 Engineering Drive 3, Singapore 117576, Singapore c Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602, Singapore

Abstract Selective molecular-beam epitaxy (MBE) growth of GaAs quantum dots (QDs) on the uniform and periodic arrays of triangle nanocavities bounded by SiO2 mask on Si substrate has been realized. These triangle nanocavities with vertical sidewalls, known as windows, are obtained on Si substrate with thin layer SiO2 on the surface by combining inductively coupled plasma etching and nanosphere lithography. MBE growth conditions are optimized to achieve a vanishingly small sticking coefficient of incident Ga atoms on the SiO2 surface and a near unity sticking coefficient on the open triangle Si substrate surface, achieving selective growth of GaAs QDs on these triangle nanocavities. r 2004 Elsevier B.V. All rights reserved. PACS: 61.16.Ch; 61.66.Fn Keywords: A1. Atomic force microscopy; A3. Molecular beam epitaxy; B1. Quantum dots; B2. Semiconducting III–V materials

1. Introduction As the optoelectronic integrated-circuit (OEIC) technology progresses, it is strategic to realize the epitaxial growth of III–V compound semiconductors on Si substrate, the basis of an electronic circuit. On the other hand, the fabrication of quantum dots (QDs) has attracted intense interests

*Corresponding author. Department of Electrical and Computer Engineering, Center for Optoelectronics, National University of Singapore, 4 Engineering Drive 3, Singapore 117576, Singapore. Tel.: +65-68744784; fax: +65-67791103. E-mail address: [email protected] (S.J. Chua).

due to the potential applications in optoelectronics [1–7]. Various approaches to fabricating QDs have been reported. The most noticeable examples were self-assembled molecular beam epitaxy (MBE) growth [8–10] and site-controlled growth on patterned substrate. The former process showed that the ordering of QDs was not sufficient to form a predictable pattern. The latter process required conventional lithography, such as e-beam lithography and X-ray lithography which are characterized by high cost and low throughput [11,12]. Recently, the efficient and low-cost methods, known as ‘‘nanolithography’’, have been used to fabricate nano-size pattern for QD growth, e.g.

0022-0248/$ - see front matter r 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2004.04.056

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self-organized anodic oxidation of aluminum [2] and nanoimprinting [4]. Deckman’s ‘‘natural lithography’’ in 1982 [13] was renamed as nanosphere lithography (NSL) [14,15], and the method was further extended by Haes et al. [16]. Such a lithography technology becomes more flexible and is capable of producing well-ordered, 2D periodic arrays of QDs from a wide variety of materials on many substrates. Many groups have used NSL to fabricate all kinds of nanostructures, including metal [17–19], semiconductor [20–23] and magnetic nanostructures [24]. In contrast to conventional lithography, NSL is inexpensive and highthroughput. In this letter, by using NSL and inductively coupled plasma (ICP) etching, we fabricated the uniform and periodic arrays of triangle nanocavities with vertical sidewalls bounded by SiO2 on Si substrate. MBE growth conditions are optimized to achieve selective growth of GaAs QDs on these triangle nanocavities.

2. Experiment A thin layer SiO2 was grown on Si(1 0 0) substrate by dry oxidation at a temperature of 900 C for 1 h. The flow of O2 and N2 is 3000 and 150 cc/min, respectively. The resultant oxide thickness is 8 nm measured by ellipsometry. The uniform latex particles used in our experiment are monodisperse polystyrene (PS) microspheres (diameter: 300 nm) suspended in distilled water (concentration: 10%). The closely packed monolayer and double layer patterns are formed after spinning the substrate with a droplet of PS microsphere suspension on the center at a proper speed for a certain duration. A photoresist spinner was used for this purpose. ICP etching with CF4 gas system was used to transfer the closely packed pattern triangle nanocavity array onto the substrate. The PS particles were removed in alcohol with ultrasonic agitation for 2 min. The fabrication process flow is illustrated in Fig. 1. The selective growth of GaAs between Si and SiO2 was achieved at the following MBE growth condition: chamber growth temperature is 600 C;

Ratio of As/Ga is 15; BEP of Ga is 2  10 8 Torr. Totally, 6-nm GaAs was grown. The surfaces and the cross sections of the samples were characterized by atomic force microscopy (AFM) and the GaAs QDs were revealed after selectively etching away the upper SiO2 on Si substrate by 10% HF solution.

3. Results and discussion In Fig. 2, we show the AFM images of the two triangle nanocavity arrays bounded by SiO2 on Si substrates after ICP etching and removing away the PS microspheres. In Fig. 2(a), the AFM image reveals perfect and isolated triangle nanocavities arranged on the substrate. However, the AFM image in Fig. 2(b) shows that the triangle nanocavities are not isolated from each other thoroughly; instead, the upper parts are connected by the shallow channels. There are two reasons for this phenomenon. One is that the PS microspheres are not arranged tightly enough within the monolayer; the other is because there is a deviation in the ICP etching of small feature size. Such a connection could result in poor confinement of GaAs QDs within the individual nanocavity; therefore only the double layer pattern is used for further MBE growth. For a better understanding of the configuration of the single triangle nanocavity, a brief discussion of the relation between the diameter of PS microsphere and the side dimension of the triangle nanocavity will be helpful. The depth of the triangle nanocavity that is controlled by ICP etching will be discussed later. Fig. 3 gives a sketch of the geometrical relation between the diameter of PS microsphere (D) and side dimension of the triangle nanocavity (W). If D=L, then WD0.268L. To have the triangle nanocavities within SiO2 (thickness: 8 nm) with Si at the bottom, the depth of the triangle nanocavities was controlled to be around 10 nm by ICP etching. Fig. 4 shows the cross-sectional analysis of an AFM image of triangle nanocavities within SiO2 on Si(1 0 0) substrate. From the cross-sectional analysis, we can see that the horizontal distance (known as the

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SiO2

Spinning

(a)

(b)

ICP etching

Si

CF4 plasma

Triangle nanocavity

PS particles Removing PS

X 0.500 µm /div Z 40.000 nm /div

(d)

(c) Fig. 1. Schematic of the fabrication of triangle nanocavity array bounded by SiO2 mask on Si substrate using the closely packed PS particle double layer as resist mask: (a) a droplet of PS solution is pipetted onto the SiO2 surface; (b) SEM image of closely packed PS particle double layer after spinning; (c) ICP etching using CF4 gas; (d) AFM image of an order triangle nanocavity array bounded by SiO2 on Si substrate after removal of PS particles.

Fig. 2. AFM images of the two types of triangle nanocavity arrays achieved on Si substrate with SiO2 on the surface: (a) double layer; (b) monolayer.

side dimension of triangle nanocavity W) is 81.299 nm, identical to the value given by the equation WD0.268L, since the diameter of PS microspheres D=L=300 nm. With the depth of 11.698 nm, the bottom of the nanocavities has

gone into the Si substrate since the thickness of the upper SiO2 layer is 8 nm. Fig. 5 shows the relation between MBE growth temperature T and SGaAs SiO2 : SGaAs SiO2 is defined as the fractional area coverage by GaAs on an

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101

D=L

100

SGaAs-SiO2

10-1 10-2 10-3 10-4

W = 0.268L

Fig. 3. Sketch of the geometrical relation between the diameter of PS microsphere (D) and the side dimension of the triangle nanocavity (W).

Fig. 4. Cross-sectional analysis of AFM image of triangle nanocavities within SiO2 on Si(1 0 0) substrate.

unpatterned wide-area SiO2 surface for a given set of growth temperatures (BEP of Ga: 2  10 8 Torr and flow ratio of As/Ga: 15). SGaAs SiO2 decreases rapidly after growth temperature T is higher than 560 C. The decrease of SGaAs SiO2 with an increase in T is because of the reduction of nucleation and growth of GaAs clusters. In contrast, the SGaAs–Si remains close to 1 even when T is at 650 C. Similarly, SGaAs–Si is defined as the fractional area coverage by GaAs on an unpatterned wide-area Si surface. This comparison suggests that the selective growth of GaAs on SiO2 and Si surfaces is possible if growth temperature T is within the range from 560 C to 650 C. In our experiment, the growth temperature T is properly controlled at 600 C.

10-5 480 500 520 540 560 580 600 620 640 660 680 700 MBE growth temperature T (°C)

Fig. 5. A plot of the relation between MBE growth temperature T and SGaAs SiO2 at the same BEP of Ga (2  10 8 Torr) and flow ratio of As/Ga (15).

The pre-patterned substrate was further cleaned using only RCA1 in order to protect the SiO2 on the surface. De-oxidation was carried out under silicon flow (BEP= 4.0  10 7 Torr) for a short time to just remove the native oxide at the bottom of the triangle nanocavities in the MBE chamber. Fig. 6 shows the AFM images of the after-growth substrate and the resultant GaAs QDs after selectively etching away the upper SiO2 layer on the substrate. In Fig. 6(a), the top view image reveals that there is very little change on the substrate surface after growth. However, the corresponding cross-sectional analysis reveals that the triangle nanocavities become shallower after growth indicating the existence of GaAs in the nanocavities. Fig. 6(b) reveals that the GaAs QDs have selectively grown on the nanocavities after selectively etching away the upper SiO2 layer by 10% HF solution. The diameter of these QDs is identical to the side dimension of the nanocavities and the height corresponds to the thickness of grown GaAs layer, which shows that there is no diffusion-related growth mechanism involved. The deeper holes beside the GaAs QDs come from the exposed triangle nanocavity tips at the bottom where the Ga and As atoms could not reach because of tilted source beams in our MBE system and limited diffusion of Ga on the SiO2 and Si surfaces.

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Fig. 6. AFM images of the after-growth substrate and the resultant GaAs QDs after selectively etching away the upper SiO2 layer on the substrate.

4. Conclusion We have demonstrated selective growth of GaAs QDs on the uniform and periodic arrays of triangle nanocavities bounded by SiO2 mask on Si substrate. The triangle nanocavity arrays were achieved by NSL, which is inexpensive and high-throughput. The MBE growth temperature effects on the sticking coefficient of incident Ga atoms on the surfaces of SiO2 and Si were investigated and a vanishingly small sticking coefficient of incident Ga atoms on the SiO2 mask and a near unity sticking coefficient on the open triangle Si substrate surface were afforded at 600 C. Acknowledgements The authors would like to thank the National University of Singapore and the Institute of Materials Research and Engineering for financial support. References [1] Y. Honda, Y. Kawaguchi, Y. Ohtake, S. Tanaka, M. Yamaguchi, N. Sawaki, J. Crystal Growth 230 (2001) 346.

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