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Semiconductor manufacturing in Central Europe
812
World Abstracts on Microelectronics and Reliability
epitaxial-silicon deposition. Constantly-advancing IC technology is continually forcing the development of more advanced epitaxial reactors.
Semiconductor manufacturing in Central Europe. BRIAN DANCE. Semiconductor Int. 48 (November 1983). This report 5. M I C R O E L E C T R O N I C S - - D E S I G N A strategy for rule verification shrinks LSI layouts. CLARK BECK and STEVE HARDY. Electronics 141 (15 December 1983). Product-specific design rules cut die size; automated approach assigns optimal alignment aids.
Parametric test system update. PETER H. SINGER. Semiconductor Int. 84 (September 1983). Programmable parametric test systems are used for the evaluation of test patterns for process control and device characterization in integrated circuit manufacturing operations. Improved electrical performance required for future MOS packaging. LEONARD W. SCHAPER and DANIEL I. AMEY. IEEE Trans. Components Hybrids Mf9 Technol. Chmt-6 (3), 283 (September 1983). High speed integrated circuit (IC) families and the demands which these devices place on interconnection and power systems are compared, concluding that new materials, components, and packaging techniques arc required to provide a nonlimiting electrical environment for high performance systems using metal-oxide semiconductor (MOS) technologies.
A new chip carrier for high performance applications: integrated decoupling capacitor chip carrier (IDCCC). CHRISTIAN M. VAL and JACQUESE. MARTIN. IEEE Trans. Components Hybrids Mf9 Technol. Chmt-6 (3), 290 (September 1983). The impact of inductance has rarely been considered in semiconductor packaging. This is the reason for using the capacitor in the first place: it is a small, local energy reservoir for those current transients which cannot go back to the power supply without causing unacceptably large voltage drops (V = Ldi/dt). Since 1978 a new chip carrier with integrated decoupling capacitor (IDCCC) has been studied. The capacitor is located inside the bottom layer in a three-layer or a single-layer chip-carrier. The ceramic package previously used had a nonactive bonding pad layer: with our IDCCC, this layer (standard thickness is 25mils) is made out of several layers from 3 to 5mils with the electrodes. The technology is about the same as the one used in multilayer ceramic capacitors. This capacitor is located just under the device, but not under the conductor I/O to avoid a parasitic capacitive coupling. With the coming of lcadless and leaded full array chip carriers such as pin grid array, we applied the same concept with a capacitor inside the cap. The results with different current-pulse signals show the effects of the capacitor's inductance, resistance, and capacitance. The main specifications of this new chip carrier will be presented. In addition to improving speed and electrical performances, the IDCCC allows an increase in density and in reliability level.
High pinout IC packaging and the density advantage of surface mounting. WULF H. KNAUSENBERGERand NICHOLAS A. TENEKETGES. IEEE Trans. Components Hybrids Mf9 Technol. Chmt-6 (3), 298 (September 1983). The packaging industry has been addressing the high pinout integrated circuit (IC) packaging issue in recent years. The specific solutions adopted have varied on a case by case basis and appear to be based on meeting a combination of objectives: (1) meeting needs with a workable short term evolution of the current packaging technology, and (2) consistency with long term objectives. The former is usually emphasized over the latter. Extensions of conventional through-hole packages are more directly compatible with the present day dual-in-
will cover the development of semiconductor technology and the companies that are the focal point of this technology in the countries of West Germany, Austria, and The Netherlands. West Germany and Austria share a common language and this has resulted in some of the manufacturers operating fabricating plants in both countries.
AND
CONSTRUCTION
line package (DIP). Surface mounted packages are expected to yield higher board level interconnection densities in the long term. A procedure is utilized which incorporates the Schmidt routability analysis methodology to compute packaged circuit pack level gate densities as a function of various IC, IC package, and printed wiring board (PWB) technology options. The PWB technology options include multilayer approaches spanning a range of combinations of feature sizes and via types. Packaged board level gate densities are compared for state-of-the-art gate array chips packaged in the following IC package options: (1) through hole pin grid array, (2) surface mount pad grid array, and (3) surface mount JEDEC-style chip carriers. The paper will conclude that for the range of interconnection technologies considered there are significant inherent density advantages to surface mounted components such that it is worthwhile overcoming some incompatibility with the ubiquitous DIP package.
Direct attachment of leadless chip carriers to organic matrix printed wiring boards. ROBERT W. KORB and DAVID O. ROSS. IEEE Trans. Components Hybrids M]~; Technol. Chmt-6 (3), 227 (September 1983). A test program was performed that compares the reliability of various leadless chip carrier (LCC) solder joint configurations under conditions of temperature cycling from - 5 5 to + 125°C. Since there is a coefficient of thermal expansion mismatch between the ceramic body of the LCC (6ppm/°C) and that of an epoxy-glass printed wiring board (15ppm/°C), it was of interest to determine the optimum solder joint configuration that results in maximum reliability after extensive exposure to temperature extremes. This configuration was determined to be the one that results in a 45 ° solder fillet; consequently, the distance the printed wiring board (PWB) pad extends beyond the edge of the LCC is a critical requirement. For an 18 pad LCC, this distance is 40mils. Information on the use of various substrates for leadless chip carriers is also discussed.
High thermal conduction package technology for flip chip devices. MASANOBU KOHARA, SHIN NAKAO, KAZUHITO TSUTSUMI, HIROSHI SHIBATA and HIDEFUMI NAKATA. IEEE Trans. Components Hybrids Mr9 Technol. Chmt-6 (3), 267 (September 1983). The technology of new packages with high thermal conduction performance, simplified structure, and also high reliability for flip chip devices is described. In order to obtain high thermal conduction, a thermal conduction plate is individually bonded to the back surface of a large-scale integrated (LSI) chip by soft solder and is arranged in close proximity to the inner surface of the cap, when the chip is assembled together with the cap and substrate. The cavity is then filled with a gas which has a high thermal conductance characteristic. As a result, a large part of the heat is effectively drawn off from the back side of the chip to the air-cooling fin through the plate and across the narrow gap filled with the gas. A series of experiments were conducted on a single chip package and a nine chip multichip module. These tests indicated a junction-to-fin thermal resistance of 3.2°C/W for the single chip package and 4.8°C/W as a worst case in the module. In addition a computer model analysis for thermal conduction was studied using a program named TNET-2. It was found that the calculated values corresponded closely to the measured data. More detailed descrip-
World Abstracts on Microelectronics and Reliability
epitaxial-silicon deposition. Constantly-advancing IC technology is continually forcing the development of more advanced epitaxial reactors.
Semiconductor manufacturing in Central Europe. BRIAN DANCE. Semiconductor Int. 48 (November 1983). This report 5. M I C R O E L E C T R O N I C S - - D E S I G N A strategy for rule verification shrinks LSI layouts. CLARK BECK and STEVE HARDY. Electronics 141 (15 December 1983). Product-specific design rules cut die size; automated approach assigns optimal alignment aids.
Parametric test system update. PETER H. SINGER. Semiconductor Int. 84 (September 1983). Programmable parametric test systems are used for the evaluation of test patterns for process control and device characterization in integrated circuit manufacturing operations. Improved electrical performance required for future MOS packaging. LEONARD W. SCHAPER and DANIEL I. AMEY. IEEE Trans. Components Hybrids Mf9 Technol. Chmt-6 (3), 283 (September 1983). High speed integrated circuit (IC) families and the demands which these devices place on interconnection and power systems are compared, concluding that new materials, components, and packaging techniques arc required to provide a nonlimiting electrical environment for high performance systems using metal-oxide semiconductor (MOS) technologies.
A new chip carrier for high performance applications: integrated decoupling capacitor chip carrier (IDCCC). CHRISTIAN M. VAL and JACQUESE. MARTIN. IEEE Trans. Components Hybrids Mf9 Technol. Chmt-6 (3), 290 (September 1983). The impact of inductance has rarely been considered in semiconductor packaging. This is the reason for using the capacitor in the first place: it is a small, local energy reservoir for those current transients which cannot go back to the power supply without causing unacceptably large voltage drops (V = Ldi/dt). Since 1978 a new chip carrier with integrated decoupling capacitor (IDCCC) has been studied. The capacitor is located inside the bottom layer in a three-layer or a single-layer chip-carrier. The ceramic package previously used had a nonactive bonding pad layer: with our IDCCC, this layer (standard thickness is 25mils) is made out of several layers from 3 to 5mils with the electrodes. The technology is about the same as the one used in multilayer ceramic capacitors. This capacitor is located just under the device, but not under the conductor I/O to avoid a parasitic capacitive coupling. With the coming of lcadless and leaded full array chip carriers such as pin grid array, we applied the same concept with a capacitor inside the cap. The results with different current-pulse signals show the effects of the capacitor's inductance, resistance, and capacitance. The main specifications of this new chip carrier will be presented. In addition to improving speed and electrical performances, the IDCCC allows an increase in density and in reliability level.
High pinout IC packaging and the density advantage of surface mounting. WULF H. KNAUSENBERGERand NICHOLAS A. TENEKETGES. IEEE Trans. Components Hybrids Mf9 Technol. Chmt-6 (3), 298 (September 1983). The packaging industry has been addressing the high pinout integrated circuit (IC) packaging issue in recent years. The specific solutions adopted have varied on a case by case basis and appear to be based on meeting a combination of objectives: (1) meeting needs with a workable short term evolution of the current packaging technology, and (2) consistency with long term objectives. The former is usually emphasized over the latter. Extensions of conventional through-hole packages are more directly compatible with the present day dual-in-
will cover the development of semiconductor technology and the companies that are the focal point of this technology in the countries of West Germany, Austria, and The Netherlands. West Germany and Austria share a common language and this has resulted in some of the manufacturers operating fabricating plants in both countries.
AND
CONSTRUCTION
line package (DIP). Surface mounted packages are expected to yield higher board level interconnection densities in the long term. A procedure is utilized which incorporates the Schmidt routability analysis methodology to compute packaged circuit pack level gate densities as a function of various IC, IC package, and printed wiring board (PWB) technology options. The PWB technology options include multilayer approaches spanning a range of combinations of feature sizes and via types. Packaged board level gate densities are compared for state-of-the-art gate array chips packaged in the following IC package options: (1) through hole pin grid array, (2) surface mount pad grid array, and (3) surface mount JEDEC-style chip carriers. The paper will conclude that for the range of interconnection technologies considered there are significant inherent density advantages to surface mounted components such that it is worthwhile overcoming some incompatibility with the ubiquitous DIP package.
Direct attachment of leadless chip carriers to organic matrix printed wiring boards. ROBERT W. KORB and DAVID O. ROSS. IEEE Trans. Components Hybrids M]~; Technol. Chmt-6 (3), 227 (September 1983). A test program was performed that compares the reliability of various leadless chip carrier (LCC) solder joint configurations under conditions of temperature cycling from - 5 5 to + 125°C. Since there is a coefficient of thermal expansion mismatch between the ceramic body of the LCC (6ppm/°C) and that of an epoxy-glass printed wiring board (15ppm/°C), it was of interest to determine the optimum solder joint configuration that results in maximum reliability after extensive exposure to temperature extremes. This configuration was determined to be the one that results in a 45 ° solder fillet; consequently, the distance the printed wiring board (PWB) pad extends beyond the edge of the LCC is a critical requirement. For an 18 pad LCC, this distance is 40mils. Information on the use of various substrates for leadless chip carriers is also discussed.
High thermal conduction package technology for flip chip devices. MASANOBU KOHARA, SHIN NAKAO, KAZUHITO TSUTSUMI, HIROSHI SHIBATA and HIDEFUMI NAKATA. IEEE Trans. Components Hybrids Mr9 Technol. Chmt-6 (3), 267 (September 1983). The technology of new packages with high thermal conduction performance, simplified structure, and also high reliability for flip chip devices is described. In order to obtain high thermal conduction, a thermal conduction plate is individually bonded to the back surface of a large-scale integrated (LSI) chip by soft solder and is arranged in close proximity to the inner surface of the cap, when the chip is assembled together with the cap and substrate. The cavity is then filled with a gas which has a high thermal conductance characteristic. As a result, a large part of the heat is effectively drawn off from the back side of the chip to the air-cooling fin through the plate and across the narrow gap filled with the gas. A series of experiments were conducted on a single chip package and a nine chip multichip module. These tests indicated a junction-to-fin thermal resistance of 3.2°C/W for the single chip package and 4.8°C/W as a worst case in the module. In addition a computer model analysis for thermal conduction was studied using a program named TNET-2. It was found that the calculated values corresponded closely to the measured data. More detailed descrip-