Sequential substrate and channel hot electron injection to separate oxide and interface traps in n-MOSTs

Solid-State ElecrroniesVol.38, No. I, pp. 105-I 13, 1995 Copyright 0 1995 Elsevier Science Ltd 0038-l lOl(!M)EOO38-G Printed in Great Britain. All rights reserved 0038-l IO1195 $9.50 + 0.00

Pergamon

SEQUENTIAL SUBSTRATE AND CHANNEL HOT ELECTRON INJECTION TO SEPARATE OXIDE AND INTERFACE TRAPS IN n-MOSTs K. MICHAEL HAN and TOSHIKAZUNISHIDA Florida Solid-State Electronics Laboratory, Department of Electrical Engineering, University of Florida, Gainesville, FL 32611, U.S.A. (Received I November 1993; in revised form

7 February 1994)

Abstract-h

the present work oxide traps present in the gate oxide of n-channel MOS transistors (n-MOSTs) are filled by substrate hot electron (SHE) injection prior to channel hot electron (CHE) injection stress. By employment of SHE to fill existing oxide traps at low fields without generating interface traps, the contributions of oxide trap charging and interface trap generation on CHE induced n-MOST

degradation may be separated. Using this sequential two-stage SHEjCHE stress, it is shown that (1) oxide trap charging and interface trap generation contribute to the threshold voltage shift and subthreshold distortion during short stress duration and (2) after the existing oxide traps are filled. interface trap generation dominates during long stress duration.

1. INTRODUCTION Hot carrier effects in short-channel metaloxide-semiconductor transistors (MOST) have generated considerable interest for technological and fundamental reasons since an understanding of the mechanisms involved would allow a prediction of the degradation rate of the MOST during electrical operation[l]. The hot carrier effects include threshold voltage shift, AVT, and transconductance degradation, Ag,/g,,,, initiated by electrons accelerated to high kinetic energies by the electric field in the n-channel MOST (n-MOST) and holes in p-channel MOST (p-MOST)[2]. Since the electric field increases as the physical dimensions are reduced at constant or near-constant voltages, hot carrier effects become more severe and thus are of increased concern in scaled-down MOST technologies[3]. Although it is clear that hot carrier effects in MOSTs are due to charging of the metal-oxidesilicon structure[4-191, a consensus has not been reached on the relative importance of charged oxide and interface traps. The parallel shift of the drain current-gate voltage characteristics (1,-V,), distortion of the subthreshold slope, and transconductance degradation have been used to measure oxide and interface trap charge densities[20-22,281. From an observed linear relation between the threshold voltage shift, AV,, subthreshold slope shift, AS, and transconductance degradation, Ag,/g,,,, after CHE stress at several drain voltage-gate voltage combinations. Hu et al., concluded that interface trap generation was the dominant degradation mechanism[20]. A similar linear relation has been reported under uniform substrate injection[21]. However,

localized oxide charge near the drain junction has also been shown to distort the 1,-V, characteristics[l I]. Interface trap generation was estimated to be responsible for 90% of the degradation at Vo = 6 V and V,, = 8 V (L = 2 pm) in the conventional thermal oxide with low trap density while electron trapping was found to be dominant in the oxide with a high density of oxide traps[22]. From charge pumping measurement[23-251, hole trapping was found to be the main constituent of AV, at low gate voltage, VG z VT < V,,, while interface trap generation at Vc g V,/2 was suggested by the large AI,, and small AVbase. Oxide trap charging was suggested at higher gate voltage, VG z V,,[24]. However, acceptor-type interface traps located very near the drain junction can result in a negative shift of the transition edge which may mask the positive shift due to electron trapping[25]. Tsuchiya et a/.[261 concluded that electron trapping was primarily responsible for the observed degradation from measurements of the parallel shift, A VT. under uniform electron injection, and distortion of the I,,-V, characteristics after CHE electron injection (V, = 2.2 V, V. = 5.5 V) which recovered after hole injection ( VC; = 0.6 V, V,, = 5.5 V). 2D device simulation suggested that CHE-induced degradation may be explained mainly by interface trap generation[27]. The spatial distribution of the oxide traps has also been shown to affect the distortion of the I,-V,[ll,26]. In this paper, we propose a new sequential stress procedure to separate the effects of oxide and interface traps. The oxide traps in n-MOST are first filled by spatially uniform substrate hot electron (SHE) injection, then the CHE stress is applied at Vc 2 I-‘,/2 on the same device. From the threshold voltage shift I05

K. MICHAELHAN

106

and TOSHIKAZUNISHIDA

underwent the two-stage SHE/CHE stress. Group-B (CHE-only control) transistors were stressed at the same CHE stress conditions as in stage II of the group A transistors. The methodology of the twostage SHE/CHE stress is described in the Section 2.2.

and subthreshold slope shift during CHE stress on the device with oxide electron traps intentionally filled compared with that on a fresh device with no electron pre-injection, it is shown that (1) oxide trap charging and interface trap generation both occur during saturation CHE stress and (2) after the oxide traps are filled, further degradation is dominated by interface trap generation.

2.2. Methodology

of two-stage

SHEICHE

technique

In stage I, SHE injection using the nonavalanche forward-biased emitter-base injection method described previously[2!9-311 is used to fill the existing (as-fabricated) oxide electron traps uniformly over the entire gate oxide area of the n-MOST. The injection is stopped when the total injected fluence reaches a pre-specified value. In stage II, the same n-MOST is stressed by CHE in the current saturation range ( Vns = 7.0 V, Vos = 2.5 V). The effect of filling the oxide electron traps prior to CHE stress on the threshold voltage shift and subthreshold distortion is discussed in Section 3. The details of stage-I SHE injection and stage-II CHE injection are given in Sections 2.2.1 and 2.2.2, respectively.

2. EXPERIMENTALPROCEDURE

2.1. Test structure The test structure used is a junction-isolated Nchannel MOST fabricated in a conventional CMOS process. The n-MOST transistor used has a drawn channel length of 1.6 pm and a width of 100 pm. The gate oxide, thermally grown at 850 “C in a dry oxidation ambient, is 17 nm thick. The transistors used in this experiment were separated into two groups: A and B. Group-A (SHE/CHE) transistors

N-epitaxlal layer

N+ substrate

T 1Kf-J

EMllTER

Vc0+k3

= 1

;

SHEi: SubstrateHot Electroninjection ETEi: EmitterThermalElectroninjection Fig. 1. Experimental setup for BiMOS substrate electron injection.

Oxide and interface traps in n-MOSTs

107

svox EC Et _______--~ &

EV

I

Spacechargeregion ..____________

4 I

n+sigate

SiO,

I

,

1 n+Si

psi

I-

IFig. 2. Energy band diagram of BiMOS substrate electron injection.

2.2.1. Stage I SHE injection. In Stage I, electrons are injected into the gate oxide using SHE injection (SHEi) in the BiMOS transistor consisting of the n-MOST in p-well on the n/n + substrate. A forwardbiased n + substrate/p-well emitter/base junction is employed to supply electrons which are accelerated and injected into the gate oxide of the nMOST[30,31]. This technique was used previously to investigate the oxide field and temperature dependence of oxide trap charging, discharging, generation, and annealing rates[8,3&32]. Figure 1 gives the cross-section of the BiMOS transistor with bias voltages shown for SHEi and identifies the gate, source (collector), drain (collector), p-well (base), and substrate (emitter) electrodes. The energy band diagram of the BiMOS transistor biased in SHEi mode is shown in Fig. 2. The SHEi technique[29-311 is now reviewed. A positive voltage applied between the gate and the source and drain junctions which are connected together inverts the channel underneath the gate oxide. This inverted n-channel, together with the n + source and drain junctions, serves as the collector for the vertical n +/p/n - channel bipolar transistor. Thep-well is the base and the n -/n + epitaxial substrate serves as the electron emitter. The emitter/base junction is forward-biased to inject electrons into the p-well base. These injected electrons diffuse upwards through the p-well and are accelerated towards the Si/SiO* interface by the electric field in the space-charge layer of the reverse-biased collector/base n-channel/p-well junction. The reverse bias, Vce, provides the accelerating field for these electrons. These electrons,

injected from the substrate and accelerated, may acquire sufficient energy in the Si space-charge layer to surmount the Si/SiOz barrier (3.1 eV). When the channel is strongly inverted, Vcs will be the potential difference between the hole quasi-Fermi potential, VP= FJq, in the p-well and the electron quasi-Fermi potential, V, = FN /( -q), at the Si/SiOz interface. The minimum Vc, that must be applied to accelerate the injected electrons into the gate oxide is 3.1 V which is the Si/SiO, barrier height for electrons. A larger Vce will enhance the electron emission efficiency appreciably but the energetic and hot electrons at the interface may break the weak interfacial bonds via direct impact to create new interface traps[l5,16] which we want to avoid in stage I. In addition, it is desirable to minimize the field encroachment between the reverse-biased source/well and drain/well junctions in order to maintain spatially uniform electron injection into the gate oxide. Thus, a small Vcs of 4.0 V is employed. The gate oxide current is maintained constant, within +5% of the initial preset gate current, by digital feedback control of the emitter/base forward bias programmed on a DEC MicroVAX-II computer with National Instruments IEEE-488 interface bus. The oxide electric field, E,,, is given by (V, - Vs)/Xo, The gate electron fluence, F,; or N,,, , is calculated as follows: Fo = s(Jc /q) dt = (Jo 14) . Lm

(1) (2)

where Jo is the constant gate current density, q is the

108

K.

MICHAEL HAN

and

electronic charge (1.6 x lo-l9 C), and t,,ressis the total stress time in seconds. One key advantage of using SHEi in the BiMOS transistor to fill existing bulk oxide traps in the n-MOST is the independent control of three basic stress parameters, the oxide electric field, the electron kinetic energy, and the injection current[30-321. The oxide electric field is controlled by the voltage applied between the gate electrode and the n + source/drain electrode provided the gate voltage is sufficient to invert the silicon surface layer underneath the gate oxide. The electron kinetic energy in the silicon surface space-charge layer is determined by the reverse bias applied between the n + source/drain and the p-well. Once the electrons are injected into the gate oxide, their kinetic energy can be controlled by the magnitude of the voltage drop across the gate oxide (oxide voltage, Vex). The magnitude of the gate current can be adjusted by the emitter-base forward bias which determines the emitter current, and by the collector-base reverse bias which controls the kinetic energy distribution of the electrons at the Si/SiO, interface[3&32]. Gate current magnitudes range from less than 1 pA to greater than 1 PA. The areally uniform electron injection into the gate oxide during BiMOS SHEi simplifies the analysis of the stage I injection described in Section 3. 2.2.2. Stage II CHE injection. In stage II, the n-MOST in the BiMOS structure is biased in the current saturation range. A cross section of the

TOSHIKAZU NISHIDA

n-MOST with bias connections shown for CHE injection is shown in Fig. 3. The channel electrons are accelerated to large kinetic energy by the large channel electric field in parallel to the SiOr/Si interface near the drain. These energetic or “hot” channel electrons may (i) create interface traps by impact/rupture of weak or strained interfacial bonds, (ii) scatter towards the Si/SiOz interface and surmount the potential barrier to enter the gate oxide and charge existing oxide traps or generate new oxide traps, (iii) create electron-hole pairs by interband impact, or (iv) drift and diffuse to the drain junction[ 11. The CHE stress in n-MOST may be classified by the magnitude of the applied drain-to-source, Vos, and gate-to-source, VGs, voltages. When Vos s VGs, the gate and substrate currents can be directly measured because both are typically greater than 10 pA. When V,, > VGs- VGT, the n-MOST is biased in the drain current saturation range. In saturation, the substrate current is large (> 100 PA) but the gate current is small (< 1 PA). The substrate current is due to the substrate collection of holes generated by interband impact generation of electron-hole pairs by the energetic channel electrons. The maximum substrate current corresponds to the maximum interband impact generation rate of electron-hole pairs and the collection of holes by the p-well electrode. The observed peak substrate current frequently occurs at V,, z Vo,/2. Since maximum

I N-epitaxial layer

I

I

Substrate

Fig. 3. Experimental setup for channel hot electron (CHE) stress.

Oxide and interface

degradation of the n-MOST characteristics is observed at this CHE stress condition, it is employed in the stage II CHE stress.

traps

in n-MOSTs

109

VoKl V)

Eox/(lMV/cm)

3. RESULTS

The oxide electron traps, filled uniformly during the stage I SHEi, affect the n-MOST degradation during the stage II CHEi stress in the group A transistors. This effect is monitored by the magnitude of the threshold voltage shift and subthreshold distortion during the stage II CHE stress. For comparison, control transistors are stressed using the same CHE stress conditions as those in stage II for the entire duration of the two-stage SHEjCHE stress in the group B transistors without prior electron injection. Section 3.1 gives the oxide electric field dependence of the gate voltage and subthreshold slope shifts under SHE injection. Section 3.2 describes the degradation of the tn-If, characteristics stressed under saturationrange CHE stress. Section 3.3 gives the experimental results of the two-stage SHEjCHE stress and compares the two-stage stress with the one-stage CHE stress. 3. I. Oxide trap jilling by low -field SHE injection Figure 4 shows the oxide electric field dependence of the gate voltage shift vs the injected electron fluence at room temperature. The gate voltage shift is extracted from the forward (source and drain in the normal configuration) Ins-V,, curves at a constant drain current of 1.OpA and Vns = 0.1 V. The forward and reverse Ins-Vos curves exhibit identical shift (less than 3% variation between AVG.,,,,,,, and which indicates uniform injection of A I’c-REVERSE electrons into the gate oxide and charging of oxide traps. This is expected for SHE injection because the drain, source and the inversion layer are maintained at the same potential. Thus, the reverse bias applied between the n + source/inversion layer/n + drain and

t

F

V&V)

’ Eox/(lMV/cm)

v 1.5 + 6.0

4.41 3.53

FG /( 1 0"cmm2) Fig. 5. Subthreshold slope shift vs injected electron fluence for different oxide electric fields (0.884.41 MVjcm) at room temperature.

the p-well gives a spatially uniform accelerating field for the electrons in the Si depletion region underneath the gate oxide. Two features can be identified from Fig. 4 which are important for stage I SHE injection. (1) At small oxide electric field (< 3 MVjcm), the gate voltage shift nearly saturates to an asymptotic plateau due to the steady state balance of the electron trapping and detrapping at the existing (as-fabricated) oxide electron traps[30]. This corresponds to parallel shifts of the I,,-VGs and transconductance (gM)-Vcs curves. Least squares fit of the gate voltage shift vs electron fluence at 0.88 MV/cm oxide field indicates oxide trap capture cross sections of (T,= (1.2 f 0.6) x lO--” cm’ and oz = (4.1 f 0.2) x IO-l9 cm?. (2) Generation of interface traps at these low oxide electric fields is small as seen from the negligible distortion in subthreshold slope, As. shown in Fig. 5. Therefore, the gate voltage shift under low-field SHE injection is essentially due to the capture of injected electrons by the existing oxide electron traps. The low-field SHE injection is employed for stage I filling of oxide traps. The gate voltage shift can be described by[33]: A Vo-or = - AQOT/Co = -(q ~~oT/Co)~(.~o,/-~ox)

Fc

/(

1 0"cmB2)

Fig. 4. Gate voltage shift vs injected electron fluence for different oxide electric fields (0.884.41 MVjcm) at room temperature.

(3) (4)

where QOT is the effective areal density of charged oxide trap, Co is the gate oxide capacitance per unit area, .x0x is the oxide thickness, t0 is the oxide permitivity, q is the electron charge, nor is the total area1 density of charged oxide traps ( # /cmz), and xor is the centroid of the charged oxide traps measured from the gate/oxide interface. xOTis assumed equal to x0, in these measurements. At higher oxide electric field (> 3 MVjcm), the gate voltage and subthreshold slope shifts do not saturate in Figs 4 and 5. This has been extensively investigated and is attributed to the generation of new oxide and

110

K.

MICHAEL HAN

and

U A Unstressed

Fig. 6. Forward and reverse IDspVcs characteristics before and after CHE stress measured at V,, = 0.1 V. CHE stress condition is VDs = 7 0 V and VGs = 2.5 V. Stress time is 800 min.

traps[9,10,30]. The injected electrons gain sufficient kinetic energy during transit through the gate oxide, generating new oxide and interface traps. A model based on bond breaking and/or rupturing of the weak or strained intrinsic bonds (Sio 00, Sio lSi bonds) and the weak extrinsic hydrogen bonds (Si-H, Si-O-H) has been proposed to describe the trap generation mechanism[ 15.161.To minimize oxide trap generation during stage I SHEi, an oxide field of 0.88 MV/cm is used to avoid the high field injection. Interface trap generation at the Si/SiOl interface is monitored by the shift in the subthreshold slope as shown in Fig. 5. The interface trap density is given by[34]: interface

As=S(q,,)--S(q,,=O) = 2.303.(kT/q).(C,,/Co),

(5) (6)

where C,, = qD,, and D,, is the density of the interface traps. Interface trap generation during SHE injection is minimized by employing a low oxide field (0.88 MVjcm) during stage I SHE as shown in Fig. 5. In summary, Figs 4 and 5 indicate that new oxide and interface traps are not generated during SHE injection at low oxide electric field (< 3 MVjcm) and small I’,, (4.0 V). Therefore, a low oxide field accelerating potential (0.88 MVjcm) and (Vca = 4.0 V) is employed in stage I SHEi to charge the existing (or as fabricated) oxide electron traps in the gate oxide of the n-MOST prior to CHE stress. 3.2. CHE induced degradation of I,,

TOSHIKAZU NISHIDA

sensitive to the local charge distribution near the source junction[30-321. In the forward configuration, the source and drain connections are identical during CHE stress and I,,,-V,, measurement. In the reverse configuration, the source and drain connections are reversed. Figure 6 shows the forward and reverse I,,- VGs characteristics before and after CHE stress at V,,s = 7.0 V, V,, = 2.5 V for 800 min. Figure 7 plots the transconductance for the same device shown in Fig. 6. In Figs 6 and 7, the electrical characteristics degrade for both forward and reverse configurations. The reverse configuration shows a larger shift and distortion which is indicative of localized damage near the drain junction. The positive threshold voltage shift indicates a net negative charging of oxide traps. Because the electrons are most energetic near the drain junction, the distribution of charged oxide traps is expected to have a spatial dependence between the source and drain junctions. The distortion of the subthreshold slope of the Z,,-V,, charactrap teristics is caused by either interface generation[20] or nonuniform oxide charge distribution near the drain[11,26] or both. Numerical modelling of the MOST predicts a distortion of the subthreshold IDS-Vcs characteristics when a spatially nonuniform oxide charge distribution is located near the interface close to the drain junction[ 11,261. These possible causes of subthreshold distortion are considered in Section 3.3. 3.3. Results of the two-stage

SHEjCHE

stress

The n-MOST transistors were separated into two groups: A and B. Group A (SHE/CHE) transistors underwent the two-stage SHEjCHE stress. Group B (CHE-only, the control) transistors underwent the two-stage SHE/CHE stress, Group B (CHE-only, the control) transistors were stressed at the same CHE stress conditions as in stage II of the group A transistors. In stage I, SHE injection is employed to fill the existing (as-fabricated) oxide electron traps at 1200.0

I I I I

I

I I I

I I I I

UA Unstressab F x Forward configuration 1000.0 -R+ Reverse configuration

VGs character -

istics

Due to the localized high electric field near the drain junction under the CHE stress condition, the electronic traps created by the channel hot electrons at the Si/SiOZ interface and in the SiOZ are localized near the drain junction. Thus, the I,,- VGs characteristics measured in the forward and reverse configurations are asymmetric because the drain current is

vGS/(

1v>

Fig. 7. Forward and reverse g,-V,, characteristics before and after CHE stress measured at V,, = 0. I V. CHE stress condition is V,,s = 7.0 V and Vo, = 2.5 V. Stress time is 800 min.

Oxide and interface traps in n-MOSTs

111

x Group A: Two-stagestress WIWHE) - Group B: One-stagestress (CHBonly) 300.0 T

.

E -

200.0

A"v,m

7 >" Q

.

__---_-___

100.0

A"v,,

500.0

Time/(

I 2000.0

1500.0

1000.0

time/(

1 min)

Fig. 8. Gate voltage shift (at I,, = I PA, forward and reverse configuration) vs stress time of group A transistor and group B control transistor at room temperature. Sk’,, is the gate voltage shift in stage I of the two-stage BiMOSSHE/CHE stress (group A) for a total fluence of 2.8 x lOI*cm-* and total injection time of 2200 min. AV,,, is the gate voltage shift during the stage II CHE stress. A vG-CHE is the total gate voltage shift for group B control transistor. SHE stress conditions are Eox = 0.88 MV/cm and V,, = 4.0 V. CHE stress conditions are V, = 7.0 V and vos = 2.5 v.

electric field (0.88 MV/cm) and low Vcs( =4.0 V). A total electron fluence of 2.8 x 10”q/cm2 electrons is injected int,, the gate oxide. In stage II, the n-MOST is CHE-stressed in the current saturation range ( Vos = 7.0 V, Vo, = 2.5 V). The effect of filling the oxide traps in stage I is examined by the magnitude of the threshold voltage shift, A VoT, and the subthreshold distortion, AS, during the stage II CHE stress. Figure 8 plots the gate voltage shift, AV,, for the two groups of n-MOST (group A and group B) as a function of time. AVo is extracted from the forward and reverse I,,-Vos curves at a constant drain current of 1 p A and Vos = 0.1 V. The reverse measurements a low oxide

60.C

I,,,

III,

III,

II,

Group : Two-stage’(SIWCHE)’ - GroupB: One-stagestress (CHEonly) x

T

4o.c

E 7

30.a

7 q

20.a i 0.0

500.0

Fig.

9.

1000.0

500.0

i500.0

time/( 1 min) Subthreshold slope shift (at

I,,s = 0.1 nA,

V, z 0.10 V, forward and reverse configuration)

vs stress time of group A transistor and group B control transistor at room temperature. SHE stress conditions are E,, = 0.88 MV/cm and V,, = 4.0 V. CHE stress conditions are V,, = 7.0 V and V,, = 2.5 V.

1000.0

1500.0

2000.0

1 min)

Fig. 10. Subthreshold slope shift (at I,, = 1nA, Vs z 0.16 V, forward and reverse configuration) vs stress time of group A transistor and group B control transistor at room temperature. SHE stress conditions are E,, = 0.88 MV/cm and V,, = 4.OV. CHE stress conditions are Vos = 7.0 V and v,, = 2.5 v.

probe the degradation near the drain junction. Figures 9 and 10 plot the subthreshold slope shift, AS, vs time for the group A and B n-MOST. The subthreshold slope shift is extracted at a constant drain current of 0.1 nA ( Vs z 0.10 V) and 1 nA ( Vs s 0.16 V), respectively. The surface potential, V,, is estimated by comparing the subthreshold IDS-Vos curve of an unstressed n-MOST with the C,- Vo curve of a 200 x 200 pm capacitor located on the same wafer. The gate voltage shift of the group A n-MOST which underwent the two-stage SHE/CHE injection plotted in Fig. 8 consists of two parts: A Vo = A Vo_oT+ A Vo.,r

(7)

In Section 3.1, the gate voltage shift was shown to saturate to an asymptotic plateau during low field SHE injection. This was attributed to the steady stage balance of electron trapping and detrapping at existing oxide electron traps and negligible generation of interface traps. Therefore, the gate voltage shift in stage I SHE injection can be attributed to the filling of bulk oxide electron traps. Since the electron emission is negligible at 0.88 MV/cm oxide fieldj321, most of the bulk oxide electron traps are filled with electrons. The electron fluence used in stage I fills the oxide traps with capture cross sections larger than l/2.8 x 10’8cm-2 =4 x 10m’9cm2. The gate voltage shift due to the charging of existing oxide electron traps during stage I stress is given by AL’,_,, in eqn (7). The gate voltage shift extracted from the forward and reverse configuration ~os-Vos curves is identical in stage I which is expected for the uniform injection and oxide trap charging under SHE injection stress. The gate voltage shift during stage II CHE stress is denoted by AVo.,,. The gate voltage shift in stage II, AVo.,,., is attributed to the generation of interface traps during the CHE stress because the existing oxide traps with capture cross sections larger than

112

K.

MICHAELHAN and TOSHIKAZUNISHIDA

3 x 1O-‘9 cm’ are already filled during stage I although some smaller cross section traps may be charged. A larger gate voltage shift, AL’,.,,, is observed for the reverse configuration compared to the forward configuration in stage II CHE stress. The following discussions of the two-stage SHEjCHE stress results refer to the reverse configuration shift which probes the degradation near the drain junction. The subthreshold slope shift, AS, plotted in Figs 9 and 10 at two surface potentials, Vs, support the conclusion that negligible interface trap generation occurs in stage I during low field SHE injection. AS is nearly zero in stage I indicating that interface traps were not generated. Interface trap generation occurs in stage II CHE stress as evidenced by the rapidly increasing AS. The asymmetry of A Vc_,r is probably due to localized generation of interface traps near the drain junction during the stage 11 CHE stress instead of nonuniform oxide charge distribution since the oxide electron traps were filled in stage I. However. local detrapping of oxide electron traps[32] and hole trapping during CHE may also contribute to the asymmetry. A small detrapping of electrons from the shallow oxide traps (giving Ak’o < 0) is observed when the group A transistor is switched from stage I SHE injection to stage II CHE stress. Electrons trapped at the shallow traps can either tunnel out or be thermally emitted into the SiO, conduction band[32]. However, the gate voltage shift due to detrapping is less than 1% of A VCi_oTand is not significant relative to the net gate voltage shift. The large increase in AS seen in Figs 9 and 10 indicates that interface trap generation dominates during stage II CHE stress. Negligible electron trapping occurs in group A n-MOST during stage II because the majority of the oxide traps have already been filled during stage I. The injection probability of hot electrons over the Si/SiOZ barrier near the drain is likely reduced by the repulsive Coulombic interacting between the trapped electrons and the injected channel hot electrons. Generation of new oxide traps is small during stage II CHE stress since maximum oxide electric field. VGs/.~cx the (2.5 V/17 nm = 1.5 MVjcm). is small. Near the drain where the electron has the maximum kinetic energy, the oxide electric field opposes the injection of electrons into the gate oxide. Comparing the group B control transistor subjected to CHE stress with the group A SHE/CHE stressed transistor. two observations are made: (1) The gate voltage shift of the group B control transistor during CHE stress, AVG_cHEr is larger than the group A n-MOST stage II CHE gate voltage shift, AVG.11.. (2) AFV,.,,, is observed to asymptotically converge to the total group A gate voltage shift, A V, = A V,.,, + A I’,.,, at long stress duration. (I) At’,.,,, > Al’,.,, is attributed to the presence of both oxide trap charging and interface trap generation during the control CHE stress. This gives a

larger AV,,,, for the control n-MOST because the bulk oxide traps were not previously charged compared with the stage II CHE stress which is due to only interface trap generation because the oxide traps were pre-filled in stage I. (2) The gate voltage shifts of the group A and group B transistors asymptotically converge at long stress time (Z 1500 min.). This is expected since the oxide traps in both the pre-injected (group A) and the control (group B) transistors are filled at long time. Using a different measurement of AIn and AFT during CHE stress, Choi et al. suggested also that oxide trap charging may saturate before interface trap generation[22]. We conclude that, at long stress time, the gate voltage shift is due to interface trap generation in both group A and group B (control) transistors. Therefore, n-MOST degradation during saturation CHE stress is dominated by interface generation at long times after the oxide traps are filled. Possible models for interface trap generation include hole recombination and electron impact. Hot holes that are injected into the SiOZ beyond the field reversal or depletion point, ~1> y (V,. = V, - VCT), near the drain can be captured by the oxide hole traps located near the SiO#i interface. Thermal recombination of the sideway injected electron (CHE) with this trapped hole can impart sufficient energy to the Si/SiO, interface and break the weak or strained interfacial bond[l7,18]. Sah has emphasized that a lattice relaxation or atomic reconfiguration around the broken bonds after the bond breaking process is necessary to leave a dangling bond[l]. Otherwise, atomic reconstruction or thermal annealing will heal the broken bonds. Impact of the channel hot electron near the drain of a n-MOST which breaks the weak or strained interfacial bonds by “tangential impact” may also generate interface traps[ 15,16].

4. CONCLUSION

A sequential two-stage SHEjCHE stress technique is introduced to determine the effect of uniform charging of oxide traps on the Ins- Vcs characteristics of an n-MOST during CHE stress. By employing SHE injection to fill existing oxide traps at low field without generating interface traps. it is shown that the contribution of oxide trap charging and interface trap generation to the CHE induced n-MOST degradation may be separated. Using SHEjCHE stress, it is shown that (1) oxide trap charging and interface trap generation contribute to the threshold voltage shift and subthreshold distortion at short time and (2) after the existing oxide traps are filled, interface trap generation dominates at long time. This technique may be extended to hole trapping and interface trap generation and provides a method to sequentially separate the generation and charging rates of oxide and interface traps.

Oxide and interface Acknowledgemenrs-This work is supported by the Semiconductor Research Corporation under contract with Dr T. Nishida of the University of Florida (92~SJ-145). The authors thank their industrial mentors for support and Professor Chih-Tang Sah for suggestions.

REFERENCES

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