Session F3: Hardware development tools

Session F3: Hardware development tools

563 Session F3: HARDWARE DEVELOPMENT TOOLS Chairman: Klaus Waldschmidt Technische Informatik J.W. Goethe University Frankfurt am Main (F.R.Go) Rec...

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563

Session F3:

HARDWARE DEVELOPMENT TOOLS Chairman:

Klaus Waldschmidt Technische Informatik J.W. Goethe University Frankfurt am Main (F.R.Go)

Recent advances in semi-conductor technology have led to a s i g n i f i c a n t increase in the size .and complexity of systems. I t has become more important to increase r e l i a b i l i t y and shorten design time. H i s t o r i c a l l y , the design process was carried out completely manually. A f t e r completion of one s p e c i f i c level of the design, the s p e c i f i c a t i o n of the lower level could be started. F a i l u r e in one level of the design resulted in e i t h e r redesign of that level or r e l a x a t i o n of the imposed constraints by redesign of the higher l e v e l . CAD systems today include so-called s i l i c o n compilers which transform s t r u c t u r a l descriptions of systems to geometric layout f o r f a b r i cation. A d d i t i o n a l l y , simulation and v e r i f i c a t i o n functions are provided to evaluate the generated design's performance. In consequence, one main problem in the present CAD scenario is the i n t e g r a t i o n of various e x i s t i n g CAD tools i n t o a design environment. By automating the design process, the design time i t s e l f can be shortened.Therefore, the development of design automation systems becomes necessary, rather than s p e c i f i c CAD tools which perform only a single function. In consequence, rule based systems are i n t r o duced in the DA scenario, which replace the procedural algorithms of present CAD t o o l s with rule based expert systems between the design levels. The l a s t , but very important point is not discussed in t h i s session. The topic of t h i s session on "Hardware Development Tools" mainly deals with semi-custom development t o o l s , tool acceleration and tool i n t e g r a t i o n . In the f i r s t paper by Werner Haas et. al. the

"Characteristics and Requirements of Semi-Custom Design Tools" are discussed. A number of t o o l s have been examined on t h e i r a p p l i c a b i l i t y to the second generation of semicustom arrays. As a s t a t e - o f - t h e - a r t semi-custom array the IMS CMOS Gate Forest is presented. The Gate Forest can be c l a s s i f i e d to the second generation of semi-custom arrays. The complexity of these s t a t e - o f - t h e - a r t arrays are demonstrated by two ASIC designs. The second paper has the t i t l e "PMLS - A Parallel Multi-Level VLSI Simulator" and is written by Aposporidis et. al. The PMLS is a logic simulator and can be classified to the so-called Broadband simula-

tors. lhe simulation technique is the dist r i b u t e d discrete event simulation. The PMLS has the f o l l o w i n g main features: - Modelling and simulation at four abstraction levels - Acceleration of simulation through p a r a l l e l processing, which is performed by c i r c u i t partitioning. I n t e r a c t i v e and incrementa| simulation and high f l e x i b i l i t y and m a i n t a i n a b i l i t y of the simulator. The paper describes the object oriented architecture of PMLS in d e t a i l . In the t h i r d paper "An Integrated DeYelol~nt System for theM( 68 705 Single Chip C ~ u t e r " is presented by Per Nylen. The primary aim of t h i s development system was to supply an easy-to-use-system that made i t possible to develop a single chip computer a p p l i c a t i o n with a minimum of investment and training. This system uses the normal development process ( e d i t , assemble, simulate and e d i t again cycle) with some a d d i t i o n a l features. The software is t o t a l l y integrated into one program and a window presentation technique is used f o r the simulator. The fourth paper, by W.A. Halang and G.-U. Spohr, discusses "Languages and Tools for the

Graphical graBBing (PLC)".

and Textual System Independent Proof Programmable Logic Controllers

The basis is the IEC d r a f t on CAD tool standardi z a t i o n f o r planning purposes, which defines two low-level and two h i g h - l e v e l PLC programming languages and provides an environment f o r t h e i r utilization. The paper o u t l i n e s the present status of the IEC standardization e f f o r t and describes a high level system independent software development tool f o r programmable logic c o n t r o l l e r s . A l l programs are w r i t t e n in the language PASCAL and run on IBM-PC AT's under MS-DOS. N a t u r a l l y , in a session on such a fast growing f i e l d as Hardware Development Tools is one, only few of the problems which deal with t h i s topic can be included. I t was the aim of t h i s session to discuss some aspects of tool development and tool i n t e g r a t i o n in d i f f e r e n t environments.