Setting daily production targets with novel approximation of target tracking operations for semiconductor manufacturing

Journal of Manufacturing Systems 49 (2018) 107–120

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Journal of Manufacturing Systems journal homepage: www.elsevier.com/locate/jmansys

Setting daily production targets with novel approximation of target tracking operations for semiconductor manufacturing

T

Yu-Ting Kaoa, , Shi-Chung Changa,b ⁎

a b

Institute of Industrial Engineering, National Taiwan University, Taipei, Taiwan, ROC Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, ROC

ARTICLE INFO

ABSTRACT

Keywords: Daily target setting Re-entrant line Target-induced variability Bernoulli trial approximation Hybrid tandem queue

Daily production target setting based on machine capacities and available wafer-in-process (WIP) is an important practice in a semiconductor fab characterized by re-entrant process steps sharing individual machine group capacities. Operations of individual machine groups will track their respective target guidance through detailed machine allocation and lot dispatching (MALD), inducing variations of wafer flow. Existing approaches do not explicitly address such target-induced variations (TIV), and the resultant target setting may incur throughput loss and prolonged cycle times. A novel design of target-setting algorithm considering TIV called TaTIV is proposed to take TIV into account for setting daily targets systematically. TaTIV integrates three innovations: i) a Bernoulli trial model for approximating TIV of MALD at a process step under a given target, ii) a hybrid and recursive tandem queue approximation of multiple-step target-induced wafer flows and flow times given initial WIPs and machine group capacities of the day, and iii) a fixed-point iteration between target setting and targetinduced wafer flow estimation. Analyses and simulations exploiting fab data show that TaTIV sets targets closer to what are actually achieved at individual steps than those set without considering TIV, reduces inter-step variations of machine allocation, and improves fab throughput and cycle times.

1. Introduction In a semiconductor fab, each type of silicon wafers requires a serial flow of process steps, which may involve hundreds of steps as well as delicate and expensive machines. The process flow of a wafer is highly re-entrant because the flow requires multiple visits to each machine group as layers of circuitry are successively added onto the wafer. This re-entrant feature is different from both traditional flow shops and job shops, posing a unique challenge to production operation management [1]. Wafers of different products as well as similar products at different layers of fabrication compete for the finite capacity of a machine group [2]. Dynamic and uncertain factors (e.g., batching requirements, waiting time constraints, machine capability, reticle availability, machine qualification, and availability) and production priorities further complicate fab operation management [3]. Increasing fab production efficiency through scheduling and control have been common fab practices that decompose and coordinate operation management in multiple continuous improvements, which are critical to achieving high return on investment [4–10]. In particular, hierarchical production planning, scheduling, and control decompose and coordinate operation management in multiple time scales and decision levels to manage the

⁎

extremely complex processes and operations in a fab for efficiency and productivity [11–13]. Fig. 1 depicts the three-level hierarchy adopted by many fabs to manage the complexity of semiconductor fabrication operations: i) master production schedule (MPS), ii) daily target setting (DTS), and iii) detailed machine allocation and wafer lot dispatching (MALD). In the top level, the MPS aims to control the WIP level and cycle time of the entire fab while satisfying delivery requirements of customer orders. Frequently, MPS considers fab in an aggregated and coarse granularity capacity model with simplified production flow dynamics. MPS schedules the quantities of wafer release and output for a fab using day or week as a time unit over a few months to one year. In the bottom level, the detailed machine allocation determines the allocation of available machine capacity in each machine group to various production steps that require the same machine group once every few hours and based on fab production states. Real-time dispatching executes priority rules and dispatches individual wafer lots to the appropriate and available machines for processing. Lot dispatching is local to individual machines and steps and responds to operation status in real time. In the middle level, DTS provides a critical linkage between MPS

Corresponding author. E-mail address: [email protected] (Y.-T. Kao).

https://doi.org/10.1016/j.jmsy.2018.09.003 Received 14 June 2018; Received in revised form 12 August 2018; Accepted 12 September 2018 0278-6125/ © 2018 Published by Elsevier Ltd on behalf of The Society of Manufacturing Engineers.

Y.-T. Kao, S.-C. Chang

Journal of Manufacturing Systems 49 (2018) 107–120

problem between wafer-flow and proportional-to-workload target setting. Field applications demonstrated that quality DTS leads to more than 20% increase in daily moves and more than 8% decrease in the wafers-in-process (WIPs) of a foundry fab case. Despite the successful results, all the aforementioned target-setting schemes are mean value-based approaches. In specific, the estimated wafer flows and targets generated by TSS may significantly differ from those actually accomplished in one day as evidenced by a memory fab case depicted in Fig. 2. The horizontal axis shows the step index, while the vertical axis shows the achievable flow quantity percentage. The differences between the estimated flows (blue line) and the actually achieved flows (red line) are obvious, even up to 40%. The production targets are higher than the actual flows at certain steps, especially before step 121. It is because TSS assumes constant machine allocation over time, that is, various production steps sharing the same machine group have the same wafer flow times. However, the machines are allocated to different steps dynamically within time by shop floor supervisors to track the targets, which generates the variations of wafer flows to each step and unreachable targets. The role of variations in a fab has gained increasing attention from researchers in recent years for better control and fab management [17]. Wu identified the importance of manufacturing variability in [18] due to the combined effects of machine allocation, lot dispatching, rework, scraps, setup, preventative maintenance, and machine breakdown. High variability leads to accumulated WIP while low predictability results in on-time delivery [19]. The analysis of Kingman [20] indicates that the WIP of a single server queue is proportional to the variation coefficients of the arrival and service processes. Increase in service and inter-arrival variability to individual steps lead to an increase in waiting times, thereby increasing cycle times among the process steps. Many studies have demonstrated that the incorporation of variations into production flow helps to reduce the operation variations and to improve fab performance. The authors of [19] proposed a last-station-pace strategy to reduce inter-departure variability and performed simulation validation. The study of [21] reported that a fab accomplished 50% cycle time decrease and 35% throughput increase by lowering its operation variability through proper scheduling. Kacar et al. [22] showed that in a fab with high variability, production planning with cycle time models that consider processing variability, such as engineering holds and yield excursions, performs better than models without. Hassoun and Rabinowitz also showed that high utilization variability of machine capacity is critical to predicting WIP bubbles with accuracy [23]. Such studies have indicated the potential that including variations into DTS may help provide reasonable approximations of wafer flows and then improves fab performance. In a fab, one major objective of MALD is to track daily production targets set by DTS; however, poor targets misguide MALD and induce unnecessary variations [24]. In this paper, we investigate how daily targets should be set to achieve desirable fab performance by considering the chicken-and-egg relation that target setting induces

Fig. 1. Functional hierarchy for fab operation management.

and MALD by planners and shop floor supervisors respectively. DTS determines the targeted number of wafers to be processed for each product type at each process step and the estimated machine capacity allocation to the step daily. In practice, DTS is one of the key review items in the daily production meeting of a fab. Comparing the target number of wafers processed at each product step in a day and the actually achieved ones (called moves) helps a fab manager grasp and control the progress of production [14]. Effective target setting has made significant impacts on fab performance and facilitated quick response, on time delivery and high throughputs [15]. DTS is the focal problem in this paper. There have been various studies of the DTS problem. The author of [16] provided a detailed problem description. Govind et al. [5] adopted a linear programming-based optimization engine to convert fab requirements into targets for individual machine groups. Such integration of target, near real-time scheduling and dispatching has resulted in significant improvements in output and cycle time in the lithography area. In [16], a daily target-setting system (TSS) is proposed to approximate, under given targets, WIPs flowing into individual steps in a day and then a fixed point iteration to solve the chicken-and-egg

Fig. 2. Comparison of estimated flows from TSS and actual flows.

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Journal of Manufacturing Systems 49 (2018) 107–120

Fig. 3. Shared capacity of machine group A to steps 1 and 3. Fig. 4. Dynamic machine allocation over time.

variations through target-tracking MALD and affects wafer flows, WIP availability, and, in turn, the target setting. We develop approximation models to characterize the first-order effects by MALD on mean performance and target-induced variation (TIV) of each machine group and production flows of the fab. These models neglect operational details of MALD, such as various batching requirements, waiting time constraints, machine capability, reticle allocation, unrelated parallel machines, and machine qualification. We propose a novel approximation approach called TaTIV to take TIV into account for setting daily targets systematically. TaTIV integrates three innovations: i) a Bernoulli model for approximating TIV of MALD at a process step under a given target, ii) a hybrid and recursive tandem queue approximation of multiple-step target-induced wafer flows and flow times given initial WIPs of the day, and iii) a fixed-point iteration between target setting and target-induced wafer flow estimation. Exploiting fab data-based analysis and simulation, we show that TaTIV sets targets closer to what are actually achieved at individual steps than those set without considering TIV, reduces inter-step variations of machine allocation, and improves fab throughput and cycle times. The remainder of this paper is organized as follows. Section II explains the challenges and presents an overview of the target setting approach. Section III develops the modeling of equivalent service time induced by TTMA. Section IV approximates the penetration times starting from two steps to multiple steps. Section V proposes the TaTIV algorithm that incorporates TIV into production target setting. Section VI discusses simulation studies conducted over a mini-fab case and a memory fab case. Section VII concludes this paper.

is that the allocated number of machines remains constant. However, the practical allocation is in the unit of integers and varies within a day as depicted in the green blocks. The variations cause both arrival and service time variability, making SOPEA estimation far from both actual cycle times and the corresponding flow-ins. Specific challenges are as follows: C1. As target setting induces variations through MALD operations and production flows, how can the TIV of MALD be captured at individual steps for the given targets? C2. Under the given targets and TIV-captured model of MALD operations at individual steps, how can the inter-step wafer flows in a day be estimated? C3. How can the effects of TIV in solving chicken-and-egg problems between wafer flow and target setting be analyzed? Fig. 5 depicts the schematic diagram of TaTIV, the target-setting algorithm considering TIV. The three innovations of TaTIV are as follows: i) An approximation by repetitive Bernoulli machine allocation models a target-tracking machine allocation (TTMA) decision with a probability proportional to the step target. It captures TIV at a step for the given targets and approximates equivalent service time induced by the TTMA of each step. ii) A two-step tandem queue analysis (APT-2) and recursion for multiple steps approximate how, under the given targets and the corresponding TIV, initial WIPs at one step may flow through downstream steps in a day. It adopts the notion of penetration time as mean time required for the last lot in the initial WIP of a step to finish processing at a downstream step as a function of equivalent

2. Problem descriptions: daily target setting and induced variations In tracking daily production targets of individual steps, a supervisor first reviews the wafer-in-process (WIP) distributions, machine availability, and workloads of remaining targets through his/her decision support system. Such reviews are performed at a decision point of machine allocation, for example, every half-hour or when a need emerges. The supervisor then allocates the available machines in the machine group to process certain steps for a period. The higher the workload of a step, the higher the priority of the step. Once allocated to a step, a machine processes wafer lots of the step according to the dispatching rules of the machine. Such target-tracking machine allocations induces variations. Fig. 3 illustrates an example. Machine group A can process multiple steps (steps 1 and 3), requiring fab managers to dynamically allocate different number of machines of the same group to steps 1 and 3 in the production. Although steps 1 and 3 are given the same targets, the number of allocated machines varies within hours according to different managers, tool groups, and available number of wafers, resulting variations of wafer throughput rate, WIP levels, and wafer cycle time. Existing DTS approaches do not explicitly address such variations of wafer flows due to target-tracking MALD. Chang [16] designed Stage of Penetration Estimation Algorithm (SOPEA) in TSS to approximate the available wafers in a day under given production targets. SOPEA assumes that machines can be allocated in fractions. Once machines are allocated to individual steps, production flows of different steps are independent from each other, and the throughput rate is constant during one day for each step. As shown in Fig. 4, the premise of SOPEA

Fig. 5. Target setting algorithm considering TIV (TaTIV). 109

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Journal of Manufacturing Systems 49 (2018) 107–120

Table 1 Notations. Indices i j m Sets Sm Sm＼{(i, j)}

Index of product types, where i = 1, 2, …, I; Index of steps, where j = 1, 2, …, J; Index of aggregated machines, where m = 1, 2, …, M; Set of all product-type and step pairs that require machine m for processing; i.e., Sm≡ {(i, j) | step-j of product type-i requires processing by machine m}; Set of all product-type and step pairs that are different from but require the same machine group m as product-step (i, j);

Parameters Cm pi,j Wi,j Fi,j τi,j πi,j σi,j ζi,j Ti,j

ciA ,j

Estimated capacity of machine m in the unit of machine-time per day; Probability of allocating the machine capacity to product type-i step-j production; Amount of product type-i wafer lots at step-j in the beginning of the scheduling day (e.g. 7:00 am at each day); Amount of product type-i wafer lots flow into step-j in the scheduling day; Mean processing time of one product type-i wafer lot on step-j; τi,j = E[Ui,j]; Mean time of processing one wafer lot of product-steps that are different from but require the same machine group as product-step (i, j); πi,j = E[Xi,j]; Standard deviation of processing time of one product type-i wafer lot on step-j; σi,j = Var[Ui,j]; Standard deviation of processing time of product-steps other than (i, j); ζi,j = Var[Xi,j]; Daily target of product type-i step-j in terms of wafer lots; Squared coefficient of variation (SCV) of Ai,j;

Variables Ai,j Ui,j Xi,j ni,j Ri,j PTi,j,j’ PTj,j’

Bernoulli random variable of allocating the machine to product type-i step-j; Processing time of one product type-i wafer lot on step-j; Time of processing one wafer lot of product-steps that are different from but require the same machine group as product-step (i, j); Number of allocation decisions for product-step (i, j) to obtain a machine allocated again; Inter-departure time between two initial WIP lots of product-step (i, j); Mean time required for the last lot in the initial WIP of product step (i, j) to finish processing at product step (i, j’); Mean time required for the last lot in the initial WIP of step j to finish processing at product step j’;

service times. iii) A target-setting algorithm is designed with the iteration between capacity allocation to steps competing for the same machine group and TIV-included WIP flow estimation.

Therefore, E [Ai, j ] = pi, j , Var [Ai, j ] = pi, j (1 pi, j ) and the squared coefficient of variation (SCV) of Ai,j,

(ci,Aj )2 =

3. Bernoulli trial-based model of target-tracking machine allocation (TTMA)

pi, j (i, j)

Sm

=

i, j

Cm

.

pi, j

(3)

Note that although the Bernoulli trial is a simplified model of machine allocation operations, it does capture the TTMA key feature of proportion-to-target allocation. The (cijA )2 in Eq. (3) reflects how target tracking by TTMA induces variation at the product-step (i, j).

To capture both the mean and variations of service times of individual steps incurred by dynamic target-tracking machine allocation and dispatching under given targets,we make two assumptions without much loss of generality for the following analyses, and Table 1 summarizes the notations. A1) All WIPs are in the unit of lot, each consisting of n, say 25, wafers. A2) Machines in a machine group are homogeneous and are aggregated into one equivalent machine with the same total capacity. A machine hereafter refers to an aggregated equivalent machine. Fig. 6 depicts a Bernoulli trial model proposed to characterize target-tracking machine allocation (TTMA) by supervisors. When a machine m finishes processing, a probability pi,j exists for allocating machine m to the product-type and step pair (i, j). The probability 1－ pi,j means the machine capacity is allocated to other product-step pairs competing for machine group m, denoted as product-steps (i, j)’, in the set Sm\{(i, j)}. Specifically, the probability pi,j is defined by step target Ti,j multiplied by the mean processing time τi,j and then divided by the total capacity Cm of the day and is expressed as follows:

Ti, j

1 pi, j

3.1. Mean value of TTMA-included equivalent service time The following analyses exploit the Bernoulli trial model and approximate the mean and variance of the equivalent service time of a product-step (i, j) under TTMA. 3.1.1. Number of decisions needed to allocation to a step (i, j) Consider a product-step (i, j) with a given initial WIP level of Wi,j wafer lots. Let random variable Ui,j be the processing time of productstep (i, j) and random variable Xi,j be the time of processing productsteps that are different from but require the same machine group as product-step (i, j). The random variables Ui,j and Xi,j are mutually independent:

E [Ui, j] =

i, j ,

Var [Ui, j] =

2 i, j

Var [Xi, j ] =

2 i, j

and

E [Xi, j ] =

i, j ,

(1)

pi,j is proportional to the target and the corresponding target workload, Ti, j i, j , under given machine capacity, and pi,j ≤ 1 because the target workload cannot be higher than the machine capacity. Denote Ai,j as the Bernoulli random variable of allocating a needed machine to product-step (i, j) given as follows:

Pr(Ai, j ) =

pi, j , 1

pi, j ,

ifAi, j = 1 ifAi, j = 0.

(2)

Fig. 6. Bernoulli trial-based model of machine allocation to track targets. 110

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The first term to the right of the equality in Eq. (7) represents the variance from the uncertain processing time and can be derived as

Table 2 Parameters of the machine group (MG1) for validation. (Product, step)

(A,J1)

(A,J2)

(B,J3)

(C,J4)

(D,J5)

τi,j pi,j

20.21 0.12

34.36 0.12

20.21 0.54

20.21 0.17

40.69 0.04

E [Var [Ri, j |ni, j]] =

E [ni, j] =

pi, j

= (cijA) 2.

+ (ci,Aj )2

2 i, j

+ (ci,Aj ) 4

2 i, j ’

(8)

The second term corresponds to the induced variance due to TTMA. The independence among random variables of Eq. (5) for Ri, j | n makes derivation of the second term easy and

The number of allocation decisions, ni,j, for product-step (i, j) between two times of machine allocation for processing is a geometric random variable with parameter pi,j, and

1 pi, j

2 i, j

Var [E [Rij |nij]] = (cijA )2

2 i, j

(9)

Interested readers may refer to Appendix A for detailed derivations of Eqs. (8) and (9). Re-write the sum of both terms and get

(4)

Var [Rij] =

2 ij

+ (cijA) 2 {

2 i, j

+

2 i, j [1

+ (cijA) 2]}

(10)

Eq. (4) w shows that the SCV of the machine allocation for product step (i, j) affects the average number of allocation decisions between two times of allocating the machine to (i, j).

where the former term is the variance of raw processing time of step (i, j) while the latter is the variance induced by TTMA among the steps that require the same machine group.

3.1.2. Equivalent service time of initial WIP lots Define the equivalent service time of initial WIP lots at step (i, j) as Ri,j ≡ inter-departure time between two initial WIP lots of productstep (i, j). Given ni,j = n, Ri,j|n then equals one-lot processing time at product step (i, j) plus sum of the previous n－1 lot processing times for productsteps (i, j)’. Thus,

3.3. Simulation validation of equivalent service time models

Ri, j | n =

Xi1, j + Xi2, j +

+ Xin, j

1

This subsection uses simulations over a single machine group (MG1) scenario derived from a real fab to compare the mean and variance of the equivalent service times obtained from i) mean value method [12], V RiM , j and Ri, j , ii) Bernoulli tria -based TTMA model ones, E [Ri, j] and Var [Rij], and iii) those obtained from simulated allocation of individual machines.

+ Ui, j, if n > 1;

Ui, j, ifn = 1.

Example 1. Validation of equivalent service time

(5)

MG1 is one of the bottlenecks. MG1 is required to process five steps, including three common steps for products A, B, and C, and two other steps of relatively long processing times for A and D. Each step has the same targets as the wafer releases of four products, 250, 1100, 350, and 75 respectively. Table 2 lists Example 1 parameters. The service times obtained from simulating the allocation of individual machines are the ground truth for validation. Dispatching the allocated capacity of MG1 to wafer lots of product step is the first-comefirst-serve (FCFS) rule. The simulation of equivalent service time collects the inter-departure time between two initial WIP lots of product step (i,j). TTMA-included equivalent service time models are clearly superior approximations to the mean method for all the steps, as shown in Table 3. For example, product step (D, J5) that has the longest processing time among the five steps but a small target. The mean-value method (RijM ) leads to a maximum of 98.83% error in estimating the mean equivalent service time of product step (D, J5). The Bernoulli trial-based TTMA model in Eq. (6) significantly lowers the maximum error, also at (D, J5), to 19.11%. The variances of TTMA-included equivalent service times are also much closer to those of simulation while the mean-value only method assumes zero variance. As E[Ri,j] provides a more realistic approximation than RijM , it can be observed E [Ri,j] has smaller inter-step error variation, that is., the difference between E[Ri,j] and simulation, than RijM . Realistic service time approximation helps forecast how initial WIP at one step may flow to its downstream step for machine capacity allocation and to avoid unnecessary waiting times.

The mean equivalent service time of a product-step (i, j) lot is as follows:

E [Ri, j] = E [E [Ri, j | n]] =

i, j

+

i, j

(cijA )2 .

(6)

Note that for a low volume product, i.e., small pi,j, (ci,Aj )2 is large and the mean service time E [Ri, j] is long. It is consistent with field observations regarding low volume products in a fab. 3.2. Variance of TTMA-included equivalent service time Derivation of the variance, Var [Ri, j], adopts the law of total variance and is expressed as follows: (7)

Var [Ri, j] = E [Var [Ri, j |ni, j]] + Var [E [Ri, j |ni, j]]

Table 3 Comparisons of equivalent service time estimations among mean-value only method, TTMA models, and simulation. (a) Mean (i, j)

(A,J1)

(A,J2)

(B,J3)

(C,J4)

(D,J5)

RiM ,j

163.74

278.35

37.21

116.954

1098.75

225.20

214.24

44.49

158.39

E [Ri, j]

658.24

Simulation

201.24 −18.63%

185.73 49.87%

41.31 −9.9%

138.48 −15.54%

552.69 98.83%

Err (E [Ri, j])

11.91%

15.35%

7.7%

14.38%

19.11%

Err (RiM ,j )

4. Proposed approach: approximation of penetration times with TTMA-included equivalent service time

(b) Variance (Product, step)

(A,J1)

(A,J2)

(B,J3)

(C,J4)

(D,J5)

RiV, j

0

0

0

0

0

47949.33

36911.55

1290.42

23080.88

396030.86

Var [Ri, j]

Simulation

30245.11 −100%

24112.18 −100%

1030.27 −100%

12885.39 −100%

219340.40 −100%

Err (Var [Ri, j])

58.50%

53.08%

25.25%

79.12%

80.56%

Err (RiV, j ) *

On top of the Bernoulli trial model-based approximation of the TTMA-included service times, this section develops innovative approximations about how the TTMA effect on the service times of individual steps can affect the flow times of wafer lot between two steps under the given initial WIPs. Define the penetration time from step j to step j’, j’ ≥ j, as PTi,j,j’ ≡ mean time required for the last lot in the initial WIP of

Err(Ψ) = (Ψ – Simulation) / Simulation. 111

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Y.-T. Kao, S.-C. Chang

Rj are of general distributions. We now design approximation models for efficient computation of PTj－1,j. 4.1. Penetration times as functions of equivalent service times Each processing step is modeled as a I-WIP/GT/1 queue, where IWIP is the given initial WIP, and GT is TTMA-included equivalent service time with general distribution. The service time of a lot from the WIP of step j, Rj, is i.i.d. among individual lots and has mean and variance as described by Eqs. (6) and (7). The single step penetration time at step j, PTj,j,

Fig. 7. Illustration of two-step penetration time PTj－1,j.

product step (i, j) to finish processing at product step (i, j’). PTi,j,j’ is a function of the TTMA-included service times of the individual steps Ri,j, …, Ri,j’, j’ ≥ j. The following approximation analysis derives how TTMA affects the penetration time starting from the singleand two-step penetration times, PTi,j,j and PTi,j－1,j. These approximations serve as building blocks in Section V to approximate the multiplestep penetration times and then estimate the wafer flow-ins to the individual steps for target setting in a fab. Derivations in this Section are for each product type and thus the remainder of this Section omits the product-type index i for notational simplicity. The analysis starts from the two-step penetration time, PTj－1,j, as depicted in Fig. 7. Consider a process flow from step j－1 to step j, where initial WIPs are Wj－1, and Wj respectivey The processing times are τj－1, and τj by two independent machines. Note that the service time of step j－1, Rj－1, is also the inter-arrival time for step j, which results in a two-step tandem queue. Example 2 gives an illustration of the said scenario.

E[

PTj

1, j

=E i=1

E [Rj].

4.2. Exponential distribution approximations of general service times Approximating the processing time of a step as an exponentially distributed random variable is a reasonable and common practice in the literature [28,29]. In I-WIP+M/M/1 approximation of the I-WIP + GT/ GT/1 queue of step j, we assume exponentially distributed service times. Let Rje be the exponetial distribution approximation of Rj with

E [Rje] = E [Rj] =

+

2 j cj

and Var [Rje] = E [Rje ]2 = [ j +

Err (pj ,

j

,

j,

j,

j)

2

j

= Wj

1

E [Rj 1] + E [

2 2 j cj ]

(13)

Var [Rje]:

= Var [Rje] Var [Rj ] =

j

Rlj l=1

j

There is an approximation error in

j | Wj 1, Wj

+

Key to compute the two-step penetration time, PTj-1,j, is the term j | Wj 1, Wj ] in Eq. (11)).

i) exponential distribution to approximate service times, i.e., an I-WIP +M/M/1 approximation of the I-WIP + GT/GT/1 queue, for computation efficiency with an error analysis on variance; ii) Markov chain analysis to derive the distribution of j | Wj 1, Wj given any Wj-1 and Wj and E [ j | Wj 1, Wj]. Details are in the following two subsections.

In Fig. 7, where W1=W2 = 1, and τ1 =τ2. Penetration time PT12 equals the sum of the service time of the one lot at step 1, and its waiting time and service time at step 2. TTMA directly affects service times at both steps (Eq. (6)). Since the waiting time depends on whether the initial WIP lot at step 2 is still in the queue or in service when the initial WIP lot of step 1 arrives at step 2, TTMA indirectly affects the waiting time through the two service times. One may easily find that PTj－1,j is an addition of two parts: (i) total time required to process the initial WIP of step j－1, and (ii) the time required to process the remaining lots when the last lot of the initial WIP of step j－1 arrives at the input buffer of step j. The number of remaining lots at step j is affected by the interaction of the inter-arrival variability caused by the TTMA of step j－1 and the service variability from the TTMA of step j. Define number of lots in the queue of step j given r initial lots when j | n, r the n-th lot of the initial WIP from step j－1 arrives, including the n-th arriving lot and the in-processing lots by step j. Denote Rjk 1 as the TTMA-included service time of k-th lots of step j －1 and Rlj as l-th lots of step j. In view of the two parts constituting PTj－1,j and the definition of j | n, r , mathematically,

Rjk 1

(12)

4.1.1. I-WIP + GT/GT/1 queue model of approximating two-step penetration time(APT-2) An innovative design of I-WIP + GT/GT/1 queue models the tandem production flow from step j－1 to the output of step j, where the hybrid arrival model I-WIP + GT consists of deterministic initial WIP of step j and the stochastic arrivals from step j－1 to step j with GT distribution. Key challenges in the I-WIP + GT/GT/1 queue analysis for computing PTj－1,j lie in estimating the probability distribution of j | Wj 1, Wj from Rj1 and Rj, as well as in the efficiency of subsequent calculation of E [ j | Wj 1, Wj]. The main ideas of our innovative and computation-efficient approximation approach of APT-2 consist of two parts:

Example 2. TTMA impacts on the two-step penetration time (single initial lot per step)

Wj 1

A 2 j (c j ) ]

PTj, j = Wj E [Rj] = Wj [ j +

2 j (1

c j2) + c j2

2 j

1 c2

(14)

j

where the SCVs are as in Eq. (10) with i and A omitted, and = j2/ 2j and c 2 = j2/ j2 are SCVs of the processing time of step j and non-step j’

c j2

j | Wj 1, Wj ]

j

respectively. Eq. (14) shows that the sign of the Err depends on the value of processing time statistics, j , j , j , and j .

(11)

In Eq. (11)), the first term is the single-step penetration time, PTj－1,j－1, and the second term is the expectation of random sum of random variable Rj. Inter-arrival and service variabilities induced by the production targets and initial WIPs jointly affect the expected number of lots in queue. Note that once machine capacities are allocated to individual production flows, the production flows of different product types are essentially independent of one another. Decomposition approach is commonly adopted in the previous studies [25–27]. The challenges of computing PTj－1,j are that initial WIP levels Wj－1 and Wj and tool capacities vary daily in a fab and the service times Rj－1 and

4.3. Two-step tandem queue analysis under given initial WIP Now we analyze the I-WIP + M/M/1queue of step j to derive the probability of j | Wj 1, Wj , i.e., Pr ( j | Wj 1, Wj = k ) ≡ probability of having k lots in queue or in service at step j when the last lot of initial WIP of step j－1 completes the processing at step j－1 and enters the queue of step j, k = 1,… Wj－1+Wj. The deterministic initial WIP of step j－1, Wj－1, serves as a finite 112

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Table 5 Parameters of Example 3. 3(a) service variability of step J3impact on 2-step penetration time

Step J3－1 Step J3

Fig. 8. Given Θj|n-1,r = θ, the state transition diagram for I-WIP + M/M/1queue with finite arrivals.

Pr(

,k

j | n, r

=k

j | n 1, r

= ), 1

Step J3－1 Step J3

Pr(Rje

1

< Rje ) =

E [Rje ] E [Rje 1]

+ E [Rje ]

,

,

m

=

j (1

j)

(16)

m

(17)

The probability Pr ( j | Wj 1, Wj = k ) can then be written into a recursion between nth and (n－1)th arrivals from step j－1:

for n = 2, …, Wj

1

withPr(

j |1, Wj

= m) = p

,

(18)

m

The machine allocation variability affects j | Wj 1, Wj through j and then goes into the approximation of E [ j | Wj 1, Wj] and PT(j 1) j (Eq. (11))).

where

M j | Wj 1, Wj

= max 1, Wj

1

+ Wj

(19) RjM 1 Wj 1 R M j

26.30 28.87

10 1

pj (0.2 ∼ 0.9) 0.5

tj 20.62 20.21

pj 26.30 28.87

Initial WIP Wj 10 1

In view of the improved fidelity of the two-step penetration times, {PT(j−1)j, j = 2,…,J}, obtained by APT-2 at individual steps, this Section will first integrate{PT(j−1)j, j = 2,…,J} into the recursive algorithm SOPEA of [16] for approximating multistep penetration times and wafer flows. Such novel but simple integration approximates how effects of TTMA at individual steps may “propagate” among multiple steps and subsequently affect penetration times and wafer flows. With the estimate numbers of wafer lots that would flow into each product-step in a day based on initial WIP distributions and

APT-2 approximates two-step penetration time PTj 1, j longer than the mean value approximation, PTjM 1, j , obtained by Stages of Penetration Estimation Algorithm (SOPEA) in [16]. Denote the mean value approximation of two-step as SOPEA-2 in the following description. SOPEA-2 computes PTjM 1, j as the sum of mean times of last initial WIP lots at step j－1 to go through steps j－1 and j: M M j | Wj 1, Wj Rj

20.62 20.21

5. Setting targets with induced variability

4.4. Superior fidelity of APT-2 approximation

PTjM 1, j = Wj 1 RjM 1 +

0.5 (0.2 ∼ 0.9)

In this example, a simulation study illustrates the differences between PTj 1, j by APT-2 and PTjM 1, j by SOPEA-2 under different levels of variabilities. There are two machine groups, MG1 and MG2, where MG1 processes the five steps listed in Table 2 and MG2 processes five immediate upstream steps to those of MG1, i.e., steps J1－1, …, J5－1, with processing times listed in Table 4. The MALD rule is the same as stated in Section 2. In Example 3, the TTMA probability of step J3 ranges from 0.2 to 0.9, which determines the service variability of step J3, whereas the probability of step J3－1 is considered a fixed variable. There are 30 replications in each simulation run. Table 5 shows the details of the example parameters. Fig. 9 plots the results, and the detailed values are shown in Table 6. The approximation penetration times obtained by APT-2 fall between the simulated 95% confident intervals and fit well. With the small variability, APT-2 performs similarly to SOPEA-2. With the increase of variability, APT-2 approximates closer to the simulation results than that by SOPEA, especially when the service variability is below 3. Even when variability is up to 4 and APT-2 over-estimates the penetration time, APT-2 still outperforms SOPEA-2 in approximation errors. The results support Property 1.

and (1-αj) is then the probability that the queue of step j decreases by 1.The transition probability p , m corresponds to the event probability of m departures from step j and then one arrival from step j－1 for m = 0, 1,…, Wj:

p

Initial WIP Wj

Example 3. Evaluation and comparison by simulation.

Under the assumption of exponential distributions, let αj denote the event probability that Rje 1 < Rje as j

pj

M Given an initial WIP of step j, Wj, E [ j | n, Wj] j | n, Wj for the n-th arrival to step j from step j－1, which can be done by mathematical induction over n. Please refer to Appendix C for details.

(15)

n Wj 1.

tj

3(b) service variability of step J3－1impact on 2-step penetration time

arrival source with exponential inter-arrival time to step j. The calculation of Pr ( j | Wj 1, Wj = k ) requires transient instead of steady-state analysis. We adopt Morisaku's transient analysis [30] with a variation that arrivals to the queue are finite and up to Wj-1 instead of infinite in Morisaku’s. Fig. 8 shows the state transition diagram, in which the next arrival epoch from step j－1 to queue of step j is solely focused. A state represents the number of lots in the queue of step j between (n－1)th and nth arrivals, which ranges from 1 to +1 given j | n 1, r = . The one arrival transition probabilities are

p

pj

.

Please refer to Appendix B for details. Property 1. PTj

1, j

PTjM 1, j .

Sketch of proof: Key ideas are that E [Rj 1] RjM 1 and E [Rj] RjM because of TTMA at each step according to Kingman’s inequality [20]. Table 4 Parameters of the machine group (MG2). Step

J1－1

J2－1

J3－1

J4－1

J5－1

τj

20.62

22.74

20.62

20.62

41.24

Fig. 9. Service variability of step J3 impact on 2-step penetration time. 113

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Finding 1: SOPEA/APT-2 captures first order effects of TTMA on penetration times Fig. 11 shows that the penetration time approximations obtained by SOPEA/APT-2, PTjk , are much higher than those by the mean valueM based SOPEA, PTjk , indicating that SOPEA/APT-2 captures the first order effects of TTMA on penetration times. However, unlike the good approximation of APT-2 for two-step penetration times, the penetration time approximations by SOPEA/APT-2 are much lower than the confidence interval of the simulation. This is the price of using APT-2 and recursion instead of a detailed capture of how TIVs affect among multiple steps. k j. Finding 2: PTj, k > PTjM, k , This essentially is a result of property 1 and the property of SOPEA/ APT-2 that if PTj, k 1 > PTjM, k 1 and PTj + 1, k > PTjM+ 1, k , then PTj, k > PTjM, k . Finding 3: Relative approximation errors do not increase with the number of process steps After three steps, the relative differences between the simulated and SOPEA/APT-2 approximated penetration times stay almost the same with increase in number of process steps. It indicates that the TTMA impact on penetration times may be mainly within 3 steps.

Table 6 Comparison of 2-step penetration time by APT-2, SOPEA-2, and simulation. StepJ3 prob.

c J3

APT-2

SOPEA-2

simulation average

(L, U)*

0.2

4.00

1517.10

1111.60

1402.97

0.3 0.4 0.5 0.6 0.7 0.8 0.9

2.33 1.50 1.00 0.67 0.43 0.25 0.11

1011.84 779.86 658.99 591.91 552.93 529.25 514.18

741.03 555.78 452.82 446.08 441.27 437.66 434.86

982.72 773.74 648.22 565.36 546.30 533.87 532.33

(1295.07, 1510.87) (899.89, 1065.55) (711.40, 836.09) (602.80, 693.63) (518.69, 612.02) (489.37, 578.37) (499.46, 593.14) (489.37, 578.37)

(L, U)* = (Lower bound, upper bound) of 95% confident interval of simulated penetration time.

approximate penetration times, the target setting is then updated and then penetration times and wafer flows are re-estimated given the new targets. Such a procedure follows a fixed-point iteration framework, as illustrated in Fig. 5. Target setting based on flow approximations with TTMA is expected to be closer to actual operations and induce lower operation variability as compared with those achieved by the mean value-based targets of [16].

5.2. Flow-in estimation of individual step Penetration times of initial WIPs provide a foundation of estimating how many wafer lots may flow into a process step in a day. Define the expected number of wafer lots that may flowing into step k in Y amount of time (e.g., 24 h) as

5.1. Multistep penetration time approximation (SOPEA/APT-2) Fig. 10 shows the integrated SOPEA/APT-2 recursion that adopts a deterministic queue approximation model and analysis to compute a multiple step penetration time of three or more steps, say PTjk from PTj,k−1 and PT j+1,k, with{PT j−1,j, j = 2,…,J} as given inputs. The integrated algorithm of SOPEA and APT-2 for multistep penetration time approximation is named SOPEA/APT-2 and is is summarized as follows. SOPEA/APT-2 recursion algorithm

k 1

Ws, j *

Fk

arg min {j | PTj (k

1)

Y },

(20)

s=j*

where j* is the earliest step at which all its initial WIPs can finish step k －1 during Y period. Since the penetration times {PTj,k−1} can be obtained by either SOPEA and SOPEA/APT-2, so is Fk. Let FkV and FkM be the flow-in estimations of step j obtained by SOPEA/APT-2 and the mean value-based SOPEA respectively. Based on the definition in (20) and Finding 2, we may easily deduce that Property 2. FkV

FkM .

The equality may hold when j* is the same by the two flow-in estimation. This property implies that SOPEA yields a higher estimated WIP availability at each step during a day than SOPEA/APT-2.

Example 4. approximation

Evaluation

of

multiple-step

penetration

5.3. Iterative target setting

time

Target setting requires input information of available capacities of individual machine groups and information of individual steps such as initial WIP, estimated wafer lot flow-in and raw processing times. Target of part type i at step j is calculated according to

This example is an enrichment of Example 3 to a multiple-step process to demonstrate the simple integration of SOPEA/APT-2 and evaluate its approximation with increased steps. Starting from 2-step penetration time performance described in Example 3, more steps are gradually added after step J3 to make the flow from 3-step to 5-step. For simplicity but without loss of the purpose, the allocating probability and the processing time of each step, i.e., pj and τj, are set to 0.5 and 50. The initial WIP of step 1 is 10 and 1 for the remaining steps. Comparisons of multiple-step penetration time approximations obtained by SOPEA/APT-2 and SOPEA are as follows.

Ti, j = min Wi, j + Fi, j , (i, j) Sm

Cm (Wi, j + Fi, j )

ij

(Wi, j + Fi, j ) ,

(i , j )

Sm (21)

The capacity Cm of machine m in a unit of machine-time is allocated among product-steps (i, j) Sm according to the workload of available WIPs, (Wi,j+Fi,j)τi,j. When the total workload requiring a machine group does not exceed its available capacity, the available WIPs at (i,j) are set as the target Ti,j. Otherwise, capacity of the machine group is proportionally allocated according to the workloads among product-steps competing for the machine group. Note that Ti,j ×τi,j ≤ Cm. Fig. 12 depicts the TTMA-included target setting algorithm (TaTIV). The algorithm consists of three major functions: (i) capacity allocation and target setting (CATS), (ii) TTMA-included wafer flow estimation (WFE), and (iii) a fixed-point iteration loop between functions (i) and (ii). The CATS takes inputs of the daily wafer release and output schedule, capacity estimation of machine group, initial WIP

Fig. 10. Multiple-step penetration time estimation by SOPEA/APT-2. 114

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Fig. 11. Comparison of multiple-step penetration time by SOPEA/APT-2, SOPEA, and simulation.

Fig. 12. Target setting algorithm considering TIV (TaTIV).

distribution, and wafer flow estimation. The release and output schedule is derived from the MPS based on the estimation of mid-term machine capacity and production demand. CATS then allocates the capacity of each tool group to the processing of product steps that require the tool group to meet the output schedule while facilitating the total moves and balancing the production line. The TTMA-included WFE estimates the number of wafers that can flow into a processing step in one day from upstream steps considering the target-induced variability. The fixed-point iteration then loops between the two functions until the convergence check is fulfilled. There hypotheses regarding TaTIV are as follows:

H2. Reduction of differences between targets set by TaTIV and what actually achieved Such an expected reduction comes from improved wafer flow estimation by taking TIV into consideration. It is motivated by the simulation study and analysis in sub-sections IV.A and B. H3. TaTIV leads to cycle time and throughput improvements. Research of [31] shows that repeated application of the fixed-point iteration and proportional allocation scheme may bring a re-entrant line to balanced flows and WIP distributions. As TaTIV targets improve in closeness to what can actually be achieved in a day, we intuitively conjecture that TaTIV targets induce less inter-step variations of machine allocation to steps competing for the capacity of one machine group.

H1. TaTIV convergence to a unique target setting for a given set of initial WIP distribution and machine capacity. TaTIV adopts the “iterative proportional-to-workload capacity allocation scheme” [16]. Hwang et al. proved the existence of unique target setting by using such a scheme under a given set of WIP distribution and machine capacity in a simplified re-entrant line model [31]. Although TaTIV includes more detailed models than those of [31], we conjecture that TaTIV should maintain the convergence property of allocating finite capacities.

6. Fab performance improvement by TaTIV Monte Carlo simulation study is conducted in this Section. The goal is to evaluate performance and analyze properties of TaTIV over realistic fab data sets. There are two models, a small fab (Fab-S) and a large fab (Fab-L), constructed for the simulation study. 115

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Table 8 Summary of Fab-S and Fab-L.

Fig. 13. A five-machine six-step Fab-S case [15].

Fab-L

Fab-S

Fab dimension

# of product types # of steps # of machine groups

4 150–200 101

1 6 3

Characteristics

Batching Machine failure Varied production sequence between products Difference step processing time of each product

v v v

v x x

v

x

6.1. Simulation system volumes competing in the same MG in the fab, a Fab-L simulation model is developed to capture the existing flow. Data are derived from one of the leading memory fabs in Taiwan. Details of the fab parameters are listed in [34]. Four product types (denoted as product-type A, B, C, and D) and 101 MGs are employed. The number of operational steps for each product is between 157 and 200. Table 8 provides the summary of both Fab-S and Fab-L. The monthly output of the fab is over 2000 wafer lots. The wafer lot released at the start of each day are 7, 46, 18, and 5 for all four products, respectively, in accordance with the seasonal throughputs presented in the company marketing report. The availability and mean-time-to-repair (MTTR) of MGs are determined based on the parameters established by a previous study [35]. One-year simulation starting with an empty lot is performed for the warm-up period and to generate the initial condition, after which the daily throughputs where simulated every month to correspond to one sample. Overall, 30 samples were simulated. Product-type B, which is the main product in the fabrication, occupied 62% of the daily release; whereas product-types B, C, and D were for smaller volumes. Fab-L simulation implementation is first validated by comparing various metrics from the simulation model with those from the actual fab. One of the key metrics is the total throughput per day. According to the fab data, the daily throughput is approximately 70.67 wafer lots. In the Fab-L simulation model, the average throughput is 70.84 wafer lots with 95% confidence interval of (70.27, 71.40), which certainly captures the actual fab figure. By comparing the cycle time performance, the historical average is 60 days, whereas the average of the model is 52.07 days. This result can be attributed to lack of detailed characteristics in the simulation model, such as transportation, and the processes that aim to guarantee wafer quality, such as metrology and rework, thereby leading to a shorter simulation cycle time than that of the actual value. All of the data obtained in the model validation are the results of 30 replications of the model. Each replication runs for a warm-up period of 700 days, followed by a run length of 300 days. The simulation model is reasonable based on throughput performance and the cycle time trend.

Target setting algorithms TSS and TaTIV are separately implemented in Matlab and interfaced to a discrete event simulation tool Plant Simulation™[32]. At the beginning of each simulated day, either TaTIV or TSS sets the targets of each product-step to guide the machine allocation and dispatch the fab simulation. An Bernoulli trial allocation module calculates probabilities pi,j based on the generated targets and allocates machines of individual machine groups to processing product steps with probabilities pi,j. The first-come first-serve (FCFS) rule is implemented for dispatching wafer lots of a product-step to the allocated machine. The targets of day 1 are set to be equivalent to the release for all the product steps. Beginning from day 2, the movement of each product-step and the WIP distribution at the end of day t from the simulation were recorded as inputs for TaTIV and TSS respectively to calculate the targets for day t+1. Each simulation case runs 30 replications and collects mean and variance of performance indices such as cycle times and throughput. 6.2. Fab-S model The Fab-S model depicted in Fig. 13 has three machine groups (MG) and a six-step single product. Fab-S is exemplary and exhibits all of the essential features for fab scheduling [15,33]. Table 7 lists the process, tool group, and WIP parameters. Bj is the batch size of step j and MTm is the maximum throughput (capacity) for each MG shift m. For MG 1, a full-batch policy was required, such that each lot waited in the buffer until the number of waiting lots exceeds B1. Among all calculations, R3 is the smallest; thus, MG 3 is the capacity bottleneck (CA-BN). Furthermore, although R1 is slightly high, the batching protocol still required that the lot waited in buffer until a full batch is formed, thereby resulting in large arrival variability for the downstream steps. MG 1 is therefore the cycle time bottleneck (CT-BN) [18]. MG 2 is a non-bottleneck (non-BN). The implementation of Fab-S model in the simulation is validated by comparing the simulated throughput with that in [33]. The simulated time horizon is 25,000 min with less than 2.4% relative error. The simulation implementation of the Fab-S model is regarded consistent with that of [33]. Refer to [36] for additional details.

6.4. Convergence property of TaTIV

6.3. Fab-L model

First, it is observed that TaTIV converges to a unique solution at each time of execution as Hypothesis 1. In the Fab-S model, TaTIV is executed at the beginning of each simulated day until 30 days. With the 30 replications, there are in total 900 executions all of them converge to a unique result. In the scale of Fab-L model, the convergence property also holds during the simulation period.

To further compare the impacts of TIV on the different product Table 7 Specification of Fab-S case. m

J

τj

Bj

Cm

MTm

1

1 5 2 4 3 6

225 255 30 50 55 10

3 3 1 1 1 1

2

6.95

2

9.97

1

6.38

2 3

6.5. Closeness of targets to actual moves The targets generated by TaTIV are expected to have small closeness compared to TSS based on Hypothesis 2. An index to represent closeness was utilized to quantify the daily differences between planned targets and actual moves, which can be defined as 116

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Table 10 Fab-S performance of TaTIV and TSS schemes.

TATIV TSS Relative Error* *

Fig. 14. Comparison of the closeness between targets and actual moves.

CLj =

1 30 30

30

j = 1, …, J

where Tj(t,r) and Mj(t,r) are the target and simulated moves of step j in day t of r-th replication, respectively. As hypothesized in H2, TaTIV can lead to small CLj compared to TSS. Under the same wafer release policy and WIP level, targets with small values for closeness correspond to reasonable MPS and customer delivery, which are desirable. Thus, hypothesis H3 also holds, because TaTIV leads to shorter cycle time for these two models. Simulation results support the hypotheses. Simulation results show that targets set by TSS deviated from actual moves more than those obtained from TaTIV. Hence, a replication is conducted for demonstration. In Fig. 14, the horizontal axis is the simulated day, whereas the vertical axis shows the differences between targets and the simulated actual moves of step 5 in a given replication r, i.e., T5 (t , r ) M5 (t , r ) . The negative value of day t means the daily targets are lower than the simulated moves of that day, and vice versa. The targets generated by TSS, the blue line, has higher fluctuation than those generated by TaTIV, the red line. This observation indicates that TSS provides a larger closeness gap as compared with TaTIV. A comparison of closeness is shown in Table 9. Accordingly, the targets generated from TaTIV are closer to actual moves by 24.1% and 30.7% at step 3 of CA-BN and step 5 of CT-BN, respectively. In effect, the TaTIV targets are closer to the actual compared with those of TSS. High deviations occurred on steps 5 and 6, which refer to the downstream steps of CT and CA bottlenecks, respectively. Such high deviations imply that impacts of inappropriate target setting of bottlenecks on downstream steps are amplified because of the re-entrant process flow.

Station 1 (CT-BN) Station 2 (Non-BN)

61,100.4 [54208.0, 67,992.8] 72,272.7 [64726.0, 79,819.3] −15.4%

S3 S6 S1 S5 S2 S4

TATIV

TSS

Mean Step Cycle Time [90%C.I.] 187.3 [185.1, 189.4] 127.3 [125.6, 129.0] 650.1 [642.2, 658.1] 418.8 [413.8,423.8] 54.0 [53.1, 55.0] 58.1 [57.5, 58.7]

Mean Step Cycle Time [90%C.I.] 183.7 [180.8, 186.7] 130.2 [127.5, 132.5] 662.5 [650.2, 674.8] 425.0 [422.1, 427.9] 54.8 [54.0, 55.7] 57.8 [57.4, 58.2]

7. Conclusions In this paper, an innovative design of target setting algorithm (TaTIV) was proposed which systematically considers the variability of

Table 9 Closeness of TSS and TaTIV to the actual in Fab-S.

a

1495.6 [1486.2, 1505.1] 1513.8 [1504.7, 1522.9] −1.2%

This phenomenon is consistent with Hypothesis 3, that is, TaTIV induces less inter-step variations of machine allocation to steps that compete for the capacity of one machine group (i.e., more balanced moves within each day than the targets generated by TSS). The short cycle times on the steps of CT-BN by TaTIV result in long cycle time on the third step of CA-BN. One reason could be that the higher throughput level by TaTIV under the same production horizon leads to the increased utilization of CA-BN, which prolonged waiting times before processing. In summary, TaTIV achieves 1.1% higher throughput, 1.2% reduction in mean cycle time, and 15.4% decrease in cycle time variance compared with TSS. The inclusion of TIV into target setting results in reasonable step targets. Evaluation results of the throughput performance of Fab-L are shown in Table 12, presenting that in total 2.07% increase of throughput is achieved. Inferred from previous sections, the high allocation probability of product-type B steps results in small service time variation; thus, the targets generated from TaTIV and TSS are similar. In addition, the service time variation of product-type D steps is the highest due to the smallest allocation variation among product-types. No WIPs are observed in some product-steps of small-volume products, especially product-type D, resulting in the minor improvements. In the simulation, the steps of product-type C show significant differences; service time modeling sufficiently determines the WIPs of a productstep.

Cycle time and throughput performance are also improved as Hypothesis 3 has hypothesized. In Fab-S, the 90% confidence level of the cycle time performance of TaTIV is lower than that of TSS for mean value and variance (i.e., See Table 10). Table 11 analyzes the improvements among steps. Cycle time reduction by TaTIV mainly comes from the steps of long processing times (CT-BN), whereas the cycle times of non-BN steps are almost the same. The fifth step of CT-BN also improved its closeness by 30.7% after adopting the targets set by TaTIV.

TaTIV (lots/day) TSS (lots/day) Relative Differencea

348.5 [347.1, 350.0] 344.8 [343.4, 346.4] 1.1%

Relative error = (mean TATIV - mean TSS)/mean TSS.

Station 3 (CA-BN)

6.6. Cycle time and throughput improvements

MG 1 (CT-BN)

Cycle Time Variance [90% C.I]

(22)

r =1 t=1

MG 3 (CA-BN)

Mean Cycle Time (minutes) [90% C.I]

Table 11 Step cycle time performance (minutes).

30

[Tj (t , r ) Mj (t , r )],

Throughput (lots) [90% C.I]

Table 12 Average daily throughput and its 90% confident interval (lots) of Fab-L.

MG 2 (Non-BN)

S3 0.89 0.92

S6 3.43 4.52

S1 0.11 0.12

S5 1.24 1.79

S2 0.16 0.18

S4 1.37 1.21

3.3%

24.1%

8.3%

30.7%

11.1%

13.2%

Relarive difference = (TaTIV − TSS)/TSS.

Product

TATIV

TSS

Rel. Error*

A B C D Total

5.46 [4.83, 6.09] 44.10 [42.73, 45.47] 18.03 [17.62, 18.45] 3.42 [3.36, 3.47] 70.97 [70.01, 71.92]

5.21 [4.59, 5.82] 44.08 [42.87, 45.29] 16.82 [16.43, 17.21] 3.38 [3.31, 3.43] 69.53 [68.76, 70.29]

−4.8% 0.03% 7.23% 1.22% 2.07%

* Rel. error = (mean TaTIV - mean TSS)/mean TSS. 117

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Y.-T. Kao, S.-C. Chang

machine allocation induced by tracking targets over for cycle time improvement. Three novel designs were introduced. First, an approximation by repetitive Bernoulli machine allocation was developed to capture TIV at a step for the given targets. Second, a tandem queue analysis and the recursive procedure was proposed to approximate how initial WIPs at one step may flow through downstream steps in a day under the given targets and the corresponding TIV. Third, a fixed-point target setting iteration between machine capacity allocation and TIVincluded WIP flow estimation was adopted for the chicken-and-egg problem between target setting and TIV. Analyses showed that TaTIV targets induce less inter-step variations of machine allocation to steps competing for the capacity of one machine group, i.e., inducing more right allocations at the right time in a fab re-entrant line. Over the Fab-S case, it also demonstrated that TaTIV is close to actual moves by 30.7% of bottleneck machine groups as compared to a mean-value based scheme. TaTIV also led to reductions of 1.2% in mean cycle time and 15.4% in cycle time variance at 1.1% throughput increase. It is because

the higher throughput level by TaTIV under the same production horizon leads to the increase of utilization on capacity bottleneck, which thus prolongs the waiting times before processing. In the Fab-L case derived from one of the leading memory fabs in Taiwan, TaTIV increased the throughput by 2.07% compared to TSS. This paper has laid a foundation for future research on how TaTIV may further improve fab performance by considering the factors of a detailed MALD model, such as setup effect, batching requirements, waiting time constraints, machine capability, reticle allocation, unrelated parallel machines, and machine qualification. Acknowledgements This work was supported in part by the Ministry of Science and Technology, Taiwan, ROC, under grants MOST 103-2221-E-002-220MY2, NSC 102- 2221-E-002 -206, NSC 102-2219-E-002 -012, NSC 992219-E-002-004, and NSC 98-2221-E-002-138-MY3.

Appendix A Eq. (8) with product-step index (i, j) omitted

E [Var [RB]] = E [E [RB ]2 ] E [E [RB]]2 =

2

+

21

p p2

[(2 p)

2

+ (2 p)

2

+ 2 p]

+

1 p

2

=

2

+

1 p p2

2

+

(1 p)2 p2

2

Eq. (9) with product-step index (i, j) omitted

Var [E [RB]] = E [E [RB]2 ] E [E [RB]]2 = E [RB = 0]2 Pr[B = 0] + E [RB > 0]2 Pr[B > 0] E [R]2 2

=p

=

2

=

2

+ (1 p)

+

1 p

2

+

2

1 p p

(1 p) (1 p) 2 p2 1 p p

Appendix B Proof of Eq. (29) SOPEA is designed on the basis of the relative workloads per machine assigned between the two steps. Two cases are presented for the calculation of PT(M j 1) j . CASE 1 occurs if Wj 1 RjM 1 > (Wj 1 + Wj 1) RjM , which represents when the last wafer lot of step j－1 finishes processing, all the wafers before the last lot, i.e., Wj－1+Wj－1, finish their processing at step j. This last wafer lot does not have to wait when it arrives at step j. The time that all the Wj of wafer lots need to finish both steps j and j－1 is therefore M M PT(M j 1) j = Wj 1 Rj 1 + Rj

By contrast, in CASE 2, when the last wafer lot of step j－1 finishes processing, it has to wait. The workload of a wafer lot is assumed equally divided among assigned machines. Therefore, the number of remaining wafer lots when the last lot arrives the buffer of step j is determined by the total wafer of both steps minus the number of lots that already finished step j, i.e., Wj M PT(M j 1) j = Wj 1 Rj 1 + Wj

In CASE 2, Wj

1

+ Wj

1

+ Wj

Wj

Wj 1 RjM 1 RjM

1

RjM 1

RjM

RjM

is always larger than 1.

In summary of the two cases, the penetration time of two-step is therefore

118

1

+ Wj

Wj 1 RjM 1 RjM

. Therefore, the penetration time of two-step is

Journal of Manufacturing Systems 49 (2018) 107–120

Y.-T. Kao, S.-C. Chang

M PT(M j 1) j = Wj 1 Rj 1 + max 1, Wj

Wj

+ Wj

1

1

RjM 1

RjM

RjM

Appendix C Proof (mathematical induction) Step 0. E [

j + 1| Wj ]

is always greater than or equal to 1 no matter Wj, that is,

1 + Wj 1

E[

j + 1| Wj ]

1 + Wj 1

=

i PWj +1 (1, i)

PWj +1 (1, i) = 1.

i=1

i=1

Step 1. It is true for Wj = 1. 1 + Wj 1

E[

j + 1| Wj ]

=

i PWj +1 (1, i) i=1 Wj + 1

W j + 1) j 1

=(1

+

W j + 1 ) j 1+(Wj + 1

i (1

j +1

+ 1)

j+1

i=2

(1

= Wj + 1 + 1

j +1 )

+

(1

j + 1)

j+1

(1

> Wj + 1 + 1

Wj + 1+ 1

j+1

j+1 )

.

j+1

Step 2. Assume Wj=X－1 is true, that is, W j + 1+ X 1

E[

j + 1| X 1]

=

i PWj + 1 (X

1, i) > X

1 + Wj + 1

i=1

(X

1)

(1

j+1 )

.

j+1

Step 3.For Wj=X,

E[

j + 1| X ]

= E [E [

j + 1| X | j + 1| X 1]]

Wj + X

=

E[

j + 1| X | j + 1| X 1

= i] Pr (

j + 1| X 1

= i)

i=1 2

= PWj + 1 (X 1,1) i=1

i PWj+ 1+ X

1 (X

1, i ) + 1

(1

Wj + 1 + X 1 (X 1)

(1

i PWj +1+ X

1 (1,

i)

i=1

j+1 ) j+1

i=1

(1

i P2+…+ PWj +1 (X 1, Wj + 1 + X 1) i=1

Wj + 1+ X 1

= Wj + 1 + X X

Wj + 1+ X

3

i P1 (1, i ) + PWj + 1 (X 1,2)

j+1 ) j +1

+1

(1

j+1 ) j+1

j +1 ) j+1

Q.E.D

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