Shallow implants into GaAs

388

Nuclear Instruments and Methods in Physics Research B19/20 (1987) 388-391 North-Holland, Amsterdam

S H A L L O W I M P L A N T S I N T O GaAs Volker G R A F and Willi H E U B E R G E R IBM Zurich Research Laboratory, Siiumerstrasse 4, 8803 R~chlikon, Switzerland

Scaling of lateral device dimensions into the submicron range also requires the reduction of the vertical dimensions. Shallow ion implantation is necessary for channel formation of submicron MESFET's. Partial-ion-channeling tails were found for energies below 60 keV, and resulted in a significantly broader profile than predicted by LSS theory. Diffusion effects are investigated by comparing SIMS profiles from as-implanted, rapid thermal and furnace-annealed samples. Comparison of the CV and SIMS profiles gives information on the annealing behavior, and allows the definition of a differential activation efficiency. Our investigations showed that for vertical scaling, a simple reduction of implant energy is not enough. We found several procedures which yield shallower profiles.

I. Introduction High-speed GaAs integrated circuits have recently received more commercial attention owing to process technology improvements which showed the feasibility of L S I / V L S I GaAs circuits [1]. Among all the GaAs devices, the MESFET is the simplest to manufacture. Direct ion implantation into semi-insulating GaAs substrates for active channel formation is widely used and believed to be the key process to develop a high-yield high-speed GaAs IC technology. The main advantages of ion implantation over epitaxial growth are improved uniformity and reproducibility, ability to perform selective area implants, self-aligned registration techniques and low cost per wafer for high-volume applications. Most important for high circuit yield is good control of the threshold voltage of the MESFET devices. Although the parameter control (dose, energy) in ion implantation is excellent, it is very difficult to achieve the low threshold spread required for high performance E / D MESFET memory circuits. The quality of the GaAs substrate material has proven to be the major limiting factor. Background doping, redistributions of residual impurities and deep level defects during the high-temperature annealing step change the net doping in the MESFET channel and so the threshold voltage. Better electrical uniformity has been achieved nowadays by using substrate preparation methods such as In-doped defect-free LEC GaAs substrates and whole ingot annealing. Recent improvements in high-speed GaAs integrated circuits are made by scaling the device dimensions into the submicron range. Early investigations [2] showed that MESFET device performance can be improved by reducing the gate length (L) and channel thickness (d) and correspondingly increasing the doping concentration, so that the ratio L / d is maintained much larger 0168-583X/87/$03.50 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)

than three. The lateral device scaling is done mainly by advanced lithography techniques such as electron or ion beam and optical UV lithography. Gate lengths down to 0.1 g m [3] or even below [4] have been fabricated. For the necessary reduction of the channel depth, we found that a simple reduction of implant tnergy is no~ enough. Partial-ion-channeling tails were found for energies below 60 keV, and resulted in a significantly broader profile than predicted by LSS theory. In addition, owing to the necessary high-temperature annealing process, diffusion effects and surface defects affect the electrical device parameter.

2. Shallow implantation In the past, most of the ion-implantation work in GaAs was done for deep implants [5,6], only recently has shallow ion implantation been used to improve GaAs MESFET device performance [7,8]. Analytic models of ion-implanted GaAs FETs [9,10] show that, for successful scaling of the gate length into the submicron range, it is also necessary to decrease the channel thickness, and to increase the doping concentration. We scaled our channel implant process to lower energies to be able to fabricate high-performance MESFET's with gate lengths in the range 0.1-0.5 gm. The implantations were done with a commercial DF-3000 Varian/Extrion implanter in the deceleration mode which allows reduction of the implant energies down to 5 keV. For comparison, four different (Si, SiF, Se and Te) n-type dopants were implanted at various energies into undoped semi-insulating (100) LEC GaAs wafers (see fig. 1). The doping profile was investigated by SIMS and CV profiling before and after annealing. So far, in all cases we have found that the implant profile was much broader than expected from theoretical LSS [11] or

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Monte Carlo [12] calculations. Even for wafer-tilt angles of 15 ° the profiles show an exponential partial-ionchanneling tail and cannot be fitted by a Gaussian di.stribution. After annealing, the profiles are broadened even more by about 2-30 nm owing to diffusion. Pre-amorphization by Ar implantation prior to the ntype implant mainly reduced the implant tail, and gave the most shallow profile. Implantations through a Si3N 4 capping layer also gave steeper profiles, but the projected range values were much larger than expected from theoretical calculations [11,12] probably owing to the smaller density of the PECVD Si3N 4 films. Several GaAs samples were implanted with Se. The activation efficiency was very high (approx. 95%) for deep Se implants, and decreased for shallow implants but was still higher (approximately double) than the amphoteric Si or SiF implants. The mobilities are comparable to those of Si and SiF implantations. Similar to Si and SiF implantation, channeling effects are also present for the Se implantations but owing to the larger mass, the penetration depth for Se ions is much smaller than for Si or SiF, and therefore a more shallow implant can be done with Se. From our experiments, we found that Se is best suited for shallow implants. In the case of Te, we obtained decent activation only for very high annealing temperatures.

3. A n n e a l i n g

High-temperature annealing of ion-implanted GaAs is very difficult because of the high partial pressure of

the arsenic compound which leads to a thermal decomposition of the GaAs surface. To prevent arsenic loss, we encapsulated our samples with a PECVD Si3N 4 film. Rapid thermal annealing (RTA) with a commercial halogen flash-lamp (AG Associates) annealing system was used to minimize dopant redistribution and compared to conventional furnace annealing. To investigate stress-induced redistributions, we capped our samples with different PECVD Si3N 4 films with compressive and tensile stress, and compared results to samples which we annealed capless by using a second GaAs wafer face-to-face. For optimizing the annealing process, several GaAs samples were implanted with SiF(47) and Si(29) at 85 keV and 25 keV and a dose of 4 × 1012 cm -2. Then the samples were capped with Si3N4 and annealed at different temperatures for 20 rain in the furnace (820-880°C) and for 8 and 30 s in the heatpulse system (850-1010°C). Optimum conditions are 950-975°C for 8 s in the RTA system and 850°C for 20 rain in the furnace. When comparing different GaAs substrates from different suppliers, RTA for 8 s gave significant differences in the optimal annealing temperature, whereas furnace annealing was not so sensitive on GaAs material variations. The furnace-annealed sampies in the temperature range investigated are typically 30-35 rim, and the RTA samples only 2-15 nm (8 s) respectively 6-20 nm (30 s) broadened owing to diffusion. A selection of our CV data is shown in fig. 2. The data can be fitted by a diffusion law with diffusion coefficients in the range 1 × 10 -13 to 5 × 10 -15 cm2/s. An Arrhenius plot gave high activation energies for R T A (20-40 kJ/mol) and low values for the furnace (9 kJ/mol) annealed samples. III. SEMICONDUCTORS

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Implant profiling was performed by CV and SIMS measurements. The CV measurements have the disadvantage that the surface region is inaccessible owing to the surface depletion width. As shown in fig. 3, the CV and the SIMS data agree well for low dose implants, whereas for higher doses the CV profiles differ drastically from the SIMS data owing to saturation in the electrical activation of the dopants. The SIMS profile of the high dose implant shows a shoulder at 2-3 x Rp. By SIMS measurements, we proved that this shoulder is found only in the annealed and not in as-implanted samples. We therefore believe that the increased radiation damage causes special diffusion effects. The CVmeasured doping profile of the high-dose implants shows a maximum of approximately 10 t8 cm -3 at depth values where we found the shoulder in the SIMS measurements. In the case of the lower dose, the CV measurements access only the tail of the implant profile but fit well the SIMS data. Comparison of the CV and SIMS profiles gives information on the annealing behavior, and allows the definition of a differential activation

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efficiency which is approximately 100% for the implant tail (in our case for doping densities below 1017 cm -3) and below 100% for doping densities above 1017 c m - 3. Fig. 4 shows a SIMS profile of a 51 keV Si(29) implant before and after furnace annealing. The diffusion broadening of approximately 20 nm already discussed is found. F o r comparison of implant profiling by SIMS and CV, we made many samples with shallow implants direct into GaAs and also into pre-amorphized (Ar) GaAs. The samples were conventionally furnace annealed (850 ° C, 20 rain) as well as RTA (heat pulse 950 ° C, 8 s). So far, we have found a reduced mobility for the Ar pre-amorphized samples. The doping profiles measured by CV gave similar results for RTA and pre-amorphized furnace-annealed samples, whereas the direct implanted furnace-annealed sample showed a less shallow profile. In fig. 5, the effect of a Ar surface pre-amorphization prior to the shallow Si(29) implant is shown. The profile of the double implant is much steeper than the conventional single implant.

5. Conclusion To summarize, we want to point out that thin M E S F E T channel formation by shallow implantation into GaAs is not trivial. A simple reduction of implant energy is not enough. Partial-ion-cbanneling tails dominate the shape of the implant profile. This long channeling tail can be cut off partly by a buried pimplant. Electrical activation is lower than in conventional deep implants. Implant annealing is therefore a very critical process. To avoid diffusion, RTA is necessary. The use of selenium as a dopant is an advantage, and also pre-amorphization of the surface. By combining those techniques, it is possible to fabricate ion-

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implanted channels for GaAs MESFET's with a channel thickness as low as 40 rim. We acknowledge the assistance of A. Moser with the CV measurements, J. Kempf for SIMS profiling, Th. M o h r for Si3N 4 capping, and Th. Forster for implant annealing, and thank A. Oosenbrug for his support.

References [1] Y. Ishii, M. Ino, M. Idda, M. Hirayama and M. Ohmori, in: Proc. IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC, October 1985 (IEEE, 1984) p. 121. [2] K.E. Drangeid and R. Sommerbalder, IBM J. Res. Develop. 14 (1970) 82. [3] H. Jaeckel, V. Graf, B.J. Van Zeghbroeck, P. Vettiger and P. Wolf, to be published in IEEE Electron Device Lett. [4] W. Patrick, W.S. Mackie, S.P. Beaumount, C.D.W. Wilkinson and C.H. Oxley, IEEE Electron Device Lett. EDL-6 (1985) 471. [5] T. Hara and T. Inada, Solid State Tech. 23 (1979) 69. [6] R.T. Blunt, in: Solid State Devices, 1985, eds., P. Balk and O.G. Folbert (Elsevier, Amsterdam, 1986) p. 133. [7] N. Kato, T. Takada, K. Yamasaki and M. Hirayama, Extended Abstracts, 17th Conf. Solid State Devices and Materials, Tokyo (1985) p. 417. [8] J. Kasahara, M. Arai and N. Watanabe, IEEE Trans. Electron Devices ED-33 (1986) 28. [9] T. Chen and M.S. Shur, IEEE Trans. Electron Devices ED-32 (1985) 18. [10] H. Daembkes, W. Brockerhoff, K. Heime and A. Cappy, IEEE Trans. Electron Devices ED-31 (1984) 1032. [11] J. Lindhard, M. Scharffand H.E. Schiott, K. Dan Vidensk. Selsk. Mat. Fys. Medd. 33 (1963) no. 4. [12] J.F. Ziegler, in: Ion Implantation Science and Technology, ed., J.F. Ziegler, (Academic Press, Orlando, 1984) p. 51.

III. SEMICONDUCTORS