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Shallow junction formation by plasma immersion ion implantation
XIlRFi E COATINGS
ELSEVIER
[[CliNOLO f Surface and Coatings Technology93 (1997) 254-257
Shallow junction formation by plasma immersion ion implantation J i q u n S h a o a,,, E r i n C. J o n e s b, N a t h a n W. C h e u n g b Eaton Corporation, Semiconductor Equipment Operations, BeveHy, MA 01915, USA b Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Abstract Shallow junctions formed by BF3 and PH 3 PIII were studied. Diodes with good electrical characteristics were obtained on wafers masked by either SiOz or SiO2 plus photoresist patterns. These structures are also compared with diodes fabricated with a conventional ion beam implanter. © 1997 Elsevier Science S.A.
Keywords: Shallow junction; Plasma immersion; Ion implantation
1. Introduction
Reduction of junction depth to minimize short channel effects is required when scaling-down device dimensions for ULSI circuits. A high quality shallow junction combines a very shallow junction depth Xj with reasonably low sheet resistance R, and acceptably low reversebiased leakage current IT. Very shallow dopant introduction can be achieved using low implant energy and heavy dopant. The post-implant annealing process is more critical for controlling the junction movement, the dopant activation and the crystal defects removal. The choice of annealing conditions may be subtle because minimal junction movement requires a low thermal budget, while high activation and good defect removal require a significant thermal budget. Furthermore, these three factors are also related to the damage profiles caused during the implantation. Implant damage leads to end-of-range (EOR) defects, which may increase the leakage current IL if located within the depletion layer; maplant damage also affects the junction depth Xj due to transient enhanced diffusion (TED). Therefore, the design of annealing processes must consider the implantation conditions, such as the dopant species and energies, total dose, dose rate, etc. [t-4]. Plasma immersion ion implantation (PIII) has been used to form ultra-shallow junctions [5-7]. The PIII apparatus is a relatively simple and inexpensive implant system, which may be easily adopted as a cluster toot in ULSI fabrication. The contamination level is control* Corresponding author. 0257-8972/97/$17.00 © 1997 Elsevier ScienceS.A. All rights reserved. PH S0257-8972 (97) 00055-8
lane and is much lower than was usually thought. The device charging during implantation is minor due to built-in electron neutralization by the plasma between pulses. This is important for the thinner gate oxides required as device dimensions scale-down. In addition, PIII is capable of very low energy implantation with very high dose rate, regardless of wafer size. For example, in Eaton's PIII facility an average dose rate 1 x 15 molecules/cm2/s, has been achieved for both boron and phosphorus at 5 kV implantation. The instantaneous dose rate is as high as 4x 1016/cm2/s. during the peak of the pulses. The dopants included BFa (~85%) and BF or B (~15%) in BF 3 PIII. 1.0E+23 1.0E+22 A
8 1.0E+21 E £ 1.0E+20 1.0E+I 9 1.0E+18 O
1.0E+17 1.0E+16 1.0E+15 0
200
400
600
800
Depth (Angstroms) Fig. 1. As-implanted profilesmeasured by SIMS. The total boron dose is 3.79 x 10~s/cm2, and phophorous dose is 3.86x 1015/cm2.
255
J. Shao et al. / Surface and Coatings Technology 93 (1997) 254-257 1.00E+20
I0 8
1.00E+19
10 7
.~...... ...... : .... ....-:- .... .... - .... • .....
• A
E
AB A
10 s
dp (p/Veto)
E
1.00E+17
A A A
0 0
0
o:: T
10 6
1.00E+18 O
:
1.00E+16
~e
~o
104 Forward
. . . . . ucs -EATON(EA1)
"~ 10 3 co
O
1.00E+15
..... ~....... ~....
1.00E+14 0
0.1
0.2
t...... 0.3
E
10 2
g
lo1
Reverse
t
0.4 1 0°
Depth (microns)
Fig. 2. Junction depths measured by SRP. (A) 5 kV BF3, I050°C/I0 s, ./~ =262 f~/sq. (B) 5 kV 5% PHJH2, 850°C/20 s, R~=219 £~/sq.
10"1 10-2
Therefore, the damage profile is expected to be different from conventional implantation. In this paper, the properties of p* and n + junctions made under these conditions are studied.
2. Experimental Four-inch device wafers were prepared at UC Berkeley, which were masked either by Side_ or SiO2
•
;.
~,
~.
~
,
Bias V o l t a g e (Volts)
Fig. 4. I - V characteristics of diodes made by BF3 PIII.
plus photoresist (PR) patterns. The junction structures have diodes of area from 625 to 4 x 106gm 2 with LOCOS isolation [5]. The ion implantation was performed at Eaton. The BF3 plasma was generated by a
Effect of two.step anneal on sheet resistance
70
[]
Error
6O 600
2.4E15/c~
lkV E o 50
AO/ One.slep o C
'~ 40 400
\
(4
i\
30 ~Y~h800,0,20s
O
¢.
i / pfe.anneal
(o
5d
~,, 20 .J
10
d0s~35×I0~5~.2 I
1000'0,10s
I
10~0'0,20s
0 Mask:sio2
I
1050'0 10s
Method:
A~al cycle
SiOa
BF3 Pill
Comparison
of
PR
SiO~
BFa Pill
leakage
Fig. 3. Effect of two-step anneal on sheet resistance. The wafers were
Fig. 5.
imp~amedb'y gFa PIIi.
area = 0.04 cm2, bias voltage= - 5 V.
current
PFI
BF2 GSD
density.
Diode
256
Z Shao et at. / Surface and Coatings Technology 93 (1997) 254-257
with Si0 2 mask 100
,
1D't
f
g" lO.~
S lo-~ I) 10"~ "0 '~ t04
during PH3 PIII. For comparison, wafers were also implanted at 5 keV by a conventional GSD ion beam implanter at Eaton. After implantation, the wafers were annealed under different conditions at UC Berkeley. The electrical characteristics of these diodes were then measured.
with Si02 + PR mask
, . , .,.
100. . . . . . . . . . 10"~I
10.2l
__EA7- 5kV BF3RII 35x101Scm~ --EAS- 5kV I3t=3 P111 2.4xt0~Scm2 EA3-5keVBF2*GS0
1031
I,,
3. Results and discussion
- -
lO'sl
....
35x10~Scm~
EA5 -5kV BF3P[li 35×10~Scm"2 EA12-5kV BF3Ptli 24x10~¢m"2 .... EA6-SkeVB:2+GSD 3,SxlOlscln2
- -
1041
1@[
10q
10"~ O
104
.........
104 lO.loV:, . . . .
1040
1
2
3
4
0
1
2
3
4
Bias Voltage (Volts) Fig. 6. Comparison of electrical characteristics for diodes made by BFa PIII and by BF2 implant in GSD. large area ICP source at a pressure of 0.8 mTorr. Carrier gases Ha or He were used for the PH3 plasma with mixing ratios from 2 to 10%. Boron was implanted at - 5 and - 1 kV with dose of 2.4 or 3.5 x 10 ~5/cm 2. A typical implant time is 2.5 to 3.5 s at 5 kV. The corresponding Si etch rates during BF3 PIII were measured as 13.6 nm/min at 5 kV and 8.6 nm/min at 1 kV at the pulse rate of 12.5 kHz. The etch rate was negligible
Fig. 1 shows the as-implanted profiles at 5 kV for boron and phosphorus, where 92% of the dopants are located within 20 nm of the surface. The deeper range of phosphorus may be attributed to mass and etch rate differences. After one-step annealing, the junction depths Xj and sheet resistance Rs for 5 kV BF3 and PH3 doped wafers are as shown in Fig. 2. A two-step anneal may give a lower Rs (Fig. 3) and shorter Xj than a one-step anneal if the pre-anneal conditions are chosen so that it will remove implant damage without causing dopant movement [ 1,2]. However, if the time for the second step is too long or the pre-anneal temperature too high, the junction depth will be much deeper and dopant out-diffusion may be high. An average reverse-biased leakage current density of 3.7 nA/cm z was found for the diodes masked by SiO2. Fig. 4 shows the I - V curves of these diodes compared with a PIII diode made by UC Berkeley in 1993 [5]. The diode forward ideality factor (n) is 1.02. The higher saturation current of the forward I - V characteristics reflects the lower resistivity of the Eaton p + junction. The bumps shown in the reverse current at 3 V may indicate a layer of damage a short distance above the
S h a l l o w p+/n j u n c t i o n s b y p l a s m a i m p / a n tat/on 120 t V B = I O 18 c m -3
1 O0
0
E ¢--
v¢ - -
80
,...
(30
J
Fq
O
2. S h e n g , J V S T B, "1~ . 4 3 . F~lch~ M C U S D P , d 9 ~ 4. Ishk:~= M C U S D P , ' t 9 ~
¢-..
=
~, Jon~s~ EDL~ d g g 3 ~i Q l ~ n , A P L , tg1~t
40
7. F e l o h , liT, "lgg4.
O 20
SIMS SRP HALL
I~1
8, Q l n , T E D , 1 9 9 2 g , Qln~ PSST~ t £ g 2 "10. J o n ~ s , P h . D . 1:he$is, t g ~ 1 1 . U C B ,"]EJ~TON, 1 ~ 42. M ~:uno, V L ~ I ~ ¥ r n p . , d@Q5
0
i
0
i
2
i
4
Wafer
bias
8
6
during
implant
(kV)
Fig. 7. Correlation of junction depth after annealing to substrate bias.
10
J. Shao et al. / Surface and Coatings Technology 93 (1997) 254-257
junction. A better anneal process may eliminate theses bumps. Comparisons of leakage current density and electrical characteristics for diodes made by BF 3 PIII and by a BF2 ion beam implanter GSD with SiO2 and PR masks are shown in Figs. 5 and 6. The data did not show a correlation between the leakage current levels and the type of mask or dose. The PIII diodes show approximately equal electrical performance to those made by GSD implantation.
257
implant energies as low as possible for shallow junction formation, however, a proper annealing cycle based on defects engineering is needed to ensure the quality of the junctions.
References [1] E.C. Jones, N.W. Cheung, J.Q. Shao and A.S. Denholm, XI International Conference on Ion Implantation Technology, Austin, Texas, June 12-15, 1996.
[2] K.H. Lee, Y.S. Sotm, J.G. Oh, D.H. Lee, B.J. Cho and J.C. Kim, Ion Implantation Conference, Seottsdale, Arizona, 21-24 April, ]996.
4. Summary PIII is a promising method for fabricating ultrashallow junctions in VLSI devices. The junction depth of PIII-formed diodes made by different groups are shown in Fig. 7. A correlation between junction depth and implantation voltage is apparent, even though the data come from three different junction profiling methods. The spread of the data is due mostly to variation in annealing cycles. The trend recommends the use of
[3] A. Sultan, M. Craig, K. Reddy, E. Ishida, L. Larson, P. Maillot and S. Banerjee, SRC Pub C9608I, February I996. [4] M. Craig, A. Sultan, K. Reddy, S. Banerjee et al., J. Vac. Sci. Technol. B 14 (1996) 255-259. [5] E.C. Jones, N.W. Cheung, IEEE Electron Dev. Lett. 14 (1993) 444-446. [6] B. Mizuno, M. Takase, I. Nakayama and M. Ogura, IEEESymposlum on VLSI Technology Digest of Technical Papers, 1996, pp. 66-67. [7] S.B. Felch, T. Sheng, E. Gamn, K.K. Chan, D.L. Chapek, R.J. Matyi and J.R. Conrad, Ion hnpl. Tech., 94, North-Holland, Amsterdam, 1995, pp. 981-984.
ELSEVIER
[[CliNOLO f Surface and Coatings Technology93 (1997) 254-257
Shallow junction formation by plasma immersion ion implantation J i q u n S h a o a,,, E r i n C. J o n e s b, N a t h a n W. C h e u n g b Eaton Corporation, Semiconductor Equipment Operations, BeveHy, MA 01915, USA b Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Abstract Shallow junctions formed by BF3 and PH 3 PIII were studied. Diodes with good electrical characteristics were obtained on wafers masked by either SiOz or SiO2 plus photoresist patterns. These structures are also compared with diodes fabricated with a conventional ion beam implanter. © 1997 Elsevier Science S.A.
Keywords: Shallow junction; Plasma immersion; Ion implantation
1. Introduction
Reduction of junction depth to minimize short channel effects is required when scaling-down device dimensions for ULSI circuits. A high quality shallow junction combines a very shallow junction depth Xj with reasonably low sheet resistance R, and acceptably low reversebiased leakage current IT. Very shallow dopant introduction can be achieved using low implant energy and heavy dopant. The post-implant annealing process is more critical for controlling the junction movement, the dopant activation and the crystal defects removal. The choice of annealing conditions may be subtle because minimal junction movement requires a low thermal budget, while high activation and good defect removal require a significant thermal budget. Furthermore, these three factors are also related to the damage profiles caused during the implantation. Implant damage leads to end-of-range (EOR) defects, which may increase the leakage current IL if located within the depletion layer; maplant damage also affects the junction depth Xj due to transient enhanced diffusion (TED). Therefore, the design of annealing processes must consider the implantation conditions, such as the dopant species and energies, total dose, dose rate, etc. [t-4]. Plasma immersion ion implantation (PIII) has been used to form ultra-shallow junctions [5-7]. The PIII apparatus is a relatively simple and inexpensive implant system, which may be easily adopted as a cluster toot in ULSI fabrication. The contamination level is control* Corresponding author. 0257-8972/97/$17.00 © 1997 Elsevier ScienceS.A. All rights reserved. PH S0257-8972 (97) 00055-8
lane and is much lower than was usually thought. The device charging during implantation is minor due to built-in electron neutralization by the plasma between pulses. This is important for the thinner gate oxides required as device dimensions scale-down. In addition, PIII is capable of very low energy implantation with very high dose rate, regardless of wafer size. For example, in Eaton's PIII facility an average dose rate 1 x 15 molecules/cm2/s, has been achieved for both boron and phosphorus at 5 kV implantation. The instantaneous dose rate is as high as 4x 1016/cm2/s. during the peak of the pulses. The dopants included BFa (~85%) and BF or B (~15%) in BF 3 PIII. 1.0E+23 1.0E+22 A
8 1.0E+21 E £ 1.0E+20 1.0E+I 9 1.0E+18 O
1.0E+17 1.0E+16 1.0E+15 0
200
400
600
800
Depth (Angstroms) Fig. 1. As-implanted profilesmeasured by SIMS. The total boron dose is 3.79 x 10~s/cm2, and phophorous dose is 3.86x 1015/cm2.
255
J. Shao et al. / Surface and Coatings Technology 93 (1997) 254-257 1.00E+20
I0 8
1.00E+19
10 7
.~...... ...... : .... ....-:- .... .... - .... • .....
• A
E
AB A
10 s
dp (p/Veto)
E
1.00E+17
A A A
0 0
0
o:: T
10 6
1.00E+18 O
:
1.00E+16
~e
~o
104 Forward
. . . . . ucs -EATON(EA1)
"~ 10 3 co
O
1.00E+15
..... ~....... ~....
1.00E+14 0
0.1
0.2
t...... 0.3
E
10 2
g
lo1
Reverse
t
0.4 1 0°
Depth (microns)
Fig. 2. Junction depths measured by SRP. (A) 5 kV BF3, I050°C/I0 s, ./~ =262 f~/sq. (B) 5 kV 5% PHJH2, 850°C/20 s, R~=219 £~/sq.
10"1 10-2
Therefore, the damage profile is expected to be different from conventional implantation. In this paper, the properties of p* and n + junctions made under these conditions are studied.
2. Experimental Four-inch device wafers were prepared at UC Berkeley, which were masked either by Side_ or SiO2
•
;.
~,
~.
~
,
Bias V o l t a g e (Volts)
Fig. 4. I - V characteristics of diodes made by BF3 PIII.
plus photoresist (PR) patterns. The junction structures have diodes of area from 625 to 4 x 106gm 2 with LOCOS isolation [5]. The ion implantation was performed at Eaton. The BF3 plasma was generated by a
Effect of two.step anneal on sheet resistance
70
[]
Error
6O 600
2.4E15/c~
lkV E o 50
AO/ One.slep o C
'~ 40 400
\
(4
i\
30 ~Y~h800,0,20s
O
¢.
i / pfe.anneal
(o
5d
~,, 20 .J
10
d0s~35×I0~5~.2 I
1000'0,10s
I
10~0'0,20s
0 Mask:sio2
I
1050'0 10s
Method:
A~al cycle
SiOa
BF3 Pill
Comparison
of
PR
SiO~
BFa Pill
leakage
Fig. 3. Effect of two-step anneal on sheet resistance. The wafers were
Fig. 5.
imp~amedb'y gFa PIIi.
area = 0.04 cm2, bias voltage= - 5 V.
current
PFI
BF2 GSD
density.
Diode
256
Z Shao et at. / Surface and Coatings Technology 93 (1997) 254-257
with Si0 2 mask 100
,
1D't
f
g" lO.~
S lo-~ I) 10"~ "0 '~ t04
during PH3 PIII. For comparison, wafers were also implanted at 5 keV by a conventional GSD ion beam implanter at Eaton. After implantation, the wafers were annealed under different conditions at UC Berkeley. The electrical characteristics of these diodes were then measured.
with Si02 + PR mask
, . , .,.
100. . . . . . . . . . 10"~I
10.2l
__EA7- 5kV BF3RII 35x101Scm~ --EAS- 5kV I3t=3 P111 2.4xt0~Scm2 EA3-5keVBF2*GS0
1031
I,,
3. Results and discussion
- -
lO'sl
....
35x10~Scm~
EA5 -5kV BF3P[li 35×10~Scm"2 EA12-5kV BF3Ptli 24x10~¢m"2 .... EA6-SkeVB:2+GSD 3,SxlOlscln2
- -
1041
1@[
10q
10"~ O
104
.........
104 lO.loV:, . . . .
1040
1
2
3
4
0
1
2
3
4
Bias Voltage (Volts) Fig. 6. Comparison of electrical characteristics for diodes made by BFa PIII and by BF2 implant in GSD. large area ICP source at a pressure of 0.8 mTorr. Carrier gases Ha or He were used for the PH3 plasma with mixing ratios from 2 to 10%. Boron was implanted at - 5 and - 1 kV with dose of 2.4 or 3.5 x 10 ~5/cm 2. A typical implant time is 2.5 to 3.5 s at 5 kV. The corresponding Si etch rates during BF3 PIII were measured as 13.6 nm/min at 5 kV and 8.6 nm/min at 1 kV at the pulse rate of 12.5 kHz. The etch rate was negligible
Fig. 1 shows the as-implanted profiles at 5 kV for boron and phosphorus, where 92% of the dopants are located within 20 nm of the surface. The deeper range of phosphorus may be attributed to mass and etch rate differences. After one-step annealing, the junction depths Xj and sheet resistance Rs for 5 kV BF3 and PH3 doped wafers are as shown in Fig. 2. A two-step anneal may give a lower Rs (Fig. 3) and shorter Xj than a one-step anneal if the pre-anneal conditions are chosen so that it will remove implant damage without causing dopant movement [ 1,2]. However, if the time for the second step is too long or the pre-anneal temperature too high, the junction depth will be much deeper and dopant out-diffusion may be high. An average reverse-biased leakage current density of 3.7 nA/cm z was found for the diodes masked by SiO2. Fig. 4 shows the I - V curves of these diodes compared with a PIII diode made by UC Berkeley in 1993 [5]. The diode forward ideality factor (n) is 1.02. The higher saturation current of the forward I - V characteristics reflects the lower resistivity of the Eaton p + junction. The bumps shown in the reverse current at 3 V may indicate a layer of damage a short distance above the
S h a l l o w p+/n j u n c t i o n s b y p l a s m a i m p / a n tat/on 120 t V B = I O 18 c m -3
1 O0
0
E ¢--
v¢ - -
80
,...
(30
J
Fq
O
2. S h e n g , J V S T B, "1~ . 4 3 . F~lch~ M C U S D P , d 9 ~ 4. Ishk:~= M C U S D P , ' t 9 ~
¢-..
=
~, Jon~s~ EDL~ d g g 3 ~i Q l ~ n , A P L , tg1~t
40
7. F e l o h , liT, "lgg4.
O 20
SIMS SRP HALL
I~1
8, Q l n , T E D , 1 9 9 2 g , Qln~ PSST~ t £ g 2 "10. J o n ~ s , P h . D . 1:he$is, t g ~ 1 1 . U C B ,"]EJ~TON, 1 ~ 42. M ~:uno, V L ~ I ~ ¥ r n p . , d@Q5
0
i
0
i
2
i
4
Wafer
bias
8
6
during
implant
(kV)
Fig. 7. Correlation of junction depth after annealing to substrate bias.
10
J. Shao et al. / Surface and Coatings Technology 93 (1997) 254-257
junction. A better anneal process may eliminate theses bumps. Comparisons of leakage current density and electrical characteristics for diodes made by BF 3 PIII and by a BF2 ion beam implanter GSD with SiO2 and PR masks are shown in Figs. 5 and 6. The data did not show a correlation between the leakage current levels and the type of mask or dose. The PIII diodes show approximately equal electrical performance to those made by GSD implantation.
257
implant energies as low as possible for shallow junction formation, however, a proper annealing cycle based on defects engineering is needed to ensure the quality of the junctions.
References [1] E.C. Jones, N.W. Cheung, J.Q. Shao and A.S. Denholm, XI International Conference on Ion Implantation Technology, Austin, Texas, June 12-15, 1996.
[2] K.H. Lee, Y.S. Sotm, J.G. Oh, D.H. Lee, B.J. Cho and J.C. Kim, Ion Implantation Conference, Seottsdale, Arizona, 21-24 April, ]996.
4. Summary PIII is a promising method for fabricating ultrashallow junctions in VLSI devices. The junction depth of PIII-formed diodes made by different groups are shown in Fig. 7. A correlation between junction depth and implantation voltage is apparent, even though the data come from three different junction profiling methods. The spread of the data is due mostly to variation in annealing cycles. The trend recommends the use of
[3] A. Sultan, M. Craig, K. Reddy, E. Ishida, L. Larson, P. Maillot and S. Banerjee, SRC Pub C9608I, February I996. [4] M. Craig, A. Sultan, K. Reddy, S. Banerjee et al., J. Vac. Sci. Technol. B 14 (1996) 255-259. [5] E.C. Jones, N.W. Cheung, IEEE Electron Dev. Lett. 14 (1993) 444-446. [6] B. Mizuno, M. Takase, I. Nakayama and M. Ogura, IEEESymposlum on VLSI Technology Digest of Technical Papers, 1996, pp. 66-67. [7] S.B. Felch, T. Sheng, E. Gamn, K.K. Chan, D.L. Chapek, R.J. Matyi and J.R. Conrad, Ion hnpl. Tech., 94, North-Holland, Amsterdam, 1995, pp. 981-984.