Short-channel epitaxial germanium pMOS transistors

Thin Solid Films 518 (2010) S88–S91

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Thin Solid Films j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / t s f

Short-channel epitaxial germanium pMOS transistors G. Eneman a,b,c,⁎, B. De Jaeger a, G. Wang a,d, J. Mitard a,b, G. Hellings a,b, D.P. Brunco e,1, E. Simoen a, R. Loo a, M. Caymax a, C. Claeys a,b, K. De Meyer a,b, M. Meuris a, M.M. Heyns a,d a

IMEC, Kapeldreef 75, 3001 Leuven, Belgium ESAT-INSYS Division, Katholieke Universiteit Leuven, Belgium Fund for Scientific Research-Flanders, Belgium d MTM Department, Katholieke Universiteit Leuven, Belgium e Intel Corp., Hillsboro, Oregon 97124, USA b c

a r t i c l e

i n f o

Available online 19 October 2009 Keywords: Germanium Virtual substrates Junction leakage Epitaxy Shallow-Trench Isolation

a b s t r a c t This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epitaxial layers, selectively grown in Shallow-Trench Isolation (STI)-patterned wafers are presented. These thin layers show a 70% higher area junction leakage than thick Ge virtual substrates at 1 V bias, but the presence of STI reduces the leakage at the isolation perimeter by a factor of 5. Low-temperature epitaxial growth of silicon for gate dielectric applications is proposed as a solution to reduce the Equivalent Oxide Thickness (EOT). It is shown that a low-temperature (350 °C) recipe with a Si3H8 precursor leads to reduced Ge segregation towards the Si surface, and facilitates EOT scaling to 1 nm and below. Junction leakage generated under the transistor's spacer regions is analysed, and it is shown that this is the dominant junction leakage component in short-channel Ge technologies. As the leakage scales with electric field, reducing the supply voltage is suggested as a solution to keep this leakage component under control. © 2009 Elsevier B.V. All rights reserved.

1. Introduction Several research groups have demonstrated successful Ge pFET fabrication with different transistor architectures [1–5]. IMEC's technology on Ge-on-Si wafers demonstrated Ge pFET transistors with gate lengths LG = 190 nm in 2007 [6], LG = 125 nm in the same year [7], and LG = 70 nm in 2008 [2,8]. On the other hand, on nFETs, the gate passivation remains unsatisfactory [9]. Moreover, the electrical activation of n-type dopants in Ge is relatively low (below 5 × 1019 cm− 3), leading to a source/drain parasitic resistance that might be too high for decananometer nFETs [10,11]. Despite the promising results on pFETs, several challenges remain before they can be incorporated into high-performance CMOS technologies, something which is under consideration for the 16 nm node or below [12]. Implementing Ge pMOS while using a better performing nMOS semiconductor for CMOS requires that Ge is present only in the pMOS regions of the design, while another semiconductor is used in the nFET active areas. Another issue is that most Ge pFET gate dielectrics use multi-layer stacks, which severely complicates Equivalent Oxide Thickness (EOT) scaling down to the values specified by ITRS, 0.5 nm or lower. Finally, Ge's small band gap may lead to severely increased junction leakage as compared to Si ⁎ Corresponding author. IMEC, Kapeldreef 75, 3001 Leuven, Belgium. E-mail address: [email protected] (G. Eneman). 1 Formerly Intel Assignee to IMEC. 0040-6090/$ – see front matter © 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2009.10.063

technology, an effect that may be aggravated in scaled technologies with high electric fields present in the junctions. The purpose of this paper is to give an overview of the recent developments of IMEC's Ge pFET technology, especially in view of the challenges mentioned above. After briefly discussing the standard process flow, this paper presents advances in Ge epitaxial layer growth (Section 3.1), gate dielectric scaling (Section 3.2) and junction leakage control (Section 3.3).

2. Experimental Our standard process flow starts from an 8 inch, (100)-oriented Cz-Si wafers, with a 1.5 μm-thick, fully relaxed Ge virtual buffer on top. A Post-Growth (PG) anneal at 850 °C for 3 min in nitrogen ambient is given to reduce the Threading Dislocation Thickness (TDD) from 1 × 108 to 2 × 107 cm− 2 [13,14]. After this, n-type well regions are implanted, and 350 nm of silicon oxide is deposited and etched to define the transistor's active regions. At the time of the gate stack deposition and etching, this isolation leads to a topography of 175 nm. The gate stack is formed by a thin epitaxial silicon layer, grown in an ASM 2000 Epsilon reactor at a deposition temperature of 500 °C, partially oxidised in ozonated water, followed by 4 nm HfO2 deposited by Atomic Layer Deposition (ALD), leading to an EOT of 1.4 nm. The gate metal consists of 10 nm TaN and 70 nm TiN, deposited by Physical Vapor Deposition (PVD). Using this gate stack, hole mobilities

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have been demonstrated that are up to 2.5 times higher than the silicon universal hole mobility [7]. After gate definition, halos and extensions are implanted. Oxide/ nitride spacers with a total width of 90 nm are formed followed by a Ge pre-amorphization implant to increase the p-type dopant activation, and HDD implants. By using Sentaurus-Process simulations, the implant profiles have been matched to short-channel pFET profiles from silicon technology. With these implant conditions, excellent device characteristics have been demonstrated down to gate lengths of 70 nm [2]. The activation anneal is at 550 °C for 5 min. A two-step nickel germanidation [15] (5 nm deposited nickel) and a TiN/Ti/Al/TiN contact metallisation concluded the processing. 3. Results and discussion

Fig. 2. (Left) Area leakage JA and (right) isolation leakage JI, at a reverse bias of 1 V.

3.1. Thin Ge epitaxial layers: Towards a cost-effective CMOS solution The 1.5 μm-thick Ge-on-Si substrates described in Section 2 offer an excellent starting point for Ge MOS development, thanks to its low TDD of 2 × 107 cm− 2 [13] and RMS surface roughness below 0.4 nm. Thicker Ge layers tend to have a lower TDD [14], therefore several high-quality thick (>1 μm) layers with low TDD have been demonstrated, usually combining epitaxial growth with chemical–mechanical polishing to reduce the surface roughness [16]. On the other hand, because of the significant growth costs of thick Ge-on-Si layers, there is a strong drive to develop virtual substrates that are as thin as possible [17–19]. When the Ge growth process is selective towards SiO2, a thin Ge-on-Si solution offers an extra advantage: in this case it can be selectively grown only on specific areas of a wafer, after Shallow-Trench Isolation (STI) formation and silicon removal in the active regions. Furthermore, the use of STI as isolation technique leads to lower topography than a deposited oxide, and facilitates going to shorter gate lengths. Recently, selective 330 nm-thick Ge growth inside the active regions of STI-patterned wafers has been demonstrated by Wang et al. [18]. Starting from STI-patterned silicon wafers, about 330 nm of Si is selectively etched in an ASM Epsilon 2000 reactor. This is followed by undoped Ge epitaxial growth using a GeH4 precursor in a two-step process (450 °C, H2 carrier and 350 °C, N2 carrier). After growth, defect etching revealed a TDD of 2 × 1010 cm− 2. After a PG-anneal at 850 °C, the threading density is reduced to 4 × 108 cm− 2. The layers are smooth and show little or no facets, Fig. 1. P+/n junctions have been implanted in these layers to evaluate the diode leakage. These junctions are identical to the ones used in short-channel pFET fabrication. The leakage has been measured at a fixed reverse bias of 1 V, and has been decoupled into the area and isolation components JA and JI, respectively, using the methodology described in [20]. A comparison between the thin Ge epitaxial layers and the standard, 1.5 μm-thick substrates described in Section 2 is shown in Fig. 2 (left) for the area component, and Fig. 2 (right) for the isolation component. Thin Ge layers show about 70% higher area leakage than the reference substrates. Although the most probable reason for this is the higher TDD, the fact that JA scales nonlinearly with TDD suggests that other generation mechanisms contribute

Fig. 1. Cross-section Scanning Electron Micrograph of thin Ge epitaxial layers, selectively grown into STI-patterned silicon wafers (from [18]).

significantly to JA as well, such as generation through defects formed by the implantations. Although JA is increased for the thin epitaxial layers, they lead to about 5 times lower JI (Fig. 2, right), thanks to the STI that provides better isolation than the deposited oxide used for the thick substrates. For thin Ge epitaxial layers, several techniques have been proposed in literature to reduce the TDD further: when Ge is grown inside narrow STI trenches, threading dislocations will terminate at the STI oxide, leading to a nearly defect-free Ge top layer, a technique known as aspect-ratio trapping [19]. Another technique grows the Ge layer inside STI-patterned wafers, with significant overgrowth above the original silicon level. After PG-anneal and chemical–mechanical polishing of the Ge, this leads to 300 nm-thick epitaxial layers with a TDD below 1 × 107 cm− 2 [21]. 3.2. Gate stack: Towards sub-1 nm equivalent oxide thickness Our standard gate passivation uses a thin Si Interfacial Layer (IL), deposited at 500 °C with a SiH4 precursor, and has led to good shortchannel pFET performance [2]. Secondary Ion Mass Spectroscopy (SIMS) depth profiling revealed a significant Ge peak at the surface (Fig. 3), which is expected to have a detrimental effect on mobility. This is confirmed by interface trap density (DIT) measurements: Fig. 4 shows a steep increase of DIT for thinner silicon. The resulting degradation in performance puts a lower limit to the Equivalent Oxide Thickness (EOT) that can be reached with this growth process [8]. When using Si3H8 as the precursor gas, low-temperature (350 °C) Si deposition with reasonable growth rates is feasible [22,23]. SIMS profiling shows that the low-temperature process exhibits a significantly lower Ge peak at the Si surface, even for a thinner Si IL (Fig. 3). For a similar Si thickness, this leads to a lower DIT than for the hightemperature process (Fig. 4). As a consequence, the EOT can be scaled further, down to 1.05 nm, while maintaining excellent device characteristics [8]. Furthermore, EOT scaling down to 0.8 nm can be

Fig. 3. Raw SIMS Ge signal of Ge virtual substrate using a low-temperature and a hightemperature silicon passivation (from [8]).

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Fig. 4. Interface state density integrated over the valence band half for gate dielectrics using low- and a high-temperature Si IL growth (from [8]).

achieved [24] when low-temperature Si growth is combined with a reduced HfO2 thickness, facilitated by the low-topography process using thin Ge epitaxial layers and STI, described in Section 3.1. As to the physical origins of the reduced Ge peak for the lowtemperature process, it is suggested that this is caused by the difference in reaction chemistry between the SiH4 and Si3H8 precursor, rather than by the difference in deposition temperature. When using a Si3H8 precursor, the surface is hydrogen-passivated at all times [22], pushing Si to surface positions. This is confirmed by Ge segregation modeling, showing good agreement with experimental results [23,25]. 3.3. Junction leakage: Towards a low-leakage architecture Ge's band gap of 0.66 eV leads to an intrinsic carrier concentration ni that is about 2500 times larger than in Si. Short-channel HighlyDoped Drain (HDD) junction leakage is typically dominated by Shockley–Read–Hall (SRH) generation and Trap-Assisted Tunneling (TAT) [20]. The current for both mechanisms scales directly with ni, as the difference between Ge and Si for other parameters of these mechanisms, such as the TAT enhancement factor Γ is expected to be smaller [20]. As a consequence, HDD area leakage in Ge pFETs is around 4 × 10− 10 A/μm2 for short-channel (gate length of 70 nm) implant conditions at 1 V reverse bias, as can be seen from the reference data in Fig. 2 (left). Besides leakage through the HDDs, drain-to-bulk leakage in pFETs will also be generated at the edge between the active regions and the isolation (isolation leakage JI), and under the transistor's spacers, in the junction formed by the extension and halo implants (extension leakage JE). These components are indicated in Fig. 5. JA and JI can be determined from diode measurements (Fig. 2), while JE needs to be measured on transistors, in off-state condition. Comparison of JI and JE indicates that for short-channel transistors, the latter is dominant: JI values below 1 × 10− 9 A/μm are feasible by using STI as the isolation scheme (Fig. 2, right), while JE is 1 × 10− 7 A/ μm or higher, and reaches 4 × 10− 7 A/μm for IMEC's standard shortchannel pFET halo dose of 5 × 1013 cm− 2 (Fig. 6). JE shows an exponential dependence on the dose of the halo implant, and increases

Fig. 5. Schematic cross-section of a Ge pFET, indicating the different components of drain-to-substrate leakage: area leakage JA, isolation leakage JI and extension leakage JE.

Fig. 6. Extension leakage JE versus halo dose, measured on pFET transistors, in off-state condition (VGate = VTSAT + 0.33 V; VDrain = − 1 V, with VTSAT the transistor's saturation threshold voltage).

by more than a factor of 7 when the halo dose is increased by 85%, from 3.5 × 1013 to 6.5 × 1013 cm− 2. The reason for this is likely the higher electric fields inside the junction's Space Charge Region (SCR), leading in turn to enhanced Band-To-Band Tunneling (BTBT). This dependence of JE is well-known from silicon [26], but the absolute leakage levels are higher in a Ge technology because of the smaller band gap. Due to the electric field dependence of JE, reducing the supply voltage should lead to a reduction of the leakage. After determination of JA, JI and JE, the contribution of each component can be estimated for a minimised layout with typical dimensions of the 45 nm ITRS node [12]. When taking a transistor with a gate width W of 100 nm and a rectangular active area with a length LA of 150 nm, and using the leakage values for the thick Ge reference substrates (JA = 4.3 × 10− 10 A/μm2, JI = 2.5 × 10− 9 A/μm, JE = 4.1 × 10− 7 A/μm at 1 V supply voltage), this leads to: • Area leakage contribution: JA · W · LA = 6.5 × 10− 12 A • Isolation leakage contribution: JI · (W + 2LA) = 1.0 × 10− 9 A • Extension leakage contribution: JE · W = 4.1 × 10− 8 A. This confirms that in scaled layouts, the extension component is dominant, similar as in silicon-based technologies [26]. Further scaling of Ge CMOS technologies will require higher doping levels to improve short-channel control. From Fig. 6, it can be expected that it will get increasingly challenging to keep the extension leakage within acceptable values. Several alternative transistor architectures with Ge channels may lead to significant reduction of the leakage, and have been proposed or demonstrated in literature. Amongst the most interesting options are Ge-on-insulator and FinFET transistors [1,4,5], as well as high-hole mobility transistors, where the junctions are placed next to the transistor's gate regions by epitaxial growth, rather than through implants [27]. 4. Conclusions The purpose of this paper is to indicate what the most important remaining challenges are to incorporate a Ge pFET technology, using Ge epitaxial growth on silicon wafers, into commercial products. One challenge is the need for high-quality thin (<500 nm) Ge epitaxial layers, as it provides a route towards CMOS integration, as well as to reduce material costs. As thinner layers generally have a higher TDD, there is a concern whether this compromises the device characteristics. This work presented 330 nm-thin Ge-on-Si epitaxial layers, that are selectively grown inside the active regions of STIpatterned Si wafers. These Ge layers show 70% higher area junction leakage than thick Ge virtual substrates with 20 times lower TDD. As the total leakage is dominated by other components, such as leakage through the extension regions, using thin Ge epitaxial layers should not influence the total leakage significantly.

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High mobilities and good short-channel characteristics have been demonstrated with a gate dielectric passivation consisting of Si/SiO2/ HfO2. However, the presence of these three different layers makes EOT scaling below 1 nm challenging. One concern is the presence of a Ge peak at the surface after the growth of the silicon interfacial layer: this leads to an increased interface state density and limits the scalability of the dielectric. A low-temperature (350 °C) process is demonstrated with Si3H8 as precursor that leads to reduction of the Ge segregation, and facilitates EOT scaling below 1 nm. Technology scaling requires the use of higher doping levels. This in turn leads to higher electric fields and increased leakage. For shortchannel implant conditions, leakage through the transistor's extension regions is dominant in a scaled layout at 1 V supply voltage. It is indicated that this leakage component depends exponentially on electric field, therefore reducing the supply voltage should decrease the junction leakage significantly. If supply voltage reduction proves to be insufficient, alternative architectures, such as Ge-on-Insulator, Ge FinFETs and Ge high-electron-mobility transistors may provide a route towards a low-leakage Ge-based technology. References [1] E. Batail, S. Monfray, C. Tabone, O. Kermarrec, J. Damlencourt, P. Gautier, G. Rabille, C. Arvet, N. Loubet, Y. Campidelli, J. Hartmann, A. Pouydebasque, V. Delaye, C.L. Royer, G. Ghibaudo, T. Skotnicki, S. Deleonibus, 2008 IEEE International Electron Devices Meeting—IEDM '08, 2008, p. 397. [2] G. Hellings, J. Mitard, G. Eneman, B. De Jaeger, D. Brunco, D. Shamiryan, T. Vandeweyer, M. Meuris, M. Heyns, K. De Meyer, IEEE Electron Device Lett. 30 (1) (2009) 88. [3] T. Yamamoto, Y. Yamashita, M. Harada, N. Taoka, K. Ikeda, K. Suzuki, O. Kiso, N. Sugiyama, S. Takagi, 2007 IEEE International Electron Devices Meeting—IEDM '07, 2007, p. 1041. [4] J. Feng, R. Woo, S. Chen, Y. Liu, P. Griffin, J. Plummer, IEEE Electron Device Lett. 28 (7) (2007) 637. [5] T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi, K. Saraswat, IEEE Trans. Electron Devices 53 (5) (2006) 990. [6] B. De Jaeger, B. Kaczer, P. Zimmerman, K. Opsomer, G. Winderickx, J. Van Steenbergen, E. Van Moorhem, V. Terzieva, R. Bonzom, F. Leys, C. Arena, M. Bauer, C. Werkhoven, M. Caymax, M. Meuris, M. Heyns, Semicond. Sci. Technol. 22 (1) (2007) S221. [7] G. Nicholas, B. De Jaeger, D. Brunco, P. Zimmerman, G. Eneman, K. Martens, M. Meuris, M. Heyns, IEEE Trans. Electron Devices 54 (9) (2007) 2503.

S91

[8] J. Mitard, B. De Jaeger, F. Leys, G. Hellings, K. Martens, G. Eneman, D. Brunco, R. Loo, J. Lin, D. Shamiryan, T. Vandeweyer, G. Winderickx, E. Vrancken, C. Yu, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, M. Heyns, 2008 IEEE International Electron Devices Meeting—IEDM '08, 2008, p. 873. [9] Y. Kamata, Mater. Today 11 (1–2) (2008) 30. [10] C.O. Chui, L. Kulig, J. Moran, W. Tsai, K.C. Saraswat, Appl. Phys. Lett. 87 (9) (2005) 091909 (3 pp.). [11] D. Brunco, B. De Jaeger, G. Eneman, J. Mitard, G. Hellings, A. Satta, V. Terzieva, L. Souriau, F. Leys, G. Pourtois, M. Houssa, G. Winderickx, E. Vrancken, S. Sioncke, K. Opsomer, G. Nicholas, M. Caymax, A. Stesmans, J. Van Steenbergen, P. Mertens, M. Meuris, M. Heyns, J. Electrochem. Soc. 155 (7) (2008) H552. [12] ITRS roadmap for semiconductors, ITRS 2007 edition, process integration, devices and structures. URL http://www.itrs.net/Links/2007ITRS/Home2007.htm. [13] V. Terzieva, L. Souriau, M. Caymax, D. Brunco, A. Moussa, S. Van Elshocht, R. Loo, F. Clemente, A. Satta, M. Meuris, Thin Solid Films 517 (1) (2008) 172. [14] G. Wang, R. Loo, E. Simoen, L. Souriau, M. Caymax, M.M. Heyns, B. Blanpain, Appl. Phys. Lett. 94 (10) (2009) 102115. [15] D. Brunco, K. Opsomer, B. De Jaeger, G. Winderickx, K. Verheyden, M. Meuris, Electrochem. Solid-State Lett. 11 (2) (2008) H39. [16] A. Nylandsted Larsen, Mater. Sci. Semicond. Process. 9 (4–5) (2006) 454. [17] J. Oh, P. Majhi, H. Lee, O. Yoo, S. Banerjee, C. Kang, J.-W. Yang, R. Harris, H.-H. Tseng, R. Jammy, IEEE Electron Device Lett. 28 (11) (2007) 1044. [18] G. Wang, F.E. Leys, L. Souriau, R. Loo, M. Caymax, D.P. Brunco, J. Geypen, H. Bender, M. Meuris, W. Vandervorst, M.M. Heyns, ECS Trans. 16 (10) (2008) 829. [19] J.-S. Park, M. Curtin, J.M. Hydrick, J. Bai, M. Carroll, J.G. Fiorenza, A. Lochtefeld, J. Electrochem. Soc. 156 (4) (2009) H249. [20] G. Eneman, M. Wiot, A. Brugere, O. Casain, S. Sonde, D. Brunco, B. De Jaeger, A. Satta, G. Hellings, K. De Meyer, C. Claeys, M. Meuris, M. Heyns, E. Simoen, IEEE Trans. Electron Devices 55 (9) (2008) 2287. [21] G. Wang, R. Loo, L. Souriau, S. Takeuchi, B. De Jaeger, W. Lee, M. Caymax, J. Lin, W. Vandervorst, B. Blanpain, M.M. Heyns, Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches, Thin Solid Films (2009), doi:10.1016/j.tsf.2009.09.133. [22] F. Leys, R. Bonzom, B. Kaczer, T. Janssens, W. Vandervorst, B. De Jaeger, J. Van Steenbergen, K. Martens, D. Hellin, J. Rip, G. Dilliway, A. Delabie, P. Zimmerman, M. Houssa, A. Theuwis, R. Loo, M. Meuris, M. Caymax, M. Heyns, Mater. Sci. Semicond. Process. 9 (4–5) (2006) 679. [23] M. Caymax, F. Leys, J. Mitard, K. Martens, L. Yang, G. Pourtois, W. Vandervorst, M. Meuris, R. Loo, ECS Trans. 19 (1) (2009) 183. [24] J. Mitard, C. Shea, B. De Jaeger, A. Pristera, G. Wang, M. Houssa, G. Eneman, G. Hellings, W.-E. Wang, J. Lin, F. Leys, R. Loo, G. Winderickx, E. Vrancken, A. Stesmans, K. DeMeyer, M. Caymax, L. Pantisano, M. Meuris, M. Heyns, VLSI Symposium Tech. Dig., 2009, p. 82. [25] L. Yang, G. Pourtois, M. Caymax, A. Ceulemans, M. Heyns, Phys. Rev., B, Condens. Matter Mater. Phys. 79 (16) (2009) 165312. [26] R. Duffy, A. Heringa, J. Loo, E. Augendre, S. Severi, G. Curatola, ECS Trans. 3 (2) (2006) 19. [27] G. Hellings, G. Eneman, B.D. Jaeger, J. Mitard, N. Waldron, K.D. Meyer, M. Meuris, M.M. Heyns, Scalability of quantum well devices for digital logic applications, Abstract book of the Silicon Nanoelectronics Workshop, vol. 1 (1), 2009, p. 33.