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Si (001) surface defects after extended high temperature annealing
Materials Science and Engineering B71 (2000) 276 – 281 www.elsevier.com/locate/mseb
Si (001) surface defects after extended high temperature annealing D. Barge a,*, J.P. Joly a, G. Rolland b, B. Pichaud c a
De´partement Microtechnologies, CEA/LETI, 17 rue des Martyrs, 38054 Grenoble Cedex, France b De´partement Optronique, CEA/LETI, 17 rue des Martyrs, 38054 Grenoble Cedex, France c MATOP, Faculte´ des Sciences de Saint Je´rome, 13397 Marseille, France
Abstract Deep diffusion of dopants in Si 001 requires temperature annealing as high as 1250°C and more for several days, in a quasi-neutral atmosphere. We have shown that such thermal treatment strongly affects the surface morphology, creating several-micrometers long, 10–50 nm deep square-shaped pits faceted along the 110 directions, with a density of 10 defects/cm2 for a 50-h anneal. These kind of defects, although reported in the literature for different experimental conditions, have not been studied in details. These defects grow as the annealing time increases. A second annealing in similar conditions shows a striking difference of behavior between CZ- and FZ-grown wafers, the latter having a defect density rising up to 104/cm2. It is believed that the metallic contaminants accumulated during the first annealing precipitate during cooling and eventually dissolve during further thermal treatment, leaving small marks on the surface which grow to micron-sized squares via a surface reconstruction. Comparisons have been made between the evolution of these defects and patterns with various depths followed by a high-temperature annealing. © 2000 Elsevier Science S.A. All rights reserved. Keywords: Si; Annealing; 001-Surface; Defects; Metallic impurities; Step bunching
1. Introduction
2. Experimental
The creation of a complementary well is a common step in microelectronics, essential in many devices design. Building a well requires a diffusion annealing which allows complementary dopants to diffuse into the bulk silicon. Specific applications need deep wells. Temperatures as high as 1250°C and more are therefore needed. Even at high temperature several days are needed to obtain deep wells of our interest. This need for deep diffusion leads us to annealing conditions rarely investigated both in time and temperature range. The surface of the wafer was found to be affected very strongly by such a thermal treatment: surface defects with specific shapes strongly linked to crystallographic orientation are observed. In this paper we describe the growth of these defects and propose some tracks to explain their origin.
CZ-/FZ-, n- and p-type Si (001) wafers with different oxide thickness were annealed in a slightly oxidizing atmosphere. A: 1:100 oxygen/neutral gas ratio was used to avoid thermal etching of silicon at a temperature of 1280°C. This is the maximum temperature available in our facility. The annealing times were, respectively, 50 and 100 h (samples A). Other samples had two 50-h annealing separated by a temperature ramp down to room temperature in order to check any difference of behavior with a straight annealing (samples B). Similarly, some wafers were annealed once again for 5, 10, 15, 50 and 100 h after removal of the thin oxide created during 100 h annealing (samples C). Finally, a standard photolithographic process combined with plasma etching was used to perform etched marks into silicon with controlled dimensions. Depths from 50 to 300 nm were used with various patterns to create trenches and squared or circular holes with lateral dimensions from 0.6 to 5 mm. All theses marks were spaced by 10 mm on wafers which were annealed for 10, 20 and 40 h (samples D). For any samples, a standard RCA cleaning has preceded any heat-treatment and the
* Corresponding author. Tel.: +33-4-7688-3021; fax: + 33-4-76889456.
0921-5107/00/$ - see front matter © 2000 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 1 - 5 1 0 7 ( 9 9 ) 0 0 3 9 0 - 6
D. Barge et al. / Materials Science and Engineering B71 (2000) 276–281
277
Fig. 1. Observation of the evolution of the defect with time (samples B).
oxide resulting from the slightly oxidizing atmosphere has been measured by ellipsometry. The surface of the samples were then observed by optical microscope, optical-interferometry profilometer and Wright etch. Micro-photoconductive decay (Micro-PCD) in high injection mode was used to monitor the contamination in the bulk silicon. Characterization of the surface misorientation has been done by X-ray diffraction when needed. The estimation of hypothetical evaporation of silicon was performed by evaluating the different oxide and silicon thickness on a SOI structure by ellipsometry before and after our annealings.
3. Defect description When FZ- and CZ-wafer underwent a single annealing (samples A), surface defects with a density between 1 and 80/cm2 could be observed. FZ samples showed a systematically low defect density (below 10/ cm2), while for CZ we got a higher density (40–80/ cm2). These defects were square-shaped holes faceted along the [110] directions. Their distribution was homogenous, however, any accidental scratch on the wafer was decorated with many square defects in its neighborhood. Defects depth was typically between 10 and 100 nm, therefore a microscope with a Normasky prism was needed for a convenient and accurate observation. For FZ samples, the defect’s shape changed with annealing duration: for the shortest time, the defects looked like squares, but with longer time they evolved to a triangular shape, as it can be seen in Fig. 1. It was noticed that all the triangles were oriented in the same direction on the whole wafer. On CZ wafers the square shape holds, even for the longest annealing duration studied.
3.1. Effect of high temperatures cycles Samples annealed several times such as sample group B showed a dramatic difference compared with sample A. Whereas for FZ samples a 100-h long annealing gave a few defects/cm2, two 50-h runs separated by a temperature ramp down to room temperature gave a much larger defect density (about a 1000 times). CZ-samples with two sequential anneals exhibited similar behavior, but the defect density was raised by only one order of magnitude (Fig. 2).
3.2. Defect size kinetics Taking advantage of the large density of defects created by a high-temperature cycle, FZ wafers were annealed for 100 h at 1280°C, desoxided, and then re-heated at 1280°C for different times (samples C). Defect densitys as high as 106/cm2 were observed, which were 100 times higher than for samples B. The density measured on the wafers was roughly identical for all these samples: increasing the annealing duration did not create new defects. This is consistent with the observations discussed in Section 3.1. With increasing time, the defect’s average depth decreased regularly. Their aspect was affected also: defects evolved from a square to a triangular shape (see
Fig. 2. Influence of substrate nature and high temperatures cycles on the defect density (* with oxide removal between the two annealings).
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3.3. Effect of oxide protection
Fig. 3. Size evolution of defects.
Fig. 1). The defect growth kinetics, estimated by an optical microscope, fitted fairly well with a square-root law, as it can be seen in Fig. 3. The evolution of marks intentionally printed into the silicon (samples D) has been investigated also and used as a tool for a better understanding of the defect growth. Circular, squared-like holes and trenches with different depths (50, 120, 250 nm) were performed. With annealing, a dramatic expansion of the marks was observed. Fig. 4 illustrates this spectacular effect. All these marks grew in a comparable way regardless of their original size and shape; for example, originally designed 2 mm-diameter circular and 2 mm-long squared-like marks gave identical squares after the thermal treatment, and the same dimension increase was found for 5 mm-long squares. The depth of the marks seemed play a key role in the extension kinetics: shallow (50 nm) marks extended much faster than deeper ones. The growth kinetics of marks, compared with the defect kinetics is plotted in Fig. 3. Annealing for longer time makes the marks join, but not collapse, and eventually evolve towards a triangular shape. Further 50-h annealing creates triangular defects oriented exactly in the same way, as mentioned before for defect evolution.
A 50-nm and a 1-mm thick oxide was grown on FZ wafers to check the oxide influence on the defect creation. After the first 50-h anneal, none of the samples exhibited any defects with a density over 1/cm2. After a further 50-h annealing, defects with a density of 104/ cm2 could be seen on the surface for the sample initially covered by a 50-nm oxide. The sample with a thick oxide remained free of any surface defects. A 1 mmthick oxide is therefore an effective protection against these surface defects. However, if this oxide is removed between after the first annealing, defects appears with a density reaching 103/cm2. These experiments suggest that a 1 mm-thick oxide prevents the defect extension but not the formation of the defect nuclei.
4. Interpretation: defect origin and growth
4.1. Defect origin Marks printed into the silicon showed regular extension during annealing in a similar way as the surface defect observed in bare silicon under inert annealing conditions. Moreover, both marks and surface defects evolve to a triangular shape after a long annealing. We can therefore assume that small holes would behave in the same way as the microscopic surface defects do. The origin of the defect could be either a local thermal etching favored by precipitated impurities like metals or a dissolution of precipitates leaving small marks in the silicon. Whereas measurements done on a SOI wafer showed that the silicon evaporation/etching in our annealing condition for 100 h is not measurable globally, a local etching is still possible. Despite the absence of direct observation by TEM analysis, the hypothesis of a precipitation is supported by several clues. First, the behavior difference between samples with multiple anneals compared with samples with a
Fig. 4. view of a network of 1-mm large, 120 nm deep holes. Left-hand sided photo shows the network before any heat treatment. Right-hand sided photo shows the same network after 100 H annealing.
D. Barge et al. / Materials Science and Engineering B71 (2000) 276–281
279
Fig. 5. Correlation between oxidation induced stacking faults density after a 16-h dry oxidation and high temperature surface defects revealed by further anneals at 1280°C.
straight one shows that a temperature ramp down and up is needed to create the surface defects nuclei. Moreover, we have measured significant quantity of metallic impurities. Vapor phase decomposition and atomic absorption spectroscopy (VPD – AAS) showed an iron concentration in the oxide reaching 1012/cm2, consistent with the estimation derived from lifetime measurements by micro-PCD on FZ/P-type wafers. For uncoated samples the average lifetime fell below 0.5 ms, and can be linked with a contamination of 1014/cm3 [1]. The difference of behavior between CZ and FZ wafers could be explained by a natural internal gettering of contamination by oxygen precipitates during the temperature ramp up of the second annealing. Eventually, a 16-h dry oxidation of samples followed by a Wright-etch revealed stacking faults (SF) in a density comparable with surface defects obtained by further annealing for non-deoxidized FZ-samples (see Fig. 5). The origin of these oxidation induced stacking faults (OISF) is believed to be linked with metallic precipitates. It is known that highly contaminated samples with metallic impurities cause OISF [2]. However, other possible sources for OISF exist. For example, surface pits are believed to be able to create stacking faults during oxidation [3]. For CZ samples no OISF could be observed, and therefore no correlation with surface defects could be done.
4.2. Defect growth The evolution of the defects and marks can at least be qualitatively understood if we consider the properties of a free Si (001) surface annealed in ultra-high vacuum conditions (UHV). It is known that in UHV the diffusion of steps on the Si (001) surface happens in the [110] direction, which correspond to the faces of our squares-like defects. At high temperature (\1250°), in UHV and in absence of any surface accident a surface vicinal to a (001) plane consist in monoatomic terraces oriented in the [110] and [116 0] directions [4], statistically separated by a distance corresponding with the deviation angle to a perfect 001 surface. Although it is known that on a Si-(001) surface two kinds of terraces (SA, SB) with very distinct behavior exist [4], we will consider in this paper
that all terraces are equivalent for simplicity. In this temperature range, and in vacuum conditions a monoatomic step emits adatoms on the terrace below and therefore retreats. As a consequence a continuous ‘step flow’ results. The step’s velocity depends on the size of the terraces. A global step flow have been reported on Si (111) at all temperature and in Si (001) below 1180°C [5]. Above 1180°C, the step flow still exists but other phenomena such as steps creation and holes formation was reported also [5]. It seems then clear that a deep surface accident will affect strongly the step flow. A narrow and deep hole will locally creates a high number of steps on its both sides which are much smaller than steps located outside the hole. As a step velocity is expected to be dependent with the length of its neighboring terrace, one can expects that these steps will have much a different speed than the steps far from the hole. These differences may lead to collision between steps created by the surface accident with the steps coming from the unperturbed area of the wafer, resulting in a step bunching which delay the step flow at this point. Quite recently creation of craters and patterned structures to produce step bunches by further annealing in ultra high vacuum, sometimes in combination of a DC current, have been studied [6,5,7]. This local accumulation of steps allowed the creation of step-free surfaces as large as 10 mm on (111)-Si [5] and (001)-Si [6,7]. We believe that in our oxidizing conditions the step flow similar to the one observed in UHV is at the origin of the creation of our defects. A surface reconstruction scenario could be then considered to explain the defect growth. We must keep in mind however that in oxidizing conditions the surface diffusion is certainly much different at least in kinetics since the surface is covered by an oxide as thick as 300 nm after 100 h. At the beginning, we expect that our defect is a small pit which can be idealized as a collection of small steps accumulated on each side of the hole, as drawn in Fig. 6. The other steps present on the figure are linked with miscut to a perfect 001 plane. We assume that the steps flow behaves as in evaporation condition in UHV and move as plotted in Fig. 7. As this behavior happens in both 110 and 116 0 directions, a squared-like pit is created.
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Fig. 6. An idealized pit made with short terraces.
Fig. 7. Defect growth driven by the step flow. Arrows shows the flow direction for each kind of steps.
For longer time, step train A in Fig. 7 will interfere with the step flow coming from the opposite direction. As a consequence, as it is etched on both side, the upper terrace of step train A will disappear. The next terraces on the right side of step train A will collapse similarly, as long as steps train A exits. After step train A has disappeared completely, a large 001 terrace will result. The defect will then appear ansiotropic, with one side with a rather sharp shape, and the other side a smooth one corresponding to a real 001 plane which join the misoriented surface. Fig. 8 illustrates the final aspect of a defect using our arguments. The validity of this qualitative description can be easily evaluated by comparing the angle made by the bottom with the surface and the misorientation angle. The direction of the misorientation axis has been compared with the intersection made by the bottom of the defect with the surface. If our assumptions are correct, they should be parallel. An estimation of the angle and direction of the miscut to the 001 surface were performed by X-ray diffraction. For FZ-samples the misorientation axis was found to be close to a 100 direction. The miscut angle was estimated to be 0.57 90.01° to a 001 plane. For CZ samples we found a miscut angle of 0.11° to a 001 plane. Table 1 gives the misorientation angle deduced from X-ray diffraction and the angle made the by the smooth slope to the surface, measured in a direction perpendicular to the miscut axis determined by X-ray. This angle was determined using optical profilometry. One can notice that a qualitative agreement between the two values. Moreover, the miscut axis is exactly in the direction predicted by our scenario (see Fig. 9).
5. Conclusions We have investigated the surface stability of (001) Si at high temperature in a slightly oxidizing atmosphere. This thermal treatment creates surface defects, which are very likely microscopic holes growing to a macroscopic scale by silicon diffusion. The defect expansion can be qualitatively understood if one considers the properties of a Si 001 surface described usually in UHV in this temperature range. This interpretation makes sense if we admit that mechanisms similar to the ones encountered in UHV are present in slightly oxidizing conditions. In this case it could give new interesting development for step-free surface processing, since conventional furnaces could be used to create large step-
Fig. 8. Schematic cross-section of a defect after a long annealing, based on our assumptions, with a misorientation axis parallel to 100 direction. Table 1 Correlation between misorientation and the angle made with the smooth slope with the surface Wafer type
Misorientation angle (°)
Angle made by the smooth slope with the surface (°)
FZ CZ
0.57 90.01 0.11 90.01
0.40 0.20
D. Barge et al. / Materials Science and Engineering B71 (2000) 276–281
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Fig. 9. Correlation with the triangular shape and the misorientation axis the topography plotted in the foreground corresponds to the cross section according to the line delimited by the two squares on the figure.
free 001 surfaces by adapting the techniques reported in literature for UHV. However, much longer time would be needed to have step-free surfaces of comparable sizes. The origin of the defect nuclei have not been identified yet. However, several experimental results show that a high temperature cycle is needed to produce these defect in large quantities. Therefore, we suspect that these holes are linked to impurities precipitation. These impurities are suspected be metals. These defects can be avoided successfully by a thick oxide growth before this thermal treatment.
.
References [1] A. Kempf, P. Bo¨chl, A. Huber, Electrochem. Soc. Proc. 98-13 (1998) 221. [2] M. Hourai, K. Murakami, T. Shigematsu, Jpn. J. Appl. Phys. 28 (1989) 2413. [3] T.K. Monson, J.A. Vechten, J. Electrochem. Soc. 146 (2) (1999) 741. [4] A.W. Munz, Ch. Ziegler, W. Go¨pel, Surf. Sci. 325 (1995) 177. [5] Y. Homma, N. Aizawa, T. Ogino, Jpn. J. Appl. Phys. 35 (1996) 241. [6] S. Tanaka, C.C. Umbach, J.M. Backley, App. Phys. Lett. 69 (1996) 1235. [7] A. Ando, K. Sakamoto, K. Miki, et al., Jpn. J. Appl. Phys. 36 (1997) 1424.
Si (001) surface defects after extended high temperature annealing D. Barge a,*, J.P. Joly a, G. Rolland b, B. Pichaud c a
De´partement Microtechnologies, CEA/LETI, 17 rue des Martyrs, 38054 Grenoble Cedex, France b De´partement Optronique, CEA/LETI, 17 rue des Martyrs, 38054 Grenoble Cedex, France c MATOP, Faculte´ des Sciences de Saint Je´rome, 13397 Marseille, France
Abstract Deep diffusion of dopants in Si 001 requires temperature annealing as high as 1250°C and more for several days, in a quasi-neutral atmosphere. We have shown that such thermal treatment strongly affects the surface morphology, creating several-micrometers long, 10–50 nm deep square-shaped pits faceted along the 110 directions, with a density of 10 defects/cm2 for a 50-h anneal. These kind of defects, although reported in the literature for different experimental conditions, have not been studied in details. These defects grow as the annealing time increases. A second annealing in similar conditions shows a striking difference of behavior between CZ- and FZ-grown wafers, the latter having a defect density rising up to 104/cm2. It is believed that the metallic contaminants accumulated during the first annealing precipitate during cooling and eventually dissolve during further thermal treatment, leaving small marks on the surface which grow to micron-sized squares via a surface reconstruction. Comparisons have been made between the evolution of these defects and patterns with various depths followed by a high-temperature annealing. © 2000 Elsevier Science S.A. All rights reserved. Keywords: Si; Annealing; 001-Surface; Defects; Metallic impurities; Step bunching
1. Introduction
2. Experimental
The creation of a complementary well is a common step in microelectronics, essential in many devices design. Building a well requires a diffusion annealing which allows complementary dopants to diffuse into the bulk silicon. Specific applications need deep wells. Temperatures as high as 1250°C and more are therefore needed. Even at high temperature several days are needed to obtain deep wells of our interest. This need for deep diffusion leads us to annealing conditions rarely investigated both in time and temperature range. The surface of the wafer was found to be affected very strongly by such a thermal treatment: surface defects with specific shapes strongly linked to crystallographic orientation are observed. In this paper we describe the growth of these defects and propose some tracks to explain their origin.
CZ-/FZ-, n- and p-type Si (001) wafers with different oxide thickness were annealed in a slightly oxidizing atmosphere. A: 1:100 oxygen/neutral gas ratio was used to avoid thermal etching of silicon at a temperature of 1280°C. This is the maximum temperature available in our facility. The annealing times were, respectively, 50 and 100 h (samples A). Other samples had two 50-h annealing separated by a temperature ramp down to room temperature in order to check any difference of behavior with a straight annealing (samples B). Similarly, some wafers were annealed once again for 5, 10, 15, 50 and 100 h after removal of the thin oxide created during 100 h annealing (samples C). Finally, a standard photolithographic process combined with plasma etching was used to perform etched marks into silicon with controlled dimensions. Depths from 50 to 300 nm were used with various patterns to create trenches and squared or circular holes with lateral dimensions from 0.6 to 5 mm. All theses marks were spaced by 10 mm on wafers which were annealed for 10, 20 and 40 h (samples D). For any samples, a standard RCA cleaning has preceded any heat-treatment and the
* Corresponding author. Tel.: +33-4-7688-3021; fax: + 33-4-76889456.
0921-5107/00/$ - see front matter © 2000 Elsevier Science S.A. All rights reserved. PII: S 0 9 2 1 - 5 1 0 7 ( 9 9 ) 0 0 3 9 0 - 6
D. Barge et al. / Materials Science and Engineering B71 (2000) 276–281
277
Fig. 1. Observation of the evolution of the defect with time (samples B).
oxide resulting from the slightly oxidizing atmosphere has been measured by ellipsometry. The surface of the samples were then observed by optical microscope, optical-interferometry profilometer and Wright etch. Micro-photoconductive decay (Micro-PCD) in high injection mode was used to monitor the contamination in the bulk silicon. Characterization of the surface misorientation has been done by X-ray diffraction when needed. The estimation of hypothetical evaporation of silicon was performed by evaluating the different oxide and silicon thickness on a SOI structure by ellipsometry before and after our annealings.
3. Defect description When FZ- and CZ-wafer underwent a single annealing (samples A), surface defects with a density between 1 and 80/cm2 could be observed. FZ samples showed a systematically low defect density (below 10/ cm2), while for CZ we got a higher density (40–80/ cm2). These defects were square-shaped holes faceted along the [110] directions. Their distribution was homogenous, however, any accidental scratch on the wafer was decorated with many square defects in its neighborhood. Defects depth was typically between 10 and 100 nm, therefore a microscope with a Normasky prism was needed for a convenient and accurate observation. For FZ samples, the defect’s shape changed with annealing duration: for the shortest time, the defects looked like squares, but with longer time they evolved to a triangular shape, as it can be seen in Fig. 1. It was noticed that all the triangles were oriented in the same direction on the whole wafer. On CZ wafers the square shape holds, even for the longest annealing duration studied.
3.1. Effect of high temperatures cycles Samples annealed several times such as sample group B showed a dramatic difference compared with sample A. Whereas for FZ samples a 100-h long annealing gave a few defects/cm2, two 50-h runs separated by a temperature ramp down to room temperature gave a much larger defect density (about a 1000 times). CZ-samples with two sequential anneals exhibited similar behavior, but the defect density was raised by only one order of magnitude (Fig. 2).
3.2. Defect size kinetics Taking advantage of the large density of defects created by a high-temperature cycle, FZ wafers were annealed for 100 h at 1280°C, desoxided, and then re-heated at 1280°C for different times (samples C). Defect densitys as high as 106/cm2 were observed, which were 100 times higher than for samples B. The density measured on the wafers was roughly identical for all these samples: increasing the annealing duration did not create new defects. This is consistent with the observations discussed in Section 3.1. With increasing time, the defect’s average depth decreased regularly. Their aspect was affected also: defects evolved from a square to a triangular shape (see
Fig. 2. Influence of substrate nature and high temperatures cycles on the defect density (* with oxide removal between the two annealings).
278
D. Barge et al. / Materials Science and Engineering B71 (2000) 276–281
3.3. Effect of oxide protection
Fig. 3. Size evolution of defects.
Fig. 1). The defect growth kinetics, estimated by an optical microscope, fitted fairly well with a square-root law, as it can be seen in Fig. 3. The evolution of marks intentionally printed into the silicon (samples D) has been investigated also and used as a tool for a better understanding of the defect growth. Circular, squared-like holes and trenches with different depths (50, 120, 250 nm) were performed. With annealing, a dramatic expansion of the marks was observed. Fig. 4 illustrates this spectacular effect. All these marks grew in a comparable way regardless of their original size and shape; for example, originally designed 2 mm-diameter circular and 2 mm-long squared-like marks gave identical squares after the thermal treatment, and the same dimension increase was found for 5 mm-long squares. The depth of the marks seemed play a key role in the extension kinetics: shallow (50 nm) marks extended much faster than deeper ones. The growth kinetics of marks, compared with the defect kinetics is plotted in Fig. 3. Annealing for longer time makes the marks join, but not collapse, and eventually evolve towards a triangular shape. Further 50-h annealing creates triangular defects oriented exactly in the same way, as mentioned before for defect evolution.
A 50-nm and a 1-mm thick oxide was grown on FZ wafers to check the oxide influence on the defect creation. After the first 50-h anneal, none of the samples exhibited any defects with a density over 1/cm2. After a further 50-h annealing, defects with a density of 104/ cm2 could be seen on the surface for the sample initially covered by a 50-nm oxide. The sample with a thick oxide remained free of any surface defects. A 1 mmthick oxide is therefore an effective protection against these surface defects. However, if this oxide is removed between after the first annealing, defects appears with a density reaching 103/cm2. These experiments suggest that a 1 mm-thick oxide prevents the defect extension but not the formation of the defect nuclei.
4. Interpretation: defect origin and growth
4.1. Defect origin Marks printed into the silicon showed regular extension during annealing in a similar way as the surface defect observed in bare silicon under inert annealing conditions. Moreover, both marks and surface defects evolve to a triangular shape after a long annealing. We can therefore assume that small holes would behave in the same way as the microscopic surface defects do. The origin of the defect could be either a local thermal etching favored by precipitated impurities like metals or a dissolution of precipitates leaving small marks in the silicon. Whereas measurements done on a SOI wafer showed that the silicon evaporation/etching in our annealing condition for 100 h is not measurable globally, a local etching is still possible. Despite the absence of direct observation by TEM analysis, the hypothesis of a precipitation is supported by several clues. First, the behavior difference between samples with multiple anneals compared with samples with a
Fig. 4. view of a network of 1-mm large, 120 nm deep holes. Left-hand sided photo shows the network before any heat treatment. Right-hand sided photo shows the same network after 100 H annealing.
D. Barge et al. / Materials Science and Engineering B71 (2000) 276–281
279
Fig. 5. Correlation between oxidation induced stacking faults density after a 16-h dry oxidation and high temperature surface defects revealed by further anneals at 1280°C.
straight one shows that a temperature ramp down and up is needed to create the surface defects nuclei. Moreover, we have measured significant quantity of metallic impurities. Vapor phase decomposition and atomic absorption spectroscopy (VPD – AAS) showed an iron concentration in the oxide reaching 1012/cm2, consistent with the estimation derived from lifetime measurements by micro-PCD on FZ/P-type wafers. For uncoated samples the average lifetime fell below 0.5 ms, and can be linked with a contamination of 1014/cm3 [1]. The difference of behavior between CZ and FZ wafers could be explained by a natural internal gettering of contamination by oxygen precipitates during the temperature ramp up of the second annealing. Eventually, a 16-h dry oxidation of samples followed by a Wright-etch revealed stacking faults (SF) in a density comparable with surface defects obtained by further annealing for non-deoxidized FZ-samples (see Fig. 5). The origin of these oxidation induced stacking faults (OISF) is believed to be linked with metallic precipitates. It is known that highly contaminated samples with metallic impurities cause OISF [2]. However, other possible sources for OISF exist. For example, surface pits are believed to be able to create stacking faults during oxidation [3]. For CZ samples no OISF could be observed, and therefore no correlation with surface defects could be done.
4.2. Defect growth The evolution of the defects and marks can at least be qualitatively understood if we consider the properties of a free Si (001) surface annealed in ultra-high vacuum conditions (UHV). It is known that in UHV the diffusion of steps on the Si (001) surface happens in the [110] direction, which correspond to the faces of our squares-like defects. At high temperature (\1250°), in UHV and in absence of any surface accident a surface vicinal to a (001) plane consist in monoatomic terraces oriented in the [110] and [116 0] directions [4], statistically separated by a distance corresponding with the deviation angle to a perfect 001 surface. Although it is known that on a Si-(001) surface two kinds of terraces (SA, SB) with very distinct behavior exist [4], we will consider in this paper
that all terraces are equivalent for simplicity. In this temperature range, and in vacuum conditions a monoatomic step emits adatoms on the terrace below and therefore retreats. As a consequence a continuous ‘step flow’ results. The step’s velocity depends on the size of the terraces. A global step flow have been reported on Si (111) at all temperature and in Si (001) below 1180°C [5]. Above 1180°C, the step flow still exists but other phenomena such as steps creation and holes formation was reported also [5]. It seems then clear that a deep surface accident will affect strongly the step flow. A narrow and deep hole will locally creates a high number of steps on its both sides which are much smaller than steps located outside the hole. As a step velocity is expected to be dependent with the length of its neighboring terrace, one can expects that these steps will have much a different speed than the steps far from the hole. These differences may lead to collision between steps created by the surface accident with the steps coming from the unperturbed area of the wafer, resulting in a step bunching which delay the step flow at this point. Quite recently creation of craters and patterned structures to produce step bunches by further annealing in ultra high vacuum, sometimes in combination of a DC current, have been studied [6,5,7]. This local accumulation of steps allowed the creation of step-free surfaces as large as 10 mm on (111)-Si [5] and (001)-Si [6,7]. We believe that in our oxidizing conditions the step flow similar to the one observed in UHV is at the origin of the creation of our defects. A surface reconstruction scenario could be then considered to explain the defect growth. We must keep in mind however that in oxidizing conditions the surface diffusion is certainly much different at least in kinetics since the surface is covered by an oxide as thick as 300 nm after 100 h. At the beginning, we expect that our defect is a small pit which can be idealized as a collection of small steps accumulated on each side of the hole, as drawn in Fig. 6. The other steps present on the figure are linked with miscut to a perfect 001 plane. We assume that the steps flow behaves as in evaporation condition in UHV and move as plotted in Fig. 7. As this behavior happens in both 110 and 116 0 directions, a squared-like pit is created.
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D. Barge et al. / Materials Science and Engineering B71 (2000) 276–281
Fig. 6. An idealized pit made with short terraces.
Fig. 7. Defect growth driven by the step flow. Arrows shows the flow direction for each kind of steps.
For longer time, step train A in Fig. 7 will interfere with the step flow coming from the opposite direction. As a consequence, as it is etched on both side, the upper terrace of step train A will disappear. The next terraces on the right side of step train A will collapse similarly, as long as steps train A exits. After step train A has disappeared completely, a large 001 terrace will result. The defect will then appear ansiotropic, with one side with a rather sharp shape, and the other side a smooth one corresponding to a real 001 plane which join the misoriented surface. Fig. 8 illustrates the final aspect of a defect using our arguments. The validity of this qualitative description can be easily evaluated by comparing the angle made by the bottom with the surface and the misorientation angle. The direction of the misorientation axis has been compared with the intersection made by the bottom of the defect with the surface. If our assumptions are correct, they should be parallel. An estimation of the angle and direction of the miscut to the 001 surface were performed by X-ray diffraction. For FZ-samples the misorientation axis was found to be close to a 100 direction. The miscut angle was estimated to be 0.57 90.01° to a 001 plane. For CZ samples we found a miscut angle of 0.11° to a 001 plane. Table 1 gives the misorientation angle deduced from X-ray diffraction and the angle made the by the smooth slope to the surface, measured in a direction perpendicular to the miscut axis determined by X-ray. This angle was determined using optical profilometry. One can notice that a qualitative agreement between the two values. Moreover, the miscut axis is exactly in the direction predicted by our scenario (see Fig. 9).
5. Conclusions We have investigated the surface stability of (001) Si at high temperature in a slightly oxidizing atmosphere. This thermal treatment creates surface defects, which are very likely microscopic holes growing to a macroscopic scale by silicon diffusion. The defect expansion can be qualitatively understood if one considers the properties of a Si 001 surface described usually in UHV in this temperature range. This interpretation makes sense if we admit that mechanisms similar to the ones encountered in UHV are present in slightly oxidizing conditions. In this case it could give new interesting development for step-free surface processing, since conventional furnaces could be used to create large step-
Fig. 8. Schematic cross-section of a defect after a long annealing, based on our assumptions, with a misorientation axis parallel to 100 direction. Table 1 Correlation between misorientation and the angle made with the smooth slope with the surface Wafer type
Misorientation angle (°)
Angle made by the smooth slope with the surface (°)
FZ CZ
0.57 90.01 0.11 90.01
0.40 0.20
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Fig. 9. Correlation with the triangular shape and the misorientation axis the topography plotted in the foreground corresponds to the cross section according to the line delimited by the two squares on the figure.
free 001 surfaces by adapting the techniques reported in literature for UHV. However, much longer time would be needed to have step-free surfaces of comparable sizes. The origin of the defect nuclei have not been identified yet. However, several experimental results show that a high temperature cycle is needed to produce these defect in large quantities. Therefore, we suspect that these holes are linked to impurities precipitation. These impurities are suspected be metals. These defects can be avoided successfully by a thick oxide growth before this thermal treatment.
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