- Email: [email protected]
SiGe based low noise amplifier for WLAN applications
Applied Surface Science 224 (2004) 419–424
SiGe based low noise amplifier for WLAN applications J. Sadowya,b, D. Dubuca, J.P. Busquerea,b, K. Greniera, I. Telliezb, J. Graffeuila, E. Tourniera, R. Planaa,* b
a LAAS CNRS 7, Av du Colonel Roche, 31077 Toulouse Cedex, France ST Microelectronics 850, Rue Jean Monnet, 38926 Crolles Cedex, France
Abstract This paper presents broad band low noise amplifier for WLAN applications featuring both low noise, high linearity and low dc power consumption. Low noise figure lower than 2 dB has been obtained with IIP3 of 9 dBm and power gain larger than 20 dB using an original bias technique. Another issue has been investigated concerning LNA having very low power consumption. We have obtained a Pdc of 9 mW with 2.5 dB noise figure 17 dB gain and IIP3 of 6.2 dBm. # 2003 Elsevier B.V. All rights reserved. PACS: 61.72.T; 73.40; 85.40.Q; 84.40.L Keywords: SiGeBiCMOS; LNA; Noise figure; Linearity; WLAN
1. Introduction The Wireless Local Area Network applications are exploding and the situation will continue in the future. Consequently, this will have a strong impact on the requirements for the next generation of the RF modules. In order to satisfy these requirements, the RF modules will have to be optimized with respect to the noise issues in order to enhance the sensitivity of the terminal, the linearity, the bandwidth to meet the high bit rate demand, the power consumption and the time to the market. The latter point suggests to investigate design methodology having a high level of ruggeness in order to minimize the prototyping phase. The allocated frequency for WLAN applications ranges from 5 to 6 GHz and there is a strong need to design RF circuits featuring high level performance. Silicon based technologies * Corresponding author. Fax: þ33-561-336-969. E-mail address: [email protected] (R. Plana).
have shown very attractive capabilities and today, two types of technology are competing, the CMOS one and the SiGe based one (that is actually also CMOS compatible). This paper focuses on the exploitation of SiGe based technology to design a broad band range low noise amplifier (which is one of the key elements in the performance of the RF module). The main issue is to find design solutions to overcome the linearity and power consumption limitations, keeping the noise performance as good as possible. The paper will be organized as follows. Section 2 will briefly outline the SiGe based technology that has been used. Section 3 will address the design methodology we have developed in order to get a high ruggedness design and will present a low noise amplifier featuring both low noise and high linearity behavior. Section 4 will present another topology of low noise amplifier featuring a very low dc power consumption. Section 5 will present a comparison with the state of the art whereas Section 6 will deal with the conclusions.
0169-4332/$ – see front matter # 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.apsusc.2003.08.104
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J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
2. Technology The SiGe technology that has been used in this work has been developed by ST Microelectronics. It consists of a SiGe based BiCMOS technology featuring five metal level, a 0.35 mm emitter window. The breakdown voltage for the active devices ranges from 5.5 to 3.3 V following the option chosen. The frequency performances are in the range of 50–60 GHz both for the cut-off frequency and maximum oscillation frequency. Device isolation is done through LOCOS process and the quality factor for inductor are in the range of 15. The next section will present the design methodology we have developed to get a high design accuracy, in order to minimize the prototyping phase.
3. Low noise high linearity LNA The amplifier under discussion is a conventional cascode topology with an appropriate inductive feedback in order to achieve low noise, large bandwidth and high gain. The transistors have been sized with respect to their noise behavior (minimum noise figure, equivalent noise resistance and optimum input terminal). Note
that the inductor has been designed using electromagnetic simulation. In order to accomodate the noise matching conditions and the power matching conditions, we have used a very low value inductor that has been obtained using a loop topology. We have to outline that a very low value inductor is more sensitive to the parasitics. In order to get a very precise estimation of the parasitics related to the layout, we have done some physical simulations using ASITIC software. Note that these simulations have permitted to minimize the layout influence and to get a better accuracy with respect to the measurements. Fig. 1 shows the gain and noise figure measurements that have been done at a wafer level using a KarlZuss probe station. Note that appropriate noise calibration has been carried out in order to extract the noise behavior of the circuit itself. The first comment deals with the exhibited performances, as we report a maximum gain larger than 20 dB with a noise figure in the 2 dB range. The 3 dB frequency bandwidth has been measured in the 2 GHz range. We can furthermore observe that the agreement between simulation and measurement is very good and that the design exhibits a high ruggedness as we have tested numerous chips, and the dispersion behavior was very small. Another point can be observed related to the sensitivity of the amplifier with respect to the bias conditions. The
Fig. 1. Measured and simulated noise figure and gain for different dc bias conditions.
J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
421
Table 1 Comparison of measurements and simulation for a broad band SiGe LNA
Gain (dB) Ic (mA) P (mW) Gmax/P (dB/mW) Nfmin (dB)
Bias-a
Bias-b
Bias-c
Bias-d
Bias-e
Simulation
20.2 6.9 22.7 0.90 2.1
20.5 6.8 22.52 0.91 2
20.7 7.3 24 0.86 1.97
20.8 7.8 25.7 0.81 1.95
21 8.3 27.36 0.77 2
20.7 7 23 0.9 1.9
circuits have been measured at different bias conditions and the results are summarized in Table 1. We can observe that varying the bias current 20%, turns out in a dynamic performance change lower than 1%, which is very important for portable applications when the equipment will be affected by battery fluctuations, as the circuit keeps similar performance with different bias current. Finally, we have done large signal measurements through input referred 1 dB compression point, that has been measured in the 22 dBm range. Input referred third intermodulation intercept point has been measured in the 11 dBm range. In this case, we have to outline that a good agreement has been found with simulation which validates the models we have used, both for transistors and passives (resistor, capacitor, inductor and parasitics), and which validates our design methodology. Finally, Fig. 2 shows the photography of the circuit which features a 1:2 mm 1:3 mm area. In order to improve the linearity performance, we have investigated the different solutions. It is well
Fig. 2. Photography of the LNA-circuit surface (1:2 mm 1:3 mm).
known that increasing the dc bias is favourable for linearity improvement. Nevertheless, we decided to investigate theoretically the linearity behavior of the amplifier. Preliminary works done by Fong [7] and Watanabe [8] have demonstrated that a dramatic improvement of the linearity can be achieved by modifying the dc and RF input termination. Actually, it has been demonstrated that short circuiting the signal at the Df ¼ f2 f1 (f1 and f2 are the two tone frequencies) frequency results in a linearity improvement. Nevertheless, for noise conditions, the RF termination has to be as high as possible. So the idea is to design a circuit featuring a variable resistance featuring a very low value in the very low frequency range and high value in the high frequency range. The variable resistance circuit has been designed through an operational amplifier (referred to as oa). Note that most of the operational amplifiers have been designed using CMOS devices in order to minimize the dc power consumption. It has been possible due to the compatibility of the SiGe technology we used with a CMOS process. Special attention has been paid concerning the stability of this circuit and concerning the power consumption and its immunity with respect to the noise. Actually, we made sure that the bias circuit does not degrade the noise figure of the circuit. A low noise amplifier similar to the previous one has been designed using this concept in order to evaluate its performance. Fig. 3 displays the simulations that have been done and shows the expected improvement using this concept. The circuit has been fabricated and the large signal measurements are reported in Fig. 4. We can remark that we got a linearity improvement of 2 dB without noise figure and gain degradation. We also have to outline that this circuit does not feature additional dc consumption. Nevertheless, the measured results are different than the expected ones.
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J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
This is actually due to a bandwidth problem of the bias circuit that could be solved using CMOS devices featuring smaller dimensions. The next section of this paper will deal with a low noise amplifier featuring a very low dc power consumption.
4. Low power consumption LNA
Fig. 3. Simulation of the output power Pout and intermodulation products (IM3) for two dc bias topologies: (a) conventional bias and (b) bias using variable resistance circuit.
In order to consider a low dc power consumption LNA, we have adopted a folded common emitter topology. The circuit has been designed according to a similar methodology as previously described. The circuit has been fabricated and measured at a wafer level. The results have shown that it can turn out to very attractive properties as reported in Table 2. More precisely, it has shown a reduced dc power consumption lower than 10 mW for a noise figure of 2.5 dB (which still meets the WLAN requirements). The linearity performance are a 1 dB compression point of 16.5 dBm and a third input intermodulation intercept point of 6.2 dBm with a conventional bias topology (note that additional improvement will be expected using an operational amplifier). Again the results demonstrate the ruggedness of the design as the performances are very stable with respect to the dc bias. Additionally, we have to outline that the ratio between dynamic gain and dc power consumption is very high which confirms the high level of performance of this circuit. Section 5 will discuss the results that have been obtained by comparing them with the state of the art of the low noise amplifier.
5. Comparative study Fig. 4. Measurements of the output power Pout and intermodulation products (IM3) for two dc bias topologies: (a) conventional bias and (b) bias using variable resistance circuit.
In order to well compare different low noise amplifiers, we have decided to evaluate two figures of merit.
Table 2 Comparison between measurements (done at different dc bias) and simulation for a very low power LNA
P (mW) Gmax (dB) Gmax/P (dB/mW) Nfmin (dB)
Bias-a
Bias-b
Bias-c
Bias-d
Bias-e
Bias-f
Bias-g
Simulation
9.6 16.5 1.72 2.53
10.6 16.6 1.57 2.51
11.2 16.8 1.5 2.45
12.36 16.9 1.37 2.53
13.35 17 1.27 2.51
19.4 18 0.93 2.56
16.53 16.9 1.02 2.52
11.4 20 1.75 2.4
J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
423
Fig. 5. Comparative study of the gain, dc consumption figure of merit for different SiGe based LNA [1–7].
The first one is actually related to the yield exhibited by the circuit measured through the ratio between the dynamic gain and the dc power consumption. Fig. 5 shows a comparative study for a set of low noise amplifier already published. We have to note that the higher is the figure of merit, the better is the amplifier. It is interesting to note that most of the circuit features a figure of merit value in the 1 range
when larger values are reported for this work in the 1.8 range. In order to be complete, we have also decided to evaluate the noise figure performance. We have defined a new figure of merit which takes into account the RF gain, the noise figure and the dc power consumption. We believe that it is important to take into account the dc power consumption as it is always tricky to lower the dc bias maintaining the noise figure
Fig. 6. LNA figure of merit for a set of SiGe based LNA [1–6].
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J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
very low. The expression of the figure of merit is given by the following equation. LNAF:O:M ¼
Nf Pdc 1 ð1=GÞ
(1)
where Nf represents the noise figure, G the dynamic gain and Pdc the dc power consumption. Fig. 6 displayed the evolution of the figure of merit for a set of low noise amplifier already published. This time it is understood that lower is the figure of merit better is the circuit. The results indicate that most of the amplifiers exhibit a value in the 5 range when better results are in the range of 3. We have to note that two circuits feature better performance than our circuit. The reasons are the following. One reference concerns a pure 0.25 mm SiGe bipolar technology which is CMOS incompatible and the other one discusses a more complicated technology featuring higher metal level and smaller emitter dimensions. So, we can state that the circuits that are presented in this paper are at the state of the art of the low noise amplifier using silicon based technologies.
6. Conclusions This paper presents the results obtained on an advanced low noise amplifier for Wireless Local Area Network in the 5–6 GHz range. A specific design approach has been used through electrical, electromagnetic simulations to get a good agreement between simulations and measurements. We have used a variable active resistance concept that has turned out to a linearity improvement of 2 dB when the noise figure is unchanged lower than 2 dB. Another topology has been proposed featuring a very low power
consumption and high linearity, and a noise figure in the 2.5 dB range. The circuits have been compared with their counterparts through two figures of merit that have shown performances at the state of the art.
References [1] J. Sadowy, I. Telliez, J. Graffeuil, E. Tournier, L. Escotte, R. Plana, Low noise, high linearity, wide bandwidth amplifier using a 0.35 mm SiGe BiCMOS for WLAN applications, in: Proceedings of the Radio Frequency Integrated Circuits (RFIC) Symposium, Seattle, 2002, pp. 217–220. [2] U. Erben, H. Schumacher, A. Schuppen, J. Arndt, Application of SiGe heterojunction bipolar transistors in 5.8 and 10 GHz low-noise amplifiers, Electron. Lett. 34 (15) (1998) 1498– 1500. [3] D. Zoschg, H. knapp, T.F. Meister, W. Wilhelm, J. Bock, M. Wurzer, K. Aufinger, H.D. Wohlmuth, A.L. Scholtz, Monolithic low Noise Amplifiers up to 10 GHz in silicon and SiGe bipolar technologies, Microwave Engineering Europe, March 2001, pp. 59–62. [4] T. Nakatani, J. Itoh, I. Imanishi, O. Ishikawa, A Wide Dynamic Range Switched-LNA in SiGe BiCMOS, Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers. 2001 IEEE, 2001, pp. 223–2326. [5] T. Nakatani, J. Itoh, I. Imanishi, O. Ishikawa, A Wide Dynamic Range Switched-LNA in SiGe BiCMOS, Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers. 2001 IEEE, 2001, pp. 223–2326. [6] D. Wang, K. Krishnamurthi, S. Gibson, J. Brunt, A 2.5 GHz low noise high linearity LNA/mixer IC in SiGe BiCMOS technology, Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers. 2001 IEEE, 2001, pp. 249–252. [7] K.L. Fong, High frequency analysis of linearity improvement technique of common emitter transconductance stage using a low frequency trap network, IEEE J. Solid State Circuits 35 (9) (2000) 1249–1252. [8] D. Watanabe, et al., IP3 Boost Circuitry For Highly Linear CDMA Low Noise Amplifier, in: Proceedings of the Asia Pacific Microwave Conference, December 2000, pp 213–214.
SiGe based low noise amplifier for WLAN applications J. Sadowya,b, D. Dubuca, J.P. Busquerea,b, K. Greniera, I. Telliezb, J. Graffeuila, E. Tourniera, R. Planaa,* b
a LAAS CNRS 7, Av du Colonel Roche, 31077 Toulouse Cedex, France ST Microelectronics 850, Rue Jean Monnet, 38926 Crolles Cedex, France
Abstract This paper presents broad band low noise amplifier for WLAN applications featuring both low noise, high linearity and low dc power consumption. Low noise figure lower than 2 dB has been obtained with IIP3 of 9 dBm and power gain larger than 20 dB using an original bias technique. Another issue has been investigated concerning LNA having very low power consumption. We have obtained a Pdc of 9 mW with 2.5 dB noise figure 17 dB gain and IIP3 of 6.2 dBm. # 2003 Elsevier B.V. All rights reserved. PACS: 61.72.T; 73.40; 85.40.Q; 84.40.L Keywords: SiGeBiCMOS; LNA; Noise figure; Linearity; WLAN
1. Introduction The Wireless Local Area Network applications are exploding and the situation will continue in the future. Consequently, this will have a strong impact on the requirements for the next generation of the RF modules. In order to satisfy these requirements, the RF modules will have to be optimized with respect to the noise issues in order to enhance the sensitivity of the terminal, the linearity, the bandwidth to meet the high bit rate demand, the power consumption and the time to the market. The latter point suggests to investigate design methodology having a high level of ruggeness in order to minimize the prototyping phase. The allocated frequency for WLAN applications ranges from 5 to 6 GHz and there is a strong need to design RF circuits featuring high level performance. Silicon based technologies * Corresponding author. Fax: þ33-561-336-969. E-mail address: [email protected] (R. Plana).
have shown very attractive capabilities and today, two types of technology are competing, the CMOS one and the SiGe based one (that is actually also CMOS compatible). This paper focuses on the exploitation of SiGe based technology to design a broad band range low noise amplifier (which is one of the key elements in the performance of the RF module). The main issue is to find design solutions to overcome the linearity and power consumption limitations, keeping the noise performance as good as possible. The paper will be organized as follows. Section 2 will briefly outline the SiGe based technology that has been used. Section 3 will address the design methodology we have developed in order to get a high ruggedness design and will present a low noise amplifier featuring both low noise and high linearity behavior. Section 4 will present another topology of low noise amplifier featuring a very low dc power consumption. Section 5 will present a comparison with the state of the art whereas Section 6 will deal with the conclusions.
0169-4332/$ – see front matter # 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.apsusc.2003.08.104
420
J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
2. Technology The SiGe technology that has been used in this work has been developed by ST Microelectronics. It consists of a SiGe based BiCMOS technology featuring five metal level, a 0.35 mm emitter window. The breakdown voltage for the active devices ranges from 5.5 to 3.3 V following the option chosen. The frequency performances are in the range of 50–60 GHz both for the cut-off frequency and maximum oscillation frequency. Device isolation is done through LOCOS process and the quality factor for inductor are in the range of 15. The next section will present the design methodology we have developed to get a high design accuracy, in order to minimize the prototyping phase.
3. Low noise high linearity LNA The amplifier under discussion is a conventional cascode topology with an appropriate inductive feedback in order to achieve low noise, large bandwidth and high gain. The transistors have been sized with respect to their noise behavior (minimum noise figure, equivalent noise resistance and optimum input terminal). Note
that the inductor has been designed using electromagnetic simulation. In order to accomodate the noise matching conditions and the power matching conditions, we have used a very low value inductor that has been obtained using a loop topology. We have to outline that a very low value inductor is more sensitive to the parasitics. In order to get a very precise estimation of the parasitics related to the layout, we have done some physical simulations using ASITIC software. Note that these simulations have permitted to minimize the layout influence and to get a better accuracy with respect to the measurements. Fig. 1 shows the gain and noise figure measurements that have been done at a wafer level using a KarlZuss probe station. Note that appropriate noise calibration has been carried out in order to extract the noise behavior of the circuit itself. The first comment deals with the exhibited performances, as we report a maximum gain larger than 20 dB with a noise figure in the 2 dB range. The 3 dB frequency bandwidth has been measured in the 2 GHz range. We can furthermore observe that the agreement between simulation and measurement is very good and that the design exhibits a high ruggedness as we have tested numerous chips, and the dispersion behavior was very small. Another point can be observed related to the sensitivity of the amplifier with respect to the bias conditions. The
Fig. 1. Measured and simulated noise figure and gain for different dc bias conditions.
J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
421
Table 1 Comparison of measurements and simulation for a broad band SiGe LNA
Gain (dB) Ic (mA) P (mW) Gmax/P (dB/mW) Nfmin (dB)
Bias-a
Bias-b
Bias-c
Bias-d
Bias-e
Simulation
20.2 6.9 22.7 0.90 2.1
20.5 6.8 22.52 0.91 2
20.7 7.3 24 0.86 1.97
20.8 7.8 25.7 0.81 1.95
21 8.3 27.36 0.77 2
20.7 7 23 0.9 1.9
circuits have been measured at different bias conditions and the results are summarized in Table 1. We can observe that varying the bias current 20%, turns out in a dynamic performance change lower than 1%, which is very important for portable applications when the equipment will be affected by battery fluctuations, as the circuit keeps similar performance with different bias current. Finally, we have done large signal measurements through input referred 1 dB compression point, that has been measured in the 22 dBm range. Input referred third intermodulation intercept point has been measured in the 11 dBm range. In this case, we have to outline that a good agreement has been found with simulation which validates the models we have used, both for transistors and passives (resistor, capacitor, inductor and parasitics), and which validates our design methodology. Finally, Fig. 2 shows the photography of the circuit which features a 1:2 mm 1:3 mm area. In order to improve the linearity performance, we have investigated the different solutions. It is well
Fig. 2. Photography of the LNA-circuit surface (1:2 mm 1:3 mm).
known that increasing the dc bias is favourable for linearity improvement. Nevertheless, we decided to investigate theoretically the linearity behavior of the amplifier. Preliminary works done by Fong [7] and Watanabe [8] have demonstrated that a dramatic improvement of the linearity can be achieved by modifying the dc and RF input termination. Actually, it has been demonstrated that short circuiting the signal at the Df ¼ f2 f1 (f1 and f2 are the two tone frequencies) frequency results in a linearity improvement. Nevertheless, for noise conditions, the RF termination has to be as high as possible. So the idea is to design a circuit featuring a variable resistance featuring a very low value in the very low frequency range and high value in the high frequency range. The variable resistance circuit has been designed through an operational amplifier (referred to as oa). Note that most of the operational amplifiers have been designed using CMOS devices in order to minimize the dc power consumption. It has been possible due to the compatibility of the SiGe technology we used with a CMOS process. Special attention has been paid concerning the stability of this circuit and concerning the power consumption and its immunity with respect to the noise. Actually, we made sure that the bias circuit does not degrade the noise figure of the circuit. A low noise amplifier similar to the previous one has been designed using this concept in order to evaluate its performance. Fig. 3 displays the simulations that have been done and shows the expected improvement using this concept. The circuit has been fabricated and the large signal measurements are reported in Fig. 4. We can remark that we got a linearity improvement of 2 dB without noise figure and gain degradation. We also have to outline that this circuit does not feature additional dc consumption. Nevertheless, the measured results are different than the expected ones.
422
J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
This is actually due to a bandwidth problem of the bias circuit that could be solved using CMOS devices featuring smaller dimensions. The next section of this paper will deal with a low noise amplifier featuring a very low dc power consumption.
4. Low power consumption LNA
Fig. 3. Simulation of the output power Pout and intermodulation products (IM3) for two dc bias topologies: (a) conventional bias and (b) bias using variable resistance circuit.
In order to consider a low dc power consumption LNA, we have adopted a folded common emitter topology. The circuit has been designed according to a similar methodology as previously described. The circuit has been fabricated and measured at a wafer level. The results have shown that it can turn out to very attractive properties as reported in Table 2. More precisely, it has shown a reduced dc power consumption lower than 10 mW for a noise figure of 2.5 dB (which still meets the WLAN requirements). The linearity performance are a 1 dB compression point of 16.5 dBm and a third input intermodulation intercept point of 6.2 dBm with a conventional bias topology (note that additional improvement will be expected using an operational amplifier). Again the results demonstrate the ruggedness of the design as the performances are very stable with respect to the dc bias. Additionally, we have to outline that the ratio between dynamic gain and dc power consumption is very high which confirms the high level of performance of this circuit. Section 5 will discuss the results that have been obtained by comparing them with the state of the art of the low noise amplifier.
5. Comparative study Fig. 4. Measurements of the output power Pout and intermodulation products (IM3) for two dc bias topologies: (a) conventional bias and (b) bias using variable resistance circuit.
In order to well compare different low noise amplifiers, we have decided to evaluate two figures of merit.
Table 2 Comparison between measurements (done at different dc bias) and simulation for a very low power LNA
P (mW) Gmax (dB) Gmax/P (dB/mW) Nfmin (dB)
Bias-a
Bias-b
Bias-c
Bias-d
Bias-e
Bias-f
Bias-g
Simulation
9.6 16.5 1.72 2.53
10.6 16.6 1.57 2.51
11.2 16.8 1.5 2.45
12.36 16.9 1.37 2.53
13.35 17 1.27 2.51
19.4 18 0.93 2.56
16.53 16.9 1.02 2.52
11.4 20 1.75 2.4
J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
423
Fig. 5. Comparative study of the gain, dc consumption figure of merit for different SiGe based LNA [1–7].
The first one is actually related to the yield exhibited by the circuit measured through the ratio between the dynamic gain and the dc power consumption. Fig. 5 shows a comparative study for a set of low noise amplifier already published. We have to note that the higher is the figure of merit, the better is the amplifier. It is interesting to note that most of the circuit features a figure of merit value in the 1 range
when larger values are reported for this work in the 1.8 range. In order to be complete, we have also decided to evaluate the noise figure performance. We have defined a new figure of merit which takes into account the RF gain, the noise figure and the dc power consumption. We believe that it is important to take into account the dc power consumption as it is always tricky to lower the dc bias maintaining the noise figure
Fig. 6. LNA figure of merit for a set of SiGe based LNA [1–6].
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J. Sadowy et al. / Applied Surface Science 224 (2004) 419–424
very low. The expression of the figure of merit is given by the following equation. LNAF:O:M ¼
Nf Pdc 1 ð1=GÞ
(1)
where Nf represents the noise figure, G the dynamic gain and Pdc the dc power consumption. Fig. 6 displayed the evolution of the figure of merit for a set of low noise amplifier already published. This time it is understood that lower is the figure of merit better is the circuit. The results indicate that most of the amplifiers exhibit a value in the 5 range when better results are in the range of 3. We have to note that two circuits feature better performance than our circuit. The reasons are the following. One reference concerns a pure 0.25 mm SiGe bipolar technology which is CMOS incompatible and the other one discusses a more complicated technology featuring higher metal level and smaller emitter dimensions. So, we can state that the circuits that are presented in this paper are at the state of the art of the low noise amplifier using silicon based technologies.
6. Conclusions This paper presents the results obtained on an advanced low noise amplifier for Wireless Local Area Network in the 5–6 GHz range. A specific design approach has been used through electrical, electromagnetic simulations to get a good agreement between simulations and measurements. We have used a variable active resistance concept that has turned out to a linearity improvement of 2 dB when the noise figure is unchanged lower than 2 dB. Another topology has been proposed featuring a very low power
consumption and high linearity, and a noise figure in the 2.5 dB range. The circuits have been compared with their counterparts through two figures of merit that have shown performances at the state of the art.
References [1] J. Sadowy, I. Telliez, J. Graffeuil, E. Tournier, L. Escotte, R. Plana, Low noise, high linearity, wide bandwidth amplifier using a 0.35 mm SiGe BiCMOS for WLAN applications, in: Proceedings of the Radio Frequency Integrated Circuits (RFIC) Symposium, Seattle, 2002, pp. 217–220. [2] U. Erben, H. Schumacher, A. Schuppen, J. Arndt, Application of SiGe heterojunction bipolar transistors in 5.8 and 10 GHz low-noise amplifiers, Electron. Lett. 34 (15) (1998) 1498– 1500. [3] D. Zoschg, H. knapp, T.F. Meister, W. Wilhelm, J. Bock, M. Wurzer, K. Aufinger, H.D. Wohlmuth, A.L. Scholtz, Monolithic low Noise Amplifiers up to 10 GHz in silicon and SiGe bipolar technologies, Microwave Engineering Europe, March 2001, pp. 59–62. [4] T. Nakatani, J. Itoh, I. Imanishi, O. Ishikawa, A Wide Dynamic Range Switched-LNA in SiGe BiCMOS, Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers. 2001 IEEE, 2001, pp. 223–2326. [5] T. Nakatani, J. Itoh, I. Imanishi, O. Ishikawa, A Wide Dynamic Range Switched-LNA in SiGe BiCMOS, Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers. 2001 IEEE, 2001, pp. 223–2326. [6] D. Wang, K. Krishnamurthi, S. Gibson, J. Brunt, A 2.5 GHz low noise high linearity LNA/mixer IC in SiGe BiCMOS technology, Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers. 2001 IEEE, 2001, pp. 249–252. [7] K.L. Fong, High frequency analysis of linearity improvement technique of common emitter transconductance stage using a low frequency trap network, IEEE J. Solid State Circuits 35 (9) (2000) 1249–1252. [8] D. Watanabe, et al., IP3 Boost Circuitry For Highly Linear CDMA Low Noise Amplifier, in: Proceedings of the Asia Pacific Microwave Conference, December 2000, pp 213–214.