Ge dual channel epitaxy

Materials Science and Engineering B 124–125 (2005) 113–117

SiGe virtual substrates growth up to 50% Ge concentration for Si/Ge dual channel epitaxy Y. Bogumilowicz a,∗ , J.M. Hartmann b , N. Cherkashin c , A. Claverie c , G. Rolland b , T. Billon b a

b

STMicroelectronics, 850 rue Jean Monnet, 38921 Crolles Cedex, France CEA-DRT, LETI/D2NT & DPTS, CEA - GRE, 17 Avenue des Martyrs, 38054 Grenoble Cedex 9, France c nMAT Group, CEMES/CNRS, BP 4347, 31055 Toulouse Cedex, France

Abstract We have grown in reduced pressure–chemical vapor deposition (RP-CVD) SiGe virtual substrates with Ge concentrations ranging from 20 up to 50%. We have observed an increase of the surface rms roughness with the final Ge content of the virtual substrates. Cross sectional transmission electron microscopy images revealed an effective confinement of the misfit dislocations inside the graded buffer. The final Ge content of the virtual substrate has no impact on the field threading dislocations density, whereas an increase of the pile-up threading dislocations density occurred. We have then used Si0.49 Ge0.51 virtual substrates as templates for the growth of Si/Ge dual channels. Although some dislocations were observed, mainly in the silicon layer, we have demonstrated the growth feasibility of such highly mismatched heterostructures in RP-CVD. © 2005 Elsevier B.V. All rights reserved. Keywords: SiGe; Virtual substrates; Reduced pressure–chemical vapor deposition; Threading dislocations; Cross-hatch; Dual channel; Heterostructures

1. Introduction In order to meet the requirements of the ITRS roadmap [1], new materials have to be introduced for the channel of metal oxide semiconductor (MOS) transistors. The use of Si1−x Gex , through the tuning of the Ge content x (0 ≤ x ≤ 1) and the strain level (compressive or tensile) can drastically increase transistors performances [2]. The Ge content can easily be tuned when depositing the layer and is not an issue. The precise control of the strain level is more subtle. It can be achieved in several ways. One way is to use a SiGe virtual substrate [2], i.e. a thick SiGe layer with almost the same properties than the bulk ones but deposited on a different substrate, generally silicon to stay compatible with the actual MOS technology. Another way has been proposed the last few years, where the strain is induced in the channel by its surroundings: this approach is called process induced strain [4]. Although this approach has several advantages over the bulk bi-axial strain approach, it does not allow the same fine tuning and high strain levels achievable through the use of SiGe virtual substrates. As well, SiGe virtual substrates are needed to induce some bi-axial tensile strain in a silicon film for strained silicon-on-insulator (sSOI) fabrication [5–6]. Such

∗

Corresponding author. Tel.: +33 4 38 78 66 83; fax: +33 4 38 78 30 34. E-mail address: [email protected] (Y. Bogumilowicz).

0921-5107/$ – see front matter © 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2005.08.052

sSOI substrates, having a tensile-strained thin Si layer on top of a buried insulating layer, yield high-performance fully depleted transistors [7]. We have studied the growth of SiGe virtual substrates in reduced pressure–chemical vapor deposition with a Ge concentration ranging from 20 up to 50%. We have then used Si0.5 Ge0.5 virtual substrate as templates for the growth of Si/Ge dual channel heterostructures. Such a stack yields promising mobility gains for both electrons and holes [8]. 2. Experimental details We have used an Epi Centura reduced pressure–chemical vapor deposition tool from Applied Materials to grow all the samples of this study. The virtual substrates were deposited on 200 mm slightly p-type doped Si(0 0 1) substrates. Dichlorosilane (DCS) and germane diluted at 2% in hydrogen were used as the silicon and the germanium sources. Hydrogen, with a flow of a few tens of standard l/min, was used as the carrier gas. The growth pressure was fixed to 2666 Pa (20 Torr) for all samples. Details on the growth kinetics can be found in ref. [9]. Prior to any deposition, an “HF-last” wet cleaning was performed followed by an in-situ high temperature H2 bake in order to remove all the contaminants present on the wafer surface [10]. We used the graded buffer approach to obtain relaxed SiGe. It consists in, starting from the Si substrate: (i) a SiGe layer with a Ge concen-

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tration gradually increasing from a few % of Ge to the desired final Ge concentration, and (ii) a 1 ␮m thick constant composition SiGe layer. The grading rate we used (8% Ge ␮m−1 ) is low enough to ensure a good crystalline quality constant composition layer. It is however high enough so that the entire structure thickness is still reasonable (i.e. less than 10 ␮m). With this growth sequence, the top layer is expected to be almost totally relaxed, with threading dislocations densities orders of magnitude lower than if grown directly on silicon [11]. The Si/Ge dual channel heterostructures were grown on Si0.5 Ge0.5 virtual substrates whose crosshatch had been removed through some chemical mechanical polishing (CMP) of the surface. An “HF-last” wet cleaning was performed followed by an in-situ H2 bake whose thermal budget was minimized prior to layer deposition. The samples were characterized by X-ray diffraction (XRD) for the determination of the Ge content and the macroscopic degree of strain relaxation [3]. Atomic force microscopy (AFM) was used to study the surface cross-hatch such heterostructures tend to develop. Cross sectional transmission electron microscopy (XTEM) images were acquired to study the dislocations distribution. Finally, some chemical decorations of the surface have been performed in order to determine both the field and the pile-up threading dislocations densities. 3. Growth of SiGe virtual substrates with 20–50% Ge concentrations 3.1. Growth temperature choice The beneficial effects of high growth temperatures on the crystalline quality of SiGe virtual substrates has been demonstrated and discussed in many papers [12–14]. Unfortunately, the growth kinetics of SiGe layers in chemical vapor deposition strongly depend on the temperature. For example, the Ge incorporation in the growing film decreases (for given flows of dichlorosilane and germane) when the growth temperature increases, making it harder to reach high germanium concentrations at high temperatures. A far more important issue is that at high temperatures and high germane flows, the chemical reactions become to some extents too “efficient”. This leads to layers that are not spatially uniform over a wafer surface. Most of the precursors are indeed consumed on the chamber walls [13] and at the wafer edges and do not reach the wafer centre. Gas phase nucleation can also occur in those conditions [15]. To grow high Ge content VS, we have then to adopt a growth temperature which is high enough to yield the best crystalline quality VS possible, while still reaching high Ge contents and avoiding too fast deposition kinetics. For our set-up, this corresponds to a growth temperature of 850 ◦ C. This will be the temperature chosen to study the effects of the final Ge content on the VS structural properties. 3.2. Surface roughness SiGe virtual substrates develop a cross-hatched surface morphology that is related to buried defects and strain relaxation

Fig. 1. Surface rms roughness (left scale) and maximum amplitude of the crosshatch undulations (right scale) as a function of the final Ge concentration of the virtual substrates. Inserted in the graph are three 20 ␮m × 20 ␮m AFM images of the surfaces of 20, 35 and 50% SiGe virtual substrates.

processes (mainly dislocation glides) taking place during the growth [11,16]. We have monitored the evolution of the surface rms roughness and of the maximum amplitude of the cross-hatch undulations as a function of the Ge content of the virtual substrates. For that purpose, we have acquired numerous 20 ␮m × 20 ␮m AFM images whose metrics are summed up in Fig. 1. This figure displays as well images of the surfaces of 20, 35 and 50% Ge content SiGe VS. The images show a regular cross-hatch pattern, with an undulation wavelength that slightly increase from roughly 1 to 2 ␮m as the final Ge content increases. The curves of Fig. 1 show a clear trend: both the rms roughness and the maximum height of the cross-hatch undulations increase with the final Ge content of the VS. The value of the rms surface roughness shifts from 2.5 nm (maximum height = 20 nm) for Si0.80 Ge0.20 up to 10.1 nm (maximum height = 70 nm) for Si0.49 Ge0.51 virtual substrates. The parameters that might explain this trend are: (i) the adatoms surface diffusion length that increases with the Ge concentration [17], and (ii) the total growth time that increases as well with the Ge concentration. Both parameters will lead to a more marked cross-hatch topology. For high Ge content virtual substrates, the surface roughness can become an issue. Indeed, the rms and maximum height values are rather high (maximum height value = 6% of the thickness of the constant composition layer). Although chemical mechanical polishing (CMP) steps can efficiently be used to recover a smooth surface morphology [18–20], such high surface roughness can be detrimental to the glide of threading dislocations. This might induce the presence of many unwanted pile-up dislocations [21]. 3.3. Threading dislocations density Of particular concern for the structural quality of SiGe virtual substrates is their threading dislocations density, since they will strongly affect their electrical properties. Those dislocations can be distributed either uniformly, or bunched up in pile ups aligned along the [1 1 0] directions. The first category will be named field threading dislocations and the second one pile up threading dislocations. The results on those two densities are summed up

Y. Bogumilowicz et al. / Materials Science and Engineering B 124–125 (2005) 113–117

Fig. 2. Field and pile-up threading dislocations densities as a function of the final Ge concentration of the virtual substrates. The left scale refers to field and pile-up threading dislocations, whereas the right scale is suitable for pile-up threading dislocations only.

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centration on virtual substrates threading dislocations density by Fitzgerald et al. showed, contrary to our results, an increase of that density [22]. On the other hand, models describing the threading dislocations density in virtual substrates, notably by Fitzgerald et al. [23], predict that this quantity should be independent of the final Ge content. Our results are clearly in line with such models. The trend for the pile up threading dislocations is not the same. Their density increases with the final Ge concentration. The surface cross-hatch is expected to play a role in the bunching of dislocations [21]. Since the surface roughness increases in the Ge concentration range probed, this is the most probable explanation to that increase. 4. The growth of Si/Ge dual canal on Si0.5 Ge0.5 VS 4.1. Growth details

in Fig. 2. The left scale correspond to a surface density and can be used for both categories of dislocations. The right scale corresponds to a linear density and can only be used for the pile up threading dislocations. To move from one scale to the other for the pile up threading dislocations, we have counted at high magnification the number of threading dislocation bunched in pile ups per unit length. Fig. 2 shows that increasing the final Ge concentration has no impact on the field threading dislocations density. It stays around 4.105 cm−2 over the whole studied range. A previous experimental study on the effect of the final germanium con-

SiGe virtual substrates can be used as templates for strained layer growth. A recent review on the numerous interesting stacks can be found in ref. [24]. Of particular interest in terms of mobility gains for both electrons and holes is the tensily strained Si/compressively strained Ge dual channel grown on top of a Si0.5 Ge0.5 virtual substrate. In that heterostructure, the lattice mismatch between the Si or the Ge layers and the virtual substrate that dictates the in-plane lattice parameter is high, around 2%. This makes the growth of flat, thick enough layers very challenging. Indeed, a mismatch of 2% is normally

Fig. 3. 5 ␮m × 5 ␮m AFM images of: (a) a Si0.5 Ge0.5 virtual substrate after some polishing of the surface then an HF-last wet cleaning and finally a H2 bake. The (b) image corresponds to the same sample and sequence but after the deposition of a nominally 8 nm thick Ge layer. The (c) image shows the same stack than in (b) but after the deposition of nominally 5 nm of silicon, i.e. it shows the surface of the whole dual channel heterostructure.

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associated with a Stransky-Krastanov growth mode for Ge. To avoid it, growth temperatures have to be severely decreased. In our case, the Ge layer growth was conducted at 350 ◦ C (growth rate = 2.8 nm min−1 ). The use of such a low growth temperature was possible because germane requires very low energy amounts to decompose into its individual constituents. We then used dichlorosilane to grow the silicon layer. Although DCS requires higher temperatures to decompose than for example silane, we decided to use such a gaseous precursor for silicon in order to be able in the near future to grow the dual channels selectively versus SiO2 . We first let the DCS flow at the temperature at which the germanium layer was deposited, i.e. 350 ◦ C for a few minutes, to cap the Ge layer with a few monolayers of silicon. Then, we increased the growth temperature (ramping-up rate: 1 ◦ C s−1 ) up to 650 ◦ C, at which the rest of the silicon layer was deposited (growth rate = 0.6 nm min−1 ). This growth strategy is similar to the one proposed by Lee et al. [25]. They however used ultra high vacuum-CVD instead of RP-CVD in our case, with much longer growth times due to very slow temperature changes in their case. 4.2. Results Fig. 3 shows the evolution of the surface morphology of a Si0.5 Ge0.5 VS after: (a) an HF-last wet cleaning followed by an H2 bake, (b) the Ge layer deposition, and (c) the whole dual channel deposition. A very light crosshatch texture is visible on those images. The surface rms roughness is 0.17 nm (Z range = Z max − Z min = 1.66 nm) for the first image, 0.24 nm (Z range = 1.99 nm) for the second and 0.18 nm (Z range = 1.34 nm) for the last one. It means that the surface gets a little rougher after the germanium deposition. However, silicon smoothens it again, yielding a value similar to the one of the virtual substrate. Although those surface rms roughness are higher than the ones of silicon wafers (0.17 nm versus less than 0.1 nm for a silicon wafer), the layers are smooth and the growth mode is not of the Stransky-Krastanov type but rather of the Van der Merwe one, i.e. planar. Fig. 4 shows a XTEM image of the above mentioned t-Si/cGe heterostructure. On that image, we see that the layers are flat and that the interfaces are sharp. The Ge layer thickness is 8.5 nm and the Si layer thickness is 5.1 nm. (0 0 1) PV TEM images (not

shown) demonstrated that no misfit dislocations were present at any interfaces of the stack. Instead, dislocation loops pinned at the Ge/Si0.49 Ge0.51 interface were observed. As well, {1 1 1} half-loops originated from the Si/Ge interface and threading to the surface were evidenced. A more detailed survey of the crystalline defects present in these layers can be found in [26]. Both types of defects degrade the Si layer integrity, meaning that the individual layer thicknesses and growth conditions still need some additional tuning. Anyway, the feasibility of such a heterostructure has been demonstrated in RP-CVD. 5. Conclusion We have grown SiGe virtual substrates in reduced pressure–chemical vapour deposition. Although high growth temperatures are strongly advised to obtain the best structural properties, a compromise has to be found when growing high Ge content virtual substrates. This is to avoid too fast deposition kinetics and the problems associated with. For our set up, this compromise temperature is 850 ◦ C. SiGe virtual substrates with Ge concentrations ranging from 20% up to 50% were studied. We observed an increase in the surface rms roughness when the final Ge content of the virtual substrates increased (from 2.5 nm up to 10.1 nm). The field threading dislocations density did not depend on the final Ge content of the virtual substrates. Their density stayed around 4.105 cm−2 . On the other hand, the pile-up threading dislocations density increased with the final Ge content of the virtual substrates (from 105 up to 2.105 cm−2 ). This is mostly due to the interactions with the surface cross-hatch. We have then used Si0.5 Ge0.5 virtual substrates to growth tSi/c-Ge dual channels in RP-CVD. The AFM images after the different steps showed slightly crosshatched surfaces with rms roughness around 0.2 nm. The TEM image showed flat layers with sharp interfaces. Some defects were observed, mainly in the silicon layer, meaning that these structures still need to be optimized. Anyway, we demonstrated the feasibility of the growth of t-Si/c-Ge dual channels in RP-CVD. Acknowledgements This work, carried out inside the NaNoTec and the Silicon Technology Platform Departments of LETI, CEA-Grenoble, was supported by the Alliance (STMicroelectronics, Philips and Freescale Semiconductors) and by the European Union NANOCMOS Integrated Project. The authors would like to express their thanks to S. Rousseau, G. Rabill´e and M. Burdin for their help in operating and maintaining the Epi Centura and for the XRD experiments, respectively. References

Fig. 4. XTEM image of the dual channel. The thicknesses extracted from this picture are 8.5 nm for the c-Ge layer and 5.1 nm for the t-Si layer.

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