- Email: [email protected]
D converter applications
i~ I
Microelectronics Journal, 25 (1994) 253-277
"t
Sigma-delta modulators for high-resolution and wide-band A/D converter applications V.F. Dias 1, V. Liberali 2 and G. Palmisano 3 IINESC, R. Alves Redol 9-3°A, 1000 Lisbon, Portugal 2UniversitY1di Pavia, V. Abbiategrasso209, 27100 Pavia, Italy 3Universit3 di Catania, DEES, V. A. Doria 6, Catania, Italy
High-resolution and wide-band sigma-delta (HA) A/D converters are based on high-order single-stage or cascade modulators and, more recently, also on multibit topologies. This paper reports a comparative study of the most promising modulator topologies available today, paying special attention to a new class of cascade multibit topologies that we have developed which do not require multibit D/A converters. Comparisons are made in terms of design and implementation complexity, sensitivityto amplifier dcgain and matching between components, thermal noise, amplifier slew-rate and bandwidth, and D/A converter linearity. Design examples are given showing that 12-bit, 14-bit and 16-bit HA A/D converters with 4MHz, 1 MHz and 150 kHz output rates respectively are possible using state-of-the-art silicon technologies. 1. Introduction
he three basic concepts behind sigma-delta (HA) A/D converters are oversampling and noise-shaping, on the one hand, and digital decimation on the other. Signals are first oversampled and coarsely quantized inside a loop
T
0026-2692/94/$7.00 © 1994 Elsevier Science Ltd
(modulator), and then lowpass filtered and decimated down to the Nyquist rate (decimator). The advantages are known: possibility o f efficiently trading speed for resolution, and relaxed accuracy and matching requirements imposed on the analogue components. This is in line with the trend towards sub-micron technologies optimized for digital circuitry. Figure 1 shows the two basic modulator architectures available today: single-stage (Fig. la), and cascade (Fig. lb). Single-stage modulators have the same structure as a filter, and have one single quantizer and a D/A converter (see Fig. 2) [1-3]. The output signal in a single-stage modulator is given by Y ( z ) = X ( z ) . STF(z) + Q ( z ) . NTF(z)
(1)
where X ( z ) is the input, Q(z) is the quantization noise, and STF(z) and NTF(z) are the signal and
253
i
V.F. Dias et al./CA modulators for A/D converters
g 1¥1(z)
Ql(Z) h2Fl(Z) Q(z)
Vz)
g2Y2(z)
%(z) ' F2(z)
A/D
•
t
I hk
g kYk(z)
(a)
(b)
Fig. 1 Architectures of sigma-delta modulators: (a) single-stageand (b) cascade. the noise transfer functions, respectively. Equation (1) assumes the quantization noise is additive, uncorrelated with the input signal and white, having a power which depends on the quantization step 2A/2 N, where A and N are the quantizer input dynamic range and resolution, respectively. Usually, NTF(z) is highpass, either maximally-flat Butterworth or Chebyshev, or inverse-Chebyshev or elliptic, and the order L is usually made 3, 4 or 5 and rarely larger. The signal transfer function STF(z) is lowpass, with passband edge B0.
swing optimization. Filters Hi(z) are low-order F I R and allow the noise sources associated with the first ( k - 1 ) NSBs in the cascade to be cancelled. The remaining noise source, Qk(z), is highpass shaped by Hk(z). Cascade modulators implement noise transfer functions that are optimal highpass, i.e. NTF(z) = (1 - z-l) L, and have allpass signal transfer functions, i.e. STF(z) = z -p. As far as the modulator order is concerned, most applications use L = 3 because, for larger values o f L, c o m p o n e n t matching and accuracy becomes a critical aspect.
Figure lb shows the cascade architecture [4-11]. Cascade modulators are built up with low-order noise-shaping blocks (NSBi), whose transfer function can be zero-order multibit, first-order where N T F i ( z ) = ( 1 - z -1) and second-order where N T F i ( z ) = (1 - z - l ) 2 [8]. Each NSB in the cascade supplies to the following stage a signal, Fi(z), that can be scaled (hi) for signal
The in-band noise power in a sigma-delta modulator is given by the integral of I Q(f)12. I N T F ( f ) ]2 over the signal band, B0. For those cases where NTF(z) = (1 - z-l) L, this integral can be approximated by
254
4A 2 rc2L l 1 PQ ~ 3 2L 4- 1 " 2 2N " M 2L 4- 1
(2)
Microelectronics Journal, t/ol. 25
2. Single-stage modulator networks
where M is the oversampling ratio. Singlestage modulators have N T F ( z ) ¢ (1--z-7)L; this is because the noise transfer function is appropriately modified by adding a denominator function to guarantee stability. Stabilization of single-stage modulators leads to increased amounts of noise power respective to eq. (2)[11.
2.1 Single-bit Figure 2 shows the two most common singlestage modulator topologies reported in the literature, Type 1 (a) and Type 2 (b). We shall assume that I(z)= z - 1 / ( 1 - z -1) and that the quantizer and D/A converter are delayless.
Type 1 modulators have two sets of design parameters: coefficients Ai converging at the quantizer input node, and coefficients Bi converging at the modulator input node. From the point of view of the noise transfer function implemented, an equivalent topology results if the feedforward paths (Ai) are replaced by feedback branches subtracting from each integrator input the D/A converter output signal; this alternative has advantages in switched-capacitor implementations. The signal and the noise transfer function in Type 1 modulators are given by
Equation (2) indicates three degrees of freedom in the design of a modulator, namely the oversampling factor, M, the noise-shaping order, L, and the quantizer resolution, N. The choice of a suitable set of parameters is a key factor in sigmadelta design because technological constraints such as speed, thermal noise, matching and accuracy, on the one hand, and design complexity on the other have to be carefully considered. This paper reports a detailed study we have made of the most promising single-stage and cascade modulators available today. The paper focuses on the several trade-offs involved in the design, and explores the limits imposed on (2) by the technology. A main conclusion is that cascade pseudo-multibit modulators have advantages with respect to other topologies, and that 12-bit at 4MHz, 14-bit at 1MHz and 16-bit at 150kHz A/D converters are feasible at the present state-of-the-art.
Ao z-1 (1 -- Z-l) L L
+ y~Aiz-i(1-z-1) L-1 STF(z) =
,=1 (1 +A0z-1) (1 c
" ' "
A B I • A 22
(a)
~
(3/
+ Z (Ai ni) z-i (1 Z-l) L-i -
-
-
i=1
\c,
X(z),,-,,
z-') L
-
\c~
\c~,
\ c~
Bk
X(z)o Y(z)
[~~
=
Y(z)
(b)
Fig. 2. Topologiesof single-stagesigma-deltamodulators:(a) Type 1; (b) Type 2.
255
V.F. Dias et al./ A modulators for A/D converters
and
(1 - z - l ) L L
-- ~ - - ~ B , z - i ( 1 - z NTF(z) =
l)L-i
i= 1 (1 + A o z -1)(1 - z -1)L
(4)
L
+ ~7_~(Ai-Bi)z-'(1
-z
1)L i
i=1
respectively. The alternatives for synthesizing NTF(z) in (4) are two: one for B i = 0 and another for 8 i -7k O. In the former case, the numerator in (4) becomes an L-order differentiator, allowing maximally-flat Butterworth or Chebyshev nmse transfer functions to be synthesized. Poles are defined by A i coefficients, and are synthesized according to the stability condition established by Lee et al. [1]. Stability is achieved by decreasing the gain of NTF(z) over the high-frequency range, a decrease that results in increased amounts of in-band noise power respective to the optimal shaping case given by NTF(z) = (1 - z-l) L. The second design alternative assumes some or all B i 7/= O. This provides designers with the possibility for placing zeroes anywhere in the signal band, allowing inverse-Chebyshev and optimal elliptic filtering functions to be synthesized. Gains in resolution as large as 2-bit are possible with these alternative designs. In both designs, B i = 0 for all i and B i :fi 0 for some or all i, STF(z) is uniquely determined by t h e A i and Bi coefficients and is neither maximally-flat, equiripple or linear phase. This is one of the aspects of which the Type 2 topoplogy described next can take advantage. Type 2 topologies have three sets of coefficients, A i , B i and Ci (see Fig. 2b). In this case, Bi coefficients define second-order resonators from which pairs of transmission zeroes are namely
256
obtained and placed in the signal band rather than dc. T h e poles in NTF(z) are almost defined by the Ai coefficients and are again synthesized according to the stability condition referred to above. Finally, Ci coefficients have no effect on the noise transfer function implemented. This gives the designer more flexibility in the synthesis of the signal transfer function, STF(z), and allows better control over the amount of signal at the output of intermediate integrators. Type 2 and Type 1 topologies lead to different signal transfer functions. Figure 3 compares simulated power spectral density plots of the signal at the output o f Type 1 and Type 2 modulators. The Type 1 m o d u lator has been made maximally-flat Butterworth (T1-MF), while the Type 2 uses an optimal placement of one pair of transmission zeroes (T2-1Z). In the former case, all zeroes coincide at dc and the noise is lower near zero. In the latter case, a pair of complex transmission zeroes has been placed around 6.5 kHz. This results in a reduction in the noise level at that frequency. Figure 4 compares the simulated SNR, behaviour of three different designs of a fourth-order modulator (the input signal is sinusoidal, of frequency f < B0, and M = 64). The designs considered are Type 1 maximally-flat (T1-MF) and elliptic (T1-EL), and Type 2 with optimal placement o f one pair o f transmission zeroes (T2-1Z). Stability in high-order single-bit modulators imposes I N T F ( f ) ] < 6dB in the highfrequency range, provided no input signals larger than ~ - 6 d B are fed into the circuit (dB respective to A) [1]. In practical implementations, clipping circuits are used to limit the signal swing in the integrators, as well as overload detectors to control undesired unstable states [3]. Adams et al. [3] report a fifth-order modulator with 105 dB (18-bit) dynamic range in the digital audio band. This is considered an upper b o u n d limit to the HA technique in audio applications.
Microelectronics Journal, Vol. 25
0
PSD
(v 2/Hz)
i I I
-20 o o o i -40
- b u
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
i
,. . . . . . . . . . . . . . . . )
,. . . . . . . . . . . . . . . . =
l = i o
l i ) i
~.
_o,-,
U~
. . . . . . . . . . . . . . .
,. . . . . . . . . . . . . . .
,. . . . . . . . . . . . . . .
j
I I I I
I I I I
,
,
,
,
t i
i t
'
r
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-120
. . . . . . . . . . . . . .
-140
. . . . . . . . . . . . . .
-160
.
-180
J ~
.
.
.
Ii! .
.
.
.
.
.
.
i
.
.
.
.
.
.
I
~..
*
.
.
.
I. . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
i
I
I I
I I
I
. . . . . . . . .
4.00e+03
~I,
.J ^ at,, ~lhlJ~filllil,l~tlll/lfllv"i
I I i l
Ii
~
'~•
'
i. . . . . . . . . . . . . . .
.
|
-200
'',
. . . . . . . . . . . . . . . .
"1 . . . . . . . . . . . . .
T1-MF
'
n-lz
a
. . . . . . . . . . . . . . .
I I I I
" . . . . . . . . . . . . . . .
j . . . . . . . . . . . . . . . .
I I I I
i t
-I00
=
I
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
i .
.
.
.
.
.
.
.
.
.
J
.
i
. . . . . . . . .
I
,,'
1 i i
.
.
.
. . . . . . . . . . . . . . . .
i .
.
.
.
.
.
.
I
i I
8.00e+03
l,
.
J
.J . . . . . . . . . . . . . . .
.
'WI'
.
I I
. . . . . . . . .
1.20e+04
I
.........
1.60e+04
2.00e+04 Frequency (Hz)
Fig. 3. Spectra o f the signal at the o u t p u t o f fourth-order single-stage modulators.
2.2 Multibit topologies
Instability in high-order single-bit modulators is due to an insufficient number of bits in the quantizer and D/A converter. Analytical and simulation results agree that high-order singlestage modulators with optimal shaping can still be implemented provided enough bits are used in the quantizer and D/A converter [12]. It has been found that in idle noise conditions the relationship between the shaping order and the number of transition levels required is (2 L -
1).
One principal drawback of single-stage multibit networks has been the required D/A converter
linearity. This is because the signal at the D/A converter output is not shaped, and non-linearity effects appear unchanged at the modulator output. Several solutions have been proposed to overcome this drawback: component trimming, digital error correction and dynamic matching [13]. The first two solutions are costly, while the latter one has proved to be inadequate for highresolution applications because harmonics are simply traded for white noise, (1/M)-th of which falls again inside the signal band. This is a severe limitation from the point of view of the linearity required from the D/A. Carley [13] reports a D/A converter that achieves 16-bit dynamic range and - 9 4 dB total-harmonic distortion.
257
V.F. Dias et al./ A modulators for A/D converters
Ii0
SNR (dB)
'i
'l
T
]
'l
'I
i I
t t
f t
I i
t l I
t t t
a i
i l
,
,
t
I g I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i00
i l
90
. . . . .
i
. . . . . .
.....
. . . i 1 . . . . . . . . . . . . . .
r ...... .
70
.
i
60
,
I
I I
I I
I I
. I ,. . . . . . .
. I r .
~.
.
I . . . . .
i
4
I
.a
.
. . . . .
~
I- . o i
.
.
.
.
.
. l
.
.
.
-/-'~V" .
.
/__ . .
.
I
.
/
" / .
.
T
"/I'--~ ~7f}'i
I
~
', i .
I. . . .~/~/D,./I,L ..
I I
, "1---
.
t i /
t.
i I
I I I
T1-EL 1
J . . . . . . .
. . . . .
.
I I I
I
i
.
.
. . . . . .
.
i I I
I
.
- - - ~
, M=64
k . . . . . .
.
I I I
. o
,
I. . . . . . .
. . . . .
.
I i i
i i
. . . . .
J . . . . . . . . . . . . . . I I
80
l i
[
.
I , I
.
.
.
.
.
.
,
,
I I I
I I I
', I
, t
I
.
T2-IZ'-I. 50
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
J
40
. . . . .
ii" .
.
.
.
.
.
.
.
.
.
.
m r i
30
I I
20
J i
. . . . . . .
I
-i00
.
.
'. . . . . . .
T . . . . . . i i o o
I.
t J i I
I i i I L. . . . . . .
i I I I L . . . . . .
.
-90
-80
.
.
.
.
'. . . . . . .
.
.
.
.
• . . . . . .
I I I I • . . . . . . I I i I
.
L . . . . . .
"I . . . . . . . l t l I I I I I a . . . . . . .
.
J . . . . . . .
~ i
-70
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
~"TI-MF' .
i i
0 -ii0
.
I i I I
I I
jy
I0
. . . . . . .
.
.
-60
-50
-40
i. . . . . . . i i i I
I" . . . . . . I i I I
I"
I I I I I. . . . . . . I I I I
I I I i I. . . . . . . I I I I i. . . . . . . . . i . . . . . .
I I
I i
-30
-20
-I0
0
Input (dB) Fig. 4. Signal-to-noise ratio in fourth-order single-stage modulators.
More recently, Leung and Sutarja [12] proposed a set of alternative dynamic matching techniques designated as clocked and individual-level averaging. In clocked averaging the unit-elements of a parallel D/A converter are grouped and permuted at different clock rates (sub-multiples of the sampling frequency). The visible effect is modulation of harmonics, being translated to frequencies around sub-multiples of the sampling frequency. This technique has several drawbacks: it requires a minimum oversampling and permuting clock-rate, and it is inherently inefficient from the anti-alias filtering point of view. Indeed, with this algorithm, out-of-band tones are modulated exactly
258
as harmonics of the signal and are resulting, in certain conditions, in spurious signals inside the signal band. In the second algorithm, individual-level averaging, the D/A converter remembers the different D/A unit-element combinations used to synthesize a given digital code. Since the errors associated with each code are averaged, harmonic distortion is converted into white noise, which is highpass shaped. However, although interesting for wide-band low oversampling ratio applications, these techniques can lead to quite complex hardware implementations. This fact makes them less attractive with respect to other muhibit topologies, described below.
Microelectronics Journal, Vol. 25
3. Cascade modulator networks
In a recent w o r k we proposed a systematic approach to the design of cascade modulators [8] (Fig. lb). There we assume cascade modulators are built up from three basic noise-shaping blocks (Fig. 5), namely (a) zero-order multibit, (b) first-order single-bit and (c)second-order single-bit. Each block has two input signals, X ( z ) and Q(z), and two output signals, Y ( z ) and F(z) (Fig. 6), and is modelled with a set of four
X(z)
Y (z)
Q(z)
F (z)
X(z)~
Fig. 6. Modelling noise-shaping blocks.
Y(z)
transfer functions. These are S(z) and N ( z ) for the signal and noise transfer functions for the output, Y(z), and Fs(z) and FN(z) for their equivalent for the feedforward signal, F(z). Table 1 summarizes the whole set o f transfer functions of zero-order, first-order and second-order NSBs.
I F(z)
Type-A (a)
X(z),
Assume each of the noise-shaping blocks in Fig. lb is replaced by the corresponding model given in Fig. 6. T h e signal and noise transfer functions are then given by
Y(z)
TypicalDesigns (1)k=1
STF(z) = $1 (z) "gl • H~ (z)
~__!
(2)k=]/2
+ F s l ( z ) " h2 " S2(z) "g2 " H2(z) + . . .
F(z)
Type-A
Type-B
Co)
X(z)=
k la ~ klb
k2a k2b
~
Y(z)
and NTFi(z) = gi " N i ( z ) " Hi(z) TypicalDesigaxs (1)k*=1/2 (2) kla=klb=l/4 k2a=l,k2b=l/2
% TypeA
+ FNi(Z)" hi + 1 "Si + 1 (Z) "gi + I" Hi + 1(z)
TypeB
(c) Fig. 5. Noise-shaping blocks (NSB) used in cascade modulators: (a) zero-order N-bit; (b) first-order; (c) second order.
259
V.F. Dias et al./ A modulators for A/D converters
TABLE 1 Transfer functions of zero-order, first-order and second-order noise-shaping blocks NSB order
Feed type
S(z)
N(z)
Fs(z)
zero (0) first (F) second
A A B A
1 z 1 z ' z 2
1 (1 z -1) (1 - z -1) (1 - z 1)2
1 z 1 0 z - 9-
(S)
B
z 2
(1 -
respectively• Since L - o r d e r modulation means that S T F ( z ) = z -p, N T F i ( z ) = 0 for i = l , . . . , k- 1 and NTFk(z) = g k • (1 - z - l ) L, the following digital filters result: FNi(Z) Hi(z ) = _ _ _ Ni(z)
• (hi+l
"
Si+l(z)
"gi+l
z-l) 2
FN(z) ! m z
-1
-1 z 1 ( - 2 + z i) -1
0
3.1 Single-bit m o d u l a t o r s Figure 7 shows the two most promising cascade single-bit modulators available today [5, 9-11]• B o t h consist o f the cascade o f a second-order (S) and a first-order (F) modulator, and will be referred to as SAF and SBF (subscripts A and B stand for the type o f the first modulator). Table 2 summarizes the corresponding transfer functions
• Hi+ 1 (z) + hi+ 1 " Fsi+ 1 ( z ) . hi+ 2
xI
• Si+2(z) "gi+2 " H i + 2 ( z ) + . . .
z
)
'
-
-
h2 ~ • Sk(z)'gk
"Hk(z)
?
~
~
Y(z)
(7)
for the first (k - 1) filters o f the cascade, and (a)
(1 - z - l ) L Ht,(z) --
Nk(z)
(8) X
Iz) a
for the last one. In practical implementations, input scaling factors hi are set by the designer on the basis o f voltage swing constraints in the integrators. O n e possible way o f designing H i ( z ) filters and gi coefficients is as follows: evaluate H i ( z ) assuming hi = g i ~ - 1 ; then, calculate coefficients gi according to the following nile:
Y(z)
(b) i
gi=Hhj-' j= 1 260
(9)
Fig. 7. Cascade second-order first-order modulators: (a) S^F and (b) SBF.
Microelectronics Journal, Vol. 25
TABLE 2 Digitalfilters required to build third-order cascade modulators (S*F and S*FN topologies) Topology
H1(z)
S^F St3F
z 2(2-z
1)
z -1
H2(z)
Signal
Noise
gi
(1 - z - l ) 2 (1 - z - l ) 2
z 3X(z) z 3 X(z)
( g 2 ) ( 1 - z 1)3Q2(z ) (g2)(l - z - i ) 3 Q2(z)
gl = 1 g2 = 1/h2
Hi(z ) and scaling factors gi. T h e output signal in
1/8, Q2(z) becomes amplified and the m a x i m u m achievable resolution is limited to
S*F modulators is given by (1 - z - l ) 3
Y ( z ) = X ( Z ) " Z -3 "Jog2" Q 2 ( z ) .
(10)
RQ ~ 3.5- log2(M ) - log2(g2) - 3.5
This means a gain of 7/2-bit per octave of M, and a net loss of 1-bit per octave of the scaling factor, g2. Figure 8 shows the simulated SNlk of
where Q2(z) is the noise source of the second NSB and g2 is the corresponding scaling factor. Because h2 is smaller than unity, usually 1/4 or
SNR (dB)
I u I I
ii0 ZOO
.
u I I i
. 1.
.
.
I I I I
.; . .. . . . .. . .
I I I I
I ! I O .l . . . . . . . o !
90
. - L
80
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . a i
,
- - r
.
..
I I I n u. . . . . . .
. . . . . .
I
. . . . . .
,
.
. . .. . ..
. . A. .
f I O I a. . . . . . . i !
.
. . . .i. .
I i I I /. . . . . . .
"I . . . . . . .
i I
a
..
.
..
. ..=. . . . .. ... . . . .
I I I I £ . . . . . . i !
,
! I I o l
. . . . . . .
,~.=~
I I u I .o . . . I I I o o. . . . . u u
o
o 8-
,
I
i I I I
e- . . . . . .
r
o I I o
I I I I
o ~.
o
. . . . . .
I / ~ ~ _ _ / _ . . . . . .
% ./t
I I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- - -
-i I . . . . . .
--
I I
.
.
.
.
.
.
.
.
.
I
:
'/v ,,
L
I
I I
~u
I
?
'
sL. 50
..
I I I I
(- . . . . . . . . . . . . . . . . . . . . . . . .
,
o
..~
u n I i
I o n o
I I
,
.
I I i I
,
I o u I
I o
60
I I I I
,
I I I I
70
. .J . . .
(11)
.
.
.
.
'I M=32 ,
40
"
. . . .
30
20
. . . .
re . . . . . .
~l . . . . . .
o i
i i
Ia I I !
- - - , 4 I I o
1. .
"--
-1--i o i
~I
.
.
.
.
.
'
sF
"--
A
.
J _ .
--k
. . . . . .
i. . . . . . .
r" . . . . . .
:
:
:
,
,
,
I
t
I. . . . . . .
~. . . . . . .
l
'
,
A. . . . . . .
1' . . . . . .
I l
i i
I .
"I . . . . . . .
I i
.I . . . . . . .
i. . . . . . .
' I I I
n I n
I0
-Ii0
-I00
-90
-80
-70
-60
-50
-40
-30
-20
-i0
0
Input (dB) Fig. 8. Signal-to-noise ratio in S*F modulators: g2 =
l/h2
= 2 andg2 = h2 = 1 in SAF and SBF respectively.
261
V.F. Dias et al./ A modulators for A/D converters
two S*F modulators for oversampling ratios M = 32 and M = 64. T h e SBF modulator is not scaled (g2 = h2 = 1), while the S^F one assumes g2 = 1/h2 = 2. Ribner et al. [14] report a thirdorder cascade S , F modulator that achieves 15.5bit and 15-bit at sample rates o f 2 4 k H z and 80 kHz respectively. Y(z)
3.2 Multibit modulators
As was first noticed by Brandt and Wooley [11], cascade modulators have the peculiarity that some of the D/A.converters see a path to the output that is highpass; these NSBs can thus be multibit without regard for non-linear effects. Candidates for multibit topologies are the ones in Fig. 7 where the quantizer and the D/A converter in the second NSB are multibit rather than single-bit [11]. The same digital filters of Table 2 are valid for multibit topologies, but in this case the m a x i m u m achievable resolution is given by RQ = 3.5. log2(M ) + (N - 1) - 3.5 - log2(g2) (12) where N is the quantizer and D/A converter resolution. Brandt and Wooley [11] report a 12bit at 2 M H z rate ( M = 24) using an S^F3 topology (subscript '3' stands for the n u m b e r of bits o f the second modulator). This illustrates the potential the P,A technique has for achieving m e d i u m resolution A/D converters at relatively high sampling rates. 3.3 Pseudo-multibit modulators
Cascade pseudo-multibit topologies have one key advantage over their multibit counterparts: they avoid the use of multibit D/A converters in the feedback loop [15]. Figure 9 shows one possible third-order cascade pseudo-multibit modulator. This modulator is built up from three NSBs, one Type B secondorder (SB), another Type B first-order (FB), and
262
Fig. 9. Cascade third-order pseudo-multibit modulator (SBFBO3).
a final zero-order multibit (ON). NSB1 and NSB2 together give the noise-shaping implemented, while NSB3 alone is responsible for the quantization noise power handled. T h e dashed line indicates the separation between these two parts, indicating also that they can be implemented in different chips or dies without concern for noise or distortion. Pseudo-multibit modulators are designed in exactly the same way as single-bit and multibit modulators, i.e. by means of eqs. (7) to (9). Table 3 summarizes the filtering functions Hi(z) and the corresponding scaling factors for thirdorder topologies. T h e output signal is given by Y ( z ) = X ( z ) . z -3 +g3" Q3(z) - (1 - z-l) 3
(13)
while eq. (12) above, with g2 replaced by g3, gives the m a x i m u m achievable resolution in bits. Digital filter H3(z) is a third-order differentiator, and is alone responsible for the shaping implemented over Q3(z); this is w h y disturbances that enter or are generated internally in the multibit quantizer can be ignored from noise calculations. Figure 10 shows simulation results comparing the S N R behaviour of S^F, SAF 3 and SBFBO3
Microelectronics Journal, Vol. 25
TABLE 3 Digital filters required to build third-order cascade pseudo-multibit modulators (S*F*ON topology) Topology
Hi(z)
H2(z)
H3(z)
Signal
Noise/Q3 (z)
SAFAO N SAFBON SBFAON SBFBi~JN
z - 2 ( 2 -- Z 1) Z-2(2 -- Z - i ) Z -1 Z -1
z - l ( 1 -- z - l ) 2 (1 -- Z - I ) 2 z-l(1 --z-l) 2 (1 -- z - l ) 2
(1 (1 (1 (1
z-3X(z) z-3X(z) z-3X(z)
(g3)( 1 (g3)(1 (g3)(l (g3)(1
modulators.
The
-- z - l ) 3 -- Z 1)3 --z-l) 3 -- z - l ) 3
SBFB(~3 m o d u l a t o r is not
I I
II0
I I
.
100
. . . .
90
o !
.
.
. . . .
. I
I
e
o
I
I I
I |
I I
I I
!
I.
,
,
,
,
,
,
,
,
t L . . . . . .
I I . . . . . . ! I I I
I
! I. . . . . . . I I I !
I L . . . . . . ! ! ! I
I I . . . . . . ! I I I
|
I I. . . . . . .
r . . . . . . 1 I i i r . . . . . . I I
T . . . . . . I ! I I
. . . . . .
I
.
.
. . . . . . .
I
'
I
. . . . . .
'I
I
i. . . . . . . I I ! i r
. . . . . .
I i
'
. . . . . . . . . . . . . . . . . . .
', S g I : B O 3
.......
,'-#
I I. . . . . .
.
I ~ _ _ _~
.
1
I I I
. . . . . .
~
.
.
.
.
.
.
.
_~
.
I
-ii0
1
.
.
I i
.
.
.
.
.
.
.
.
I. . . . . . .
i" . . . . . .
I
I I
~
-I
.
.
! I
I
r ! I I I
.
.
~,~
' .
.
.
.
.
.
,
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4
r
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
*
. . . . . .
"1 . . . . . . .
,.
.
.
.
.
.
.
.
I I
I I
I I I. . . . . . . I I
I
I
:
.
.
.
.
.
.
.
.
.
.
I I
i- . . . . . .
~
I I
I I
I I . . . . . .
•
. . . . . .
-I . . . . . . .
I I
)
I
I
I. . . . . . . I
I. . . . . . . I
I . . . . . . i
.
.
.
J . . . . . . . I
.
.
.
.
.
.
.
.
.
.
i
I
|
t
)
I
I
I
I
I
I
I
I
. . . . . .
I
~ . . . . . . .
.
.
.
i- . . . . . .
.
.
+
.
.
. . . . . .
I I I
I. . . . . . . . . . . . . . . . . . . I
t I
I
.
I
I
) I
,. . . . . . .
,. . . . . . .
T . . . . . .
T
i
I
I
I
I
!
I
)
I I
I I
I I I
I I I
I I I
I I I
I I 1
I I I
I I I
-90
-80
-70
-60
-50
-40
-30
]00
. . . . . . .
I
.
.
SAF3
. . . . . .
I I
.i . . . . . . .
.
'
*
J _ _ _
' .
I
I
.
. . . .
!
.
I
.
T
I t
.
I
.
T - I I i I
I
.
I
.
. . . . . .
'
I
,.
I
,
~
I
i'" I I
I
i
]U
.
"l . . . . . .
I
:y .
i
I
I I .
,
I
I I
.
~
I
I I .
I
I L I t
II
", .
I I
I
',
,.
¢
, ' . . . . .
J . . . . . . . I I I I
T
'I .
--'~"
I
[.
gl = 1
g2 = 1/h2 g3 = 1/h2h3
.
-I . . . . . . .
t t
. . . = ~
.
i. . . . . . . I i ! i
! I
50
20
I I
I
. . . . . . . . . . . . . . . . . .
30
I |
I
r . . . . . . I I
......
i I
I I
J . . . . . . . I I I I
3 3 3 3
.
I I
60
40
.
|
r
. . . .
I I
.
I
I I I I
70
I I
.
I I
.
80
I I
.
- z-l) - z-l) -z-l) - z-I)
Figure 11 summarizes the state-of-the-art in IC implementations of high-order single-stage and cascade modulators. The range of application of the sigma-delta technique spans from very-highresolution and low sampling rates such as 20-bit
scaled and shows an improved 12 dB performance respective to its SAF 3 counterpart; in practical implementations scaling should be applied to S ' F ' O N modulators as well.
SNR (dB)
Z 3X(z)
gi
*. . . . . . . . . . . . . .
-20
T
......
-Ill
0
lnpul (did Fig. 10. S N R in cascade single-bit, m u l t i b i t a n d p s e u d o - m u l t i b i t modulators: g2 = g3 = 1 in SBFuO3, g2 = 1/h2 = 2 in SAF3 a n d g 2 = h2 = 1 in S^F.
263
V.F. Dias et al./ AA modulators for A/D converters
Rbit
Co
2o
18
D
=ill
16
Fig. 12. N o n - i n v e r t i n g
[]
14
r
12
I(z) I
//
0.5
I
I
I
I
32
64
128
256
I
I
I
I
I
512 1024 2048 4096 O u t p u t Rate (kHz)
[]
IC
S=single-stage, Cl=cascade l-bit, CM=cascade multibit
O
Predicted
CPM=cascade pseudo-multibit
Fig. 11. State-of-the-art in IC implementations of singlestage and cascadesigma-deltamodulators. at 500 Hz, passing through digital audio and up to 12-bit at 2 MHz. With the advent o f pseudomultibit topologies (CPM) a shift upwards in bandwidth is to be expected, making possible the realization o f 12-bit at 4 M H z , 14-bit at 1 M H z and 16bit at 150kHz sigma-delta A/D converters with available sub-micron silicon technologies. This is an increase o f a factor o f two in the state-of-the-art.
4. Integrator gain and pole error effects In the following, integrator gain and pole error effects in cascade and single-stage modulators are analysed. Integrator gain and pole errors are responsible for spurious noise transfer functions that limit the dynamic range.
4.1 Integrator model Let us consider the switched-capacitor integrator in Fig. 12 and define A0 as the amplifier dc gain and r = CffCo as the ratio between the sampling and integrating capacitors. The integrator transfer function is
264
J._J,"
m
=
switched-capacitor integrator.
-- ~)Z-1
(14)
1 - (1 - 6 ) z -I
where e and 6 are the gain and the pole error, respectively, and are given by _~ Ar + (1 + r)/Ao(Ao >> 1) and 6 ~_ r/Ao (Air is the mismatch assumed between Cs and C0). The analysis that follows considers gain and pole errors separately and o f small value; hence we shall assume ~ << 1 and 6 = 0 for the analysis o f the gain error, and c~ << 1 and 0~= 0 for the analysis o f the pole error; we shall also assume f <~ Bo << M F ,
4.2 Cascade topologies Gain and pole errors in NSBs are modelled as indicated in Fig. 13 [8]. We define two sets of transfer functions, respectively for gain (a) and pole (b) error analysis, whose values relate the NSB inputs X(z) and Q(z) to the spurious outputs Y~,(z) and F=(z) for (0~ # 0, ~ = 0), and Ya(z) and Fa(z) for (6 ¢ 0, ~ = 0). A complete description o f a given NSB is thus achieved with three sets o f transfer functions, one nominal for its ideal behaviour and two spurious ones that take integrator gain and pole error effects into account. Consider the example o f a Type B first-order NSB (Fig. 5b). Using (14) with ~ # 0 and 6 = 0 we obtain
Y(z) ~ X(z) . z -1 + Q(z)- (1 - z -I)
(15)
and
F(z) ~ X ( z ) . z -1
-
Q(z). (1
-
~z -1)
(16)
Microelectronics Journal, I/ol. 25
X(z)
for the output and feedforward signals respectively, where less significant terms have been discarded. Equations (15) and (16) indicate that in a Type B first-order modulator So(z) "~ O, No(z) ~-- O, Fso (z) ~ 0 and Ffo (z) ~-- o~z- 1. Similarly, for & # 0 and 0~ = 0, we obtain Sa (z) ~ 0, Na lz) -~ 6 - z -1 , Fsa(Z)'~O and F N a ( Z ) - - ~ - - 6 . z - . Table 4 summarizes the whole set of spurious transfer functions in first-order and second-order noiseshaping blocks. Delays and signs have not been considered because they are not significant in the noise calculations.
~z)
Q(z)
{z)
Tables 1-4 allow a quick analysis of integrator gain and pole error effects in cascade modulators to be made. Consider the example o f a thirdorder S*F modulator (Fig. 7) whose integrators have a gain error, ~. With the help of Table 4, we identify the only signficant spurious path as being the one that includes FN(z) in the first NSB, S(z) in the second NSB, and the filter H2(z). Because H2(z) is a second-order differentiator the excess noise respective to (2) is
(a)
x,z,
i
Q(z)
PQ~
--
167r4 1 -0~ 2 15 M~
(17)
A similar analysis can be carried out for the integrator pole error (6), and we obtain
(b)
PQa
Fig. 13. M o d e l l i n g integrator gain and pole e r r o r in l o w o r d e r n o i s e - s h a p i n g blocks: (a) gain error; (b) pole error.
TABLE 4
-
4g 2
1
9
M 3
--
52
(18)
as the excess noise respective to (2).
Spurious noise transfer functions in N S B s Gain error
Pole error
Order
Feed
S= (z)
N= (z)
Fs~ (z)
FN=(z)
Sa (z)
Na (z)
Fs~(z)
FNa(z)
First (F)
A B
~ 0 ~ 0
~-, 0 ,-~ 0
~ 0 ~ 0
~ o~ ~ ~
~ 0 ~ 0
~3 ~a
~0 ~0
~0 ~5
Second (S)
A B
~ 0 ~ 0
,-~ 0 ,-~ 0
,-, 0 ~ 0
~ 40~ ,-~ 4~
,- 0 ,,~ 0
~ 2 6 ( 1 - z -1) ~ 2 6 ( 1 - z -*)
~0 ~0
~2~ ~2~
265
V.F. Dias et al./EA modulators for A/D converters
4.3 Single-stage topologies It is well-known that single-stage modulators exhibit a small sensitivity to component mismatch and amplifier non-idealities [1]. Typically, matching tolerances as large as 10% and amplifier gain values as low as 50 dB can be used in Type 1 and Type 2 topologies without significantly degrading the modulator performance.
Figure 14 shows eqs. (17) and (18) added together with (2) for N = A = 1. These plots indicate that gain and pole errors have to be smaller than M -1 and M -2, respectively, to ensure negligible excess noise. Consider now the case of a third-order pseudomultibit modulator (Fig. 9) where the sources of excess noise are three, namely the first, second and third NSBs. Consider first NSB2 and NSB3 together with digital filters H2(z)= ( 1 - 2 - 1 ) 2 and / - / 3 ( z ) = ( 1 - z - l ) 3. Because H2(z) and /-/3 (z) are high-order differentators, in-band noise or distortion coming along with their input signals can be discarded. Thus, only the excess noise due to NSB1 has to be considered, as in the single-bit modulator analysed earlier. Hence, we can conclude that single-bit, multibit and pseudomultibit topologies are all equivalent from the point of view of integrator gain and pole error effects, and that eqs. (2), (17) and (18) can be used in each case. Simulation results, shown in Fig. 15, illustrate this conclusion for the case of an SBFBO3 modulator; gain error is given in percentages (1% = - 4 0 dB) and pole error is given as a function of the amplifier dc gain (8 "~ r/Ao).
Let us consider the modulator in Fig. 2b and assume all coefficients U i a r e zero (note that coefficients Csi do not affect NTF(z)). U n d e r these conditions, NTF(z) is given by NTF(z) =
1
1 + ~ Ag Ii(z)
-
(1 -
z
D(z)
1)L
(19)
i
where (1 - z -1)a and D(z) provide, respectively, the shaping and the stability desired. The denominator D(z) in (19) inserts no poles in the signal band; in the low frequency range D(z) simply amplifies or attenuates the shaping defined by the numerator. Assume the integrators are affected by a gain error, as indicated
VQ. %~ (dB) --70
--80
.............. 3.2.---!........................... --90
........
1100
i ..........
: .........
......
........
--110
-120
....................................
-90
-80
i .........
-70
-60
-50
i .........
-40
I .........
-30
-20 8,c~ ( d B )
Fig. 14. In-band quantization noise power m S*F modulators as a function of integrator gain (c~)and pole (3) errors.
266
Microelectronics Journal, VoL 25
I I I I
Ii0 SNR (dB)
I00
..I.
. . . . . .
I I I I .I . . . . . . I I I
80
70
.I . . . . . . . I I I I
,
90
I I I I
. . . . . . . . .
J . . . . . . l I I I
. . . . . . . . .
4 . . . . . . . . . . . . .
--I"
. . . . . . I
, , I
I I I ! 'I . . . . . . I
, , I
60
...................,
50
.........................
J . . . . . . .
"I . . . . . . . I
, ,I
I I I I I.
. . . . . .
I I !
30
. I I I
It_ . . . . . .
i I I I I
~ . . . . . .
;" . . . . . . . . . . . . . .
r-' . . . . . . I
I I
.
, . . . . . .
~ . . . . . .
I I
I I
I
' . . . . .
I I I I,- . . . . . . I I I I i. . . . . . .
I
I I
J . . . . . . . . . . I I ! I
I I
I I I I I I ,I
. . . . . . .
. .. .. .. .. .
I I
I I I I p . . . . . . I I I I i.
I
, ! I
-i00
-90
-80
-70
-60
!......
ratio o f an
Consider now the case o f non-zero Bi coefficients. These coefficients lead to transmission zeroes in the numerator, while no specific action results from their presence in the denominator. Assume these coefficients are affected by a mismatch ABi. Transmission zeroes will change slightly with respect to nominal conditions, but
- - . , I
I T . . . . . . I I I I ÷ . . . . . . I I I l J. . . . . . .
"1 . . . . . . . I I I I ,,t . . . . . . . I I I I d . . . . . . .
I. . . . . . . I I I I I. . . . . . . I I I I I. . . . . . .
I" . . . . . . I I I I I,- . . . . . . I I I I I.. . . . . . .
-50
-40
-30
-20
T I I l I -*. I I I I JL I I I I I I I I I I
-i0
0
I n p u t (dB)
SBFBO3 m o d u l a t o r
in (14), and that coefficients Ai are implemented with a mismatch Z£4i. It is easy to show that the numerator in (19) is unchanged while the denominator is slightly changed into D'(z). A key point is that D'(z) does not introduce spurious low-order-shaped noise transfer functions, as was the case with cascade modulators.
I I I I
5%
(a)
Fig. 15. S i g n a l - t o - n o i s e
•
I I
J .......
I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I I I I I
--II
!
I I
,
',
! I r . . . . . . I I ! I t- . . . . . . I I I I I. . . . . . . I I I |
I I I I I. . . . . .
.-|
:__.__/_ i ......
10
-II0
I I
,
I I
I I "1 . . . .
I I J . . . . . . .
.II . . . .
.
,,
. . . . .
20
.
I I I I ..I . . . . . . .
I I I I f" . . . . .
,Id.,O.l%, ,, \
S
I
I I I I #. . . . . . .
' SBI~ JL ~ 1¢.13 °l I I ~ _ --~ I
I I I
40
! I I I I. . . . . . .
w i t h (a) integrator gain and (b) pole errors.
will not be removed; optimal placement becomes non-optimal. However, no spurious paths are created for the quantization noise. Simulation results, shown in Fig. 16, prove this conclusion for a Type 2 modulator with an optimal placement o f one pair o f transmission zeroes. The following mismatches have been considered: &/lis in the range 1 ( ~ 1 0 % and AB/s < 30%. N o w we analyse the effect o f an error in the integrator pole. W e shall refer to the same modulator as in Fig. 2b and assume an error 6L in one o f the integrators, say the one at the end o f the cascade. After expanding the summation in (19), we obtain
267
V.F. Dias et al./ZA modulators for A/D converters
ii0 SNR
(dB)
100
90
i i i i
i i i i
I i i i
i i i i
I i i
!'
t
t ' t
!'
I'SBFBO3
; " J
,
,
,
, M=6,4
,
., . . . . . . . ! t I !
,. . . . . . . ! l i I
,. . . . . . . ! i t
, . . . . . . t o t !
., . o ! t i
4.
("
T
"1 .
,. . . . . . . M l l - - - r
70
.
.
i
• . . . . . . ! o t I
!
80
!
I i i !
.
.
'
.
.
.
.
.
I
I
I
i
I
i
i
i
i
i
- - - r
. . . . . .
I
. . . . . .
.
.
o
.
.
. . . . . .
.
r
. . . . . .
i i i
i I i
i
i
t ' i
M'
l'
,
,
i
. . . . . .
t , .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
,__ ! i i l
.
.
.
1
.
I
I
I
i
i
i
i
I ! i
i
i
i
i
i
i
-1 . . . . . . .
~
. . . . . .
r
.
.
.
.
.
.
.
.
.
.
.
.
i i
i. . . . . . .
P
. . . . . .
i.
. . . . .
i
i
i
'I
60
,
I'
i.
. . . . .
l
i
Id "l 1 0 0 d B #.8 0 d B
i
I'
'I
'I
4 . .
-
. . . . .
I
i
i
I'
'I
'I
I. . . . . . .
I. . . . . . .
i
. . . . . . . .
. . . . .
50
........
i t f. i i
. . . . . . . . . . . . . . . . . .
.
.
¢
.
i X .
.
i .
.
......... .
.
.
- ' - r
. . . . . .
iI
I
.
.
.
# I
.
.
.
.
.
.
.
i .
/---'
20
.
.
i i
/:
.
.
.
.
,
.
r
II
.
.
.
.
.
.
.
.
i
.
. .
.
.
. .
.
.
' .
. .
.
.
.
.
.
'
...........
. . . . . .
II
T
. . . . . .
|I
I
"1 . . . . . . .
II I
P
II
II
. . . . . .
T
. . . . .
II
I
I
I
i i- . . . . . .
•
i i. . . . . . .
i i- . . . . . .
i ÷ . . . . .
i i
i i
l i
l i
l i
i i
i I
i i
i i
i i
i I
I i
. . . . . .
I
I. . . . . . .
i I
i i-
.
i i I
.
I .
.
o i .
I
! . .
.
/
.
I
30
.
. i
! !
40
.
i . . . . . .
....................
i .4 . . . . . . .
...............
i i
...... ,
.
.
.
.
.
10 ,
i t i
-ii0
-i00
-90
-80
-70
-60
-50
-40
-30
-20
(b)
-i0
0
I n p u t (dB)
Fig. 15. Signal-to-noise ratio of an SBFBQ)3 modulator with (a) integrator gain and (b) pole errors.
NTF(z) -
(1 - z - t )
D'(z)
L
+
fL(1--Z-1)
D"(z)
L-1
5. Thermal noise and settling (20)
Apart from the fact that D(z) has been changed into D"(z), an additional path has been created for the quantization noise. This path provides only ( L - 1)-order differentiation of the quantization noise; for this reason pole errors (3) lower than M -1 should be used. This same conclusion can be extended to mismatches ai over the remaining integrators in the circuit. T o illustrate this result, Fig. 17 shows the simulated SNP,. behaviour of the same modulator as in Fig. 16 for different values of the amplifier dc gain (M = 64).
268
In the following section we shall consider switched-capacitor ~ A modulators since they are probably the ones most often used for implementing high-resolution and wide-band A/D converters [16-18]. The design o f the first integrator in high-resolution applications requires large sampling and integrating capacitors, while the load capacitor due to the following stage is negligible. If we assume single-stage amplifiers, such as cascode, folded cascode etc., which have a single high-impedance node placed at the amplifier output, we find that the integrator bandwidth (BW) is given bygm/Cs, wheregm is
Microelectronics Journal, Vol. 25
ii0
I00
90
80
70
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I l I. . . . . . .
I I I. . . . . . .
I I • ......
l I I. . . . . . .
SNR (dB)
I
......
. . . . . .
I I 4 ......
I
I
I
,
,
,
I
I
I
,
,
,
i.
60
.
.
.
.
.
50
30
.
.
.
.
.
-e .
I I I
I I l
I
I
.
-ii0
.
.
.
I
'
'
I
I
I
I I I
"I"
4 . . . . . .
' I
,
2 .......
I
.....
'I
I I- . . . . . .
I 4
'~
.
i-
.
.
.
.
.
.
Id.
.
.
.
.
.
.
! t. .
.
.
f .
' ' . I I, ~ ~~
.
.
.
.
',l ,
=
. . . . . I I I I
.
.
.
.
I I I
I ~ _
I-. . . . . . . . . .
"''-
I I
I I
I I
T
i
T . . . . . .
I I I
I.
.
.
.
I I .
.
.
I" .
,
,
'
I
I
I
,
', : .........
i
"= . . . . . . . . . . . . . .
'I
'I
I I- . . . . . .
! ~- . . . . . .
I .I. . . . . . .
I
I
I I I
'I
'I
'I
I I
I I
I I
I
I
I
I
,~ . . . . . .
f ......
; ......
,---
I
I
,I
I I
I I
I I
,
e
,
I. . . . . . . . . . . . . . I
I I I I
M
I
I I
| I i'-'I
____, . . . . . .
T
.
I ~i
'I
I
.
I I I
'I
I I
.
I L. . . . . . . I
'I
......
4-10%
.
I I. . . . . . .
I .a . . . . . . . I
T ......
1
.
I I I
I I I I . . . . . . .r
~
.
I I I
I I I I . . . . . . . T . . . . . . . . "1
d
~ .......
~ . . . . . . . I
.
l
.......
I
.
~5~
# /~7
r- .
I I I
"~
___,
.
.
~
Tf
'
I I
I . . . . . . . . . . . I-
I ~ I ~
'I
.
.
:......
= I I I I
.
.
.a-.
,
......
.
I
I
I
I
~
'
4
#e# - ~I . . . . .
I
I I I
I
I
/-
.
'
=
.
.
,
L
.
.
I
.......
.
.
'
'i
.
,
I
I I
. . . . . . . . . . . . r
.
,
,
I i
I
I0
, I
I !
I
20
I
~
r
.......
I
i I
I s I I
40
~
!
,
.
I I .l . . . . . . .
*,
. . . . . . . . . .
. . . . . . . . . . . . . . . . . . .I . . . . . . . . . . . . . . .
I. . . . . . .
. . . . . .
M=64
I I I. . . . . . .
I
i I
r
. . . . . .
T2-1Z
,~
l
. . . . . . . . . . . . . .
.
I I ..I . . . . . . .
4 . . . . . . . I I I
'
j
I
. . . .
.......
J
i
. . . .
I I
I. . . . . . .
I I-. . . . . . .
'I
'I
I
I I
I I. . . . . . .
I
I. . . . . . .
i
I
I I
I
~.
,
I I
L
I
I +I I I
'
,I
'. . . . . . .
t
I I I I T"
i I
......
"i
,
,
,
,
,
,
,
,
,
!
-i00
-90
-80
-70
-60
-50
-40
-30
-20
-i0
0
Input (dB) Fig. 16. Signal-to-noise ratio of a fourth-order modulator for different values of the mismatch between the filter coefficients (T2-1Z, Type 2 with one pair of transmission zeroes).
the amplifier transconductance and Cs is the sampling capacitor. Thermal noise and settling error are responsible for two bound limits in EA modulators: maximum achievable dynamic range, on the one hand, and maximum allowable oversampling frequency, on the other. Noise sources in SC circuits are M O S switches and operational amplifier broad-band and flicker noise. Flicker noise can be reduced through an increase in the gate area of the amplifier input transistors, or by using special integrator schemes such as chopper stabilization and
offset compensation [19]. In contrast, broadband noise can be reduced only by increasing the sampling capacitor or the oversampling ratio, increases that unfortunately degrade the integrator settling behaviour. Incomplete settling, due to a combined effect of slew-rate (SR) and bandwidth, implies loss of proportionality between input samples and settling error, a fact that leads to an increase in the noise power. Hence, for a given technology, the maximum achievable resolution is mainly a trade-off between thermal noise, dictated by M and Cs, and settling error dictated by SI~ and BW.
269
V.F. Dias et al./CA modulators for A/D converters
I ! I I
Iio
SNR (dB)
1 ¢ I I
I ! I I
I ! I I
I I I I
I
I
I I_ . . . . . . I I
M=64 I L . . . . . . I I
I I I I
I ! I I
I I I I
I
I
'
:
I
/
I00
.
.
I
90
80
. . . . . . .
.I . I. . . . . . .
. . . . . . . . . . . . . .
I
.
.
I . J . . . . . . ! I
.
.
.
'
1 .
.
.
.
=,I
. . . . . .
. .
.
.
.
.
n]z'
'
', JL . . . . . . I I
. .
I I i I
.
1-
.
.
.
.
.
! ! i I
.
~
.
.
.
.
.
I I i I
~
.
.
.
.
.
I I I I~
_
.
.
I I. . ~ 1
.
.
.
.
.
.
.
.
JL_.. I I
/
_
] ~ '
,
.
.
'
.
.
.
.
.
,
b .
.
.
'
.
T-"
I i i I
r I I
~1~
~
,
:
'
I J . . . . . . . ! I
I ! ~
I I
I i i I
70 i
.'
I
i
.
.I'
I
.
I
. 'I
60
i
za.
60- - dB Jo ~
_ _ _
!
i
I
.
do dB
.
I
. . . . .
l I
40
. . . . . . . . . . . . . . . . . . . . . . . .
I
I ~
....... r ...... !
i I I
1 ...... o ~ I ~ • I I ~
-, ~
i
i
',
',
I
4.
I
!
i
I
I
I ,
I I
I I
i i
I I
I
I
I
I I I I I -_.-, T--'" I I I I
I I I I
! I I I I .., T I i I I
I
I
. . . ._ •r ....... . . .
"1
.
i
I t ! I I
_~_.;.,c_
~
. ',
|
40 dB
I 50
: .
. .
I I I I
...... . . .
. . .
I I I I
I I I I
I I ! ! ,_, r I I I I
I
!
I
-,"I ....... . . . . . . .
,I.. .. .. .. . . . .. .
...... . . .
. . .
J
30 ¢
20
....... [ ...... !
I
j
!
::
!
I
I
! I
I
I
I
I
I ! I r . . . . . . I
i I I
I I I T . . . . . . I
I I I
I I I £' . . . . . . I
I I I T .... i
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ _ I i I I i I
10
I
I
I !
I ! I
I
i
I I
I I
I I
I I
I I
I I
I I
I I
-90
-80
-70
-60
-50
-40
-30
-20
-i0
:
-I00
..-,
I
I I
....
-Ii0
i ....
i
I ! I i. . . . . . . I
i
/
i I I "I . . . . . . . I
¢ I
.
.
.
.
r
. . . . . .
I
.
.
.
3. .
. . . . . .
0
Input (dB)
Fig. 17. Signal-to-noise ratio of a fourth-order modulator for different values of the amplifier gain (T2-1Z). 5.1 Thermal noise Thermal noise in SC modulators is c o m m o n l y evaluated from the simplified relationship Pth = kT/C~M, which accounts only for the noise power due to sampling switches. This relationship can be applied to SC integrators in which the noise of integrating switches and operational amplifiers is heavily filtered by the amplifier itself, giving a negligible contribution to the overall noise power. This is, however, not the case with high-resolution and wide-band P~A modulators, where the need o f speed optimization leads to particular SC integrator designs. In such applications a more accurate formulation o f the broad-band noise power is
270
required. The following relationship was proposed by the authors in a previous work [16]:
PTh
_
1
kT
M C~
[41 2+
(1+c~)
(21)
This relationship accounts for the noise o f sampling and integrating switches as well as the amplifier broad-band noise. Equation (21) was derived assuming transconductance amplifiers, as mentioned above, with the frequency compensation performed by a series o f sampling and integrating capacitors. Parameter c~ is a noise coefficient which characterizes the particular
Microelectronics Journal, Vol. 25
amplifier and is dependent on the ratio between the transconductance o f load and input transistors. For an optimal design (0c << 1), eq. (21) leads to a 10/3 increase in the in-band noise power. This means a 5 dB increase in the thermal noise floor, i.e. a loss of about 1 bit in the modulator resolution respective to that given by the simplified equation Pth = k T / C ~ M . For instance, a I pF sampling capacitor and an oversampling ratio M = 100 lead to a thermal noise power o f ~ - 1 0 0 dB, which, on its own, defines an upper bourfd limit o f ~-,16bit to the maxim u m achievable resolution. An 18-bit m o d u lator would require an ~ 1 6 p F capacitance, while a 20-bit one would require a 2 5 6 p F sampling capacitor. 5.2 Settling error Settling error in E A modulators has been largely studied via computer simulations [1, 14]. Software tools available today [20, 21] provide users with accurate behavioural models which, with other facilities, allow the effects of slew-rate and bandwidth to be analysed. Such models consider both slewing and linear-mode settling conditions, which generally occur in real operation. Typically, results obtained from the use o f finitesettling models indicate that settling-error effects increase rapidly with oversampling frequency. In a recent work we proposed a simplified relationship for evaluating setding-error effects on HA modulators [16]. After some algebraic simplifications, that relationship can be written as
P~t = 35 •
- 27.BW-
- 20 • log10
10.1ogl0(M
in normalized values with respect to the oversampling ratio, i.e. B W = B W / M F ~ and S R = SR/MF~ with S R in V/s and B W in Hz. Equation (22) is plotted in Fig. 18 as a function of (a) B W and (b) SR. For a given slew-rate the excess noise decreases linearly with integrator bandwidth; conversely, for a given bandwidth the decrease of Pst with slew-rate saturates for high values o f SR. This means that the integrator is never slew-rate limited, and the case for which the model was developed is no longer valid. Simulations made with T O S C A [21] indicate that eq. (22) is a good predictor of settling-error effects for B W and S R values___larger than three, and that for a good design S R should be larger than B W and both larger than five. 6. Discussion
In this section we consider three different applications o f a third-order pseudo-multibit topology. These are intended to achieve 12-bit at a 4 M H z rate (Design 1), 14-bit at a 1 M H z rate (Design 2) and 16-bit at a 1 5 0 k H z rate (Design 3). T h e design methodology follows from eq. (12), which gives the m a x i m u m achievable resolution as a function of the quantization noise, eqs. (17) and (18) for the excess noise due to gain and pole errors in the integrators, and eqs. (21) and (22) for the excess noise due to thermal and settling effects; these are repeated in (23) to (26), expressing the resolution in bits of an S*F*ON topology with scaling factors gl = 1, g2 = 1 / h 2 = 4 and g 3 = 1/h2 • h3 = 4. RQ --~ 3.5 - log2(M ) + N - 6.5
) - 27
(22)
where the so-called excess noise due to settling error is expressed in dB as a function of bandwidth and slew-rate parameters; for simplicity's sake, bandwidth and slew-rate are expressed
RTh
"~
(23)
0"5" log2(M ) + 0.5 • log2(CpF ) + 12.4 (24)
R= ~_ 2.5 • log2(M ) - 3-33. log10(00 - 4
(25)
R~ -~ 1.5. log2(M ) - 3.33. log10(&) - 1.9
(26)
271
V.F. Dias et al./ A modulators for A/D converters
-50
%, (dB) -70
__J
...............
.J. . . . . . . . . . . . . . .
.J. . . . . . . . . . . . . . . . I I I I I I
SR. =2
!
I I I I
-90 ---I
. . . . . . . .
=1 .
.
.
.
.
.
.
.
.
.
.
.
.
"1 .
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . . . . . .
\,
!
SR =4 I" !
-Ii0
.
I
.
.
.
.
.
.
.
.
.
.
.
.
.
I I I I
~'~ -130
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
=lO .
.
.
.
. . . . .
.
ii . . . . . . . . . . . .
-150
2
3
4
5
6
BW
These four relationships are depicted in Fig. 19 as a function of the oversampling ratio. Where settling is an issue, we shall assume SR(v/~ ) ~>BW(Hz)>~SMF~. For a real prediction of the noise performance of HA modulators, technological constraints have to be considered which set a relation between the allowable bandwidth and sampling capacitor size. As mentioned before, high-resolution GA modulators use single-stage amplifiers where the effective bandwidth (BW) during the integrating phase is inversely proportional to the sampling
272
(a) amplifier bandwidth and (b) slew-rate.
capacitor. Conversely, wide-band modulators require very high values of B W with small sampling capacitors, making the non-dominant pole and the capacitor of the following stage important parameters. Figure 20 shows one possible speed characteristic of a sub-micron silicon technology. Three particular operating points of Fig. 20 will be considered here: C~ = 0.25 pF and B W = 2 5 0 M H z for Design 1; Cs = I pF and B W = 150MHz for Design 2; and C~ = 3pF and B W = 5 0 M H z for Design 3. This sets the
Microelectronics Journal, Vol. 25
-501
PSt
(dB)-70 . ~ ~ : ~
...................
a................................
-90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
............... i.............. , ............... ] I !, I I I I I
...... -130
I ,
.=4
I I I I a
~
. . . . . . . . . . . . . . .
BW
I I, I I I , I
,. . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
a ...............
a ...............
=6
-150
I 2
I
I "l
I
I
I
I
I
i
I
I
I
I=I
I
I
I
3
I
i 4
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
l
I
5
SR
(b) Fig. 18. Settling-error noise power in switched-capacitor modulators as a function of (a) amplifier bandwidth and (b) slew-rate.
allowable oversampling frequency to 50MHz, 30 MHz and 10 MHz, respectively, in Designs 1, 2 and 3. One basic rule of the design methodology is that wide-band modulators are mainly limited by quantization noise (low oversampling ratios and wide-band amplifiers), while highresolution modulators are mainly limited by thermal noise (large sampling capacitors and slew-rate amplifiers). First, consider Design 1 (quantization noise constrained). Twelve bits of resolution at a 4 MHz rate set the oversampling ratio at 12 and
the topology to S*F*O7 (eq. (23) and Fig. 19a); Figs. 19b-d indicate that neither thermal noise nor excess noise due to integrator gain and pole errors constitutes a limit. A 60 dB operational amplifier and a 0.25 pF sampling capacitor with 0-5% matching accuracy is enough to guarantee the performance desired. Consider now the opposite case of Design 3 (thermal noise constrained). Sixteen bits at a 150 kHz rate set the oversampling ratio to 64 (MFs = IOMHz) with a sampling capacitor of 3pF (eq. (24) and Fig. 19b). Equation (23)
273
V.F. Dias et al./ A modulators for A/D converters
Rbit(Th)
Rbi t (Q) 9
7
18
5
3
N=I
....--- 64
18
/16 /
16
4
~
16
Cs=l pF 0.25
D2
14 12
14 O D1
12
3.6 4
5
6
@
D1
I
I
I
I
I
I
7
3.6
4
5
6
7
Log 2(M)
Log 2(M)
(a)
(b)
Rbit(c0
Rbit(8) 0.01%
16 18 ~
o
D
0.1%
2
cx=l%
-4 10
18
-3 10
/
16
• D3
8 =10-2 14
14
12
12
3.6
4
I
I
I
5
6
7 Log 2(M)
(c)
|
3.6 4
5
6
7 Log 2(M)
(d)
Fig. 19. Resolution in bits in cascade S*F*C)* modulators as a function of the oversampling ratio: (a) quantization noise; (b) thermal noise; (c) and (d) excess noise due to integrator gain and pole errors respectively.
(Fig. 19a) indicates that an S * F ' O 2 topology guarantees 12 bit, while (24) and (25) indicate that 1% matching in the integrated capacitors and 60 dB amplifiers are sufficient to reach the desired performance. Design 2 is mixed quantization-thermal constrained. Starting with a 1 pF sampling capa-
274
citor, we obtain that the m a x i m u m allowable oversampling frequency is 3 0 M H z and that a m i n i m u m oversampling ratio o f 16 is required to o v e r c o m e the thermal noise constraint. This limits the output rate to about 2 M H z . From (23) we see that an S * F ' O 8 modulator is required, i.e. quite a complex design. A reduction in the quantizer complexity to about 4 bit
Microelectronics Journal, Vol. 25
simulation obtained with T O S C A , using the parameters o f Table 5.
Cs(pF)
D3
7. Conclusions 132
0.5 I D1 0.25 I SO
I 100
I 20O
BIN
(MHz)
Fig. 20. Integrator speed characteristicof sub-micron silicon single-stageamplifiers. (S*F*O4) is possible provided an oversampling ratio o f five octaves is allowed. This increase in M reduces the m a x i m u m allowable output rate to 1 MHz, giving however the possibility to decrease the sampling capacitor to 0.5pF and increase the integrator bandwidth. This procedure can be iterated until a good trade-off between complexity and performance is achieved. O n e possible solution consists o f using an S*F*Q) 4 topology with a sampling capacitor o f 0.75 pF to obtain 14-bit resolution at a 1 M H z rate. Table 5 summarizes the design parameters for the three designs considered. Figure 21 shows a
This paper has reported a comparative study o f HA modulator topologies which are suitable for high-resolution and wide-band A/D converter applications. W e have revisited the single-stage and the cascade architecture and stressed the fact that cascade modulators have optimal noiseshaping, are easy to design, are unconditionally stable and are relatively insensitive to integrator gain and pole errors. W e have concluded that cascade pseudo-multibit topologies provide designers with three degrees o f freedom, namely the oversampling ratio, the noise-shaping order and the quantizer resolution, all o f this without requiring N-bit D/A converters. W e have also concluded that cascade pseudo-multibit topologies have increased design, application and testmg flexibility, allowing external multibit quantizers to be used without concern for noise or distortion. Finally, we have described the design procedure o f three pseudo-multibit topologies. The speed characteristic o f an SC integrator has been derived from the parameters o f a modern C M O S process. O n this basis we have shown that pseudo-multibit topologies have the potential o f achieving 12-bit at 4 M H z , 14-bit at 1 M H z and 16-bit at 150 kHz.
TABLE 5 Modulator and amplifierparameters for Designs 1, 2 and 3 Design 1 12-bit @ 4MHz
Design 2 14-bit @ 1 MHz
Design 3 16-bit @ 150kHz
S*F'O7 M = 12 MFs = 48 MHz B W = 250MHz S R >>-250 W/as A0 -~ 60dB Cs = 0.25 pF(~ 0.5%)
S*F*O4 M=32 MFs = 32 MHz B W = 150MHz S R >/- 150 V/ps A0 -~ 60dB Cs = 0.75 pF(~ 0.5%)
S*F*O2 M=64 MFs = 9.6 MHz B W = 50MHz S R >1 50 V/#s A0 --~60dB Cs = 3 pF(~ 0.5%)
275
V.F. Dias et al./ A modulators for A/D converters
SNR (dB)
i00 90
80
. . . . . . .
70
. . . . . . .
60
50
. . . . . . .
I
I
I I I I I. . . . . . . . I I I I I . . . . . . . I I I I I I_ . . . . . . . I I I I I
I I I I I. . . . . . . . . . . . . . . . I I I I I_ . . . . . . . . . . . . . . I I I I I I I_ . . . . . . . I. . . . . . . I I I I I I I I I I
i i '
I I '
I I
I I I-
I I I-
I I I I I
. . . . . . .
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . I
_I . . . . . . . I I
,SF~
' BB2 I
f -
,.,/
I
I
I, I /
. . . . . . . . . . . . . . . . . . . . . . .
I---I
/
"I . . . . . . .
. . . . . . . .
.
SBB4F.~.....
-'---,,
," . . . .
F
I
30
. . . . . . . . . . . . . . .
I_. I I
.
I
.
.
.
.
.
I I I I
20
I I
-I . . . . . . . . I I I i !
-I00
-90
-80
-70
I I I- . . . . . . . i I i I I
-60
.
.
.
.
O I I I. . . . . . . I I I I I I. . . . . . . I I I I I
. . . . . . . . .
10
"--S'
-50
I
I I
/.' 40
I I I I I "I-- ----
I I I I I --i . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.I . . . . . . . I I I I I -I . . . . . . . I I I I I
-40
I I I "I . . . . I
I
SF~
' BB7
i "1 . . . . . . . . I I I I I. . . . . . . I I I I I J . . . . . . . I I I I I -I . . . . . . . I I I I I
-30
. . . . . . .
I I "l . . . . . . I I I I
j
. . . . . . . I I I I I
J
. . . . . . . I I ! I I -4 . . . . . . . I I I I I
-20
j
. . . . . . I I O I I
J . . . . . . / I I I I -I . . . . . . I I I I I
-i0
o
Input(dB) Fig. 21. Sinmlated SNR of 1)esigns 1, 2 and 3 with real parameters for the amplifiers (Table 5).
References [1] K.C.-H. Chao et al., A higher order topologT for intcrpolative modulators for oversampling Aft) converters, IEEE Trans. Circuits and Systems, CAS-37 (Mar. 199{}) 309-318. [2] B. Signore, D. Kerth, N. Sooch and E. Swanson, A monolithic 20-b delta sigma Aft) converter, IEEEJ. Solid-State Circuits, SC-25 (6) (Dec. 1990) 1311-1316. [3] R.W. Adams et al., Theory and practical implementation of a fifth-order sigma delta A/D converter, J. Audio Eng. Soc., 39 (7/8)-(July/Aug. 1991) 515-528. [4] Y. Matsuya et al., A 16-bit oversampling A-to-D conversion technology using triple integration noise shaping, IEEEJ. Solid-State Circuits, SC-22 (6) (Dec. 1987) 921-929. [5] L. Longo and M. Copeland, A 13-bit ISDN-band
276
161
[7] [8] [9]
A1)C using two-stage third-order noise-shaping, Proc. 1988 Custom Integrated Circuits Conf., June 1988, pp. 21.2.1-4. C.D. Thompson et al., A monolithic 50kHz 16-bit A/D-1)/A converter using sigma-delta modulation, Proc. IEEE Int. Syrup. Circuits and Systems, 1990, pp. 906-909. M. Rebeschini et al., A high-resolution CMOS sigmadelta A/D converter with 320 kHz output rate, IEEEJ. Solid-State Circuits, SC-25 (2) (Apr. 1990) 431-440. V.F. Dias and V. Liberali, Cascade pseudo-nmltibit noise-shaping modulators, IEE Proc.-G., 140(4) (Aug. 1993) 237-246. D.B. Ribner, A comparison of modulator networks for high-order oversampled SD analog-to-digital converters, IEEE Trans. Circuits and Systems, 38 (2) (Feb. 1991 ) 145-159.
Microelectronics Journal, Vol. 25
[10] L.A. Williams III and B.A. Wooley, Third-order cascade sigma-delta modulators, IEEE Trans. Circuits and Systems, CAS-38 (May 1991) 489-497. [11] B.P. Brandt and B.A. Wooley, A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion, IEEEJ. Solid-State Circuits, SC-26 (12) (Dec. 1991) 1746-1755. [12] B.H. Leung and S. Sutarja, Multibit E - A A/D converter incorporating a novel class of dynamic element matching techniques, IEEE Trans. Circuits and Systems-ll, 39 (1) (Jan. 1992) 35-51. [13] L.R. Carley, A noise-shaping coder topology for 15 + bit converters, IEEEJ. Solid-State Circuits, SC-24 (Apr. 1989) 267-273. [14] D. Ribner eta/., A third-order multistage sigma-delta modulator with reduced sensitivity to non-idealitics, IEEEJ. Solid-State Circuits, SC-26 (12) (Dec. 1991) 1764-1773. [15] T. Leslie and B. Singh, An improved sigma-delta modulator architecture, Proc. IEEE Int. Symp. Circuits and Systems, 1990, pp. 372-375.
[16] V.F. Dias, G. Palmisano, P. O'Leary and F. Maloberti, Fundamental limitations of switched-capacitor sigma-delta modulators, IEE Proc.-G, 139 (Feb. 1992) 27-32. [17] V.F. Dias, G. Palmisano and F. Maloberti, Noise in mixed continuous-time sigma-delta modulators, IEE Proc.-G, 139 (6) (Dec. 1992) 680-684. [18] V.F. Dias, G. Palmisano and F. Maloberti, Harmonic distortion in SC sigma-delta modulators, to appear in IEEE Trans. Circuits and Systems. [19] K. Hsieh et al., A low-noise chopper-stabilized differential switched-capacitor filtering technique, IEEEJ. Solid-State Circuits, SC-16 (6) (Dec. 1981) 708-715. [20] B. Boser et al., Simulating and testing oversampled analog-to-digital converters, IEEE Trans. CAD, 7 (6) (June 1988) 668-674. [21] V. Liberali, V.F. Dias, M. Ciapponi and F. Maloberti, TOSCA: a simulator for switched-capacitor noiseshaping A/D converters, IEEE Trans. CAD lnteg. Circ. Syst., 12(9) (Sept. 1993) 1376-1386.
August 29- September 2, 1994 Senri Life Science Center, Osaka, Japan The scope of MBE-VIII will cover the entire spectrum of molecular beam epitaxyo 1) 2) 3) 4) 5) 6) 7) 8)
element-, hydride-, and metalorganic-source MBE, modulated-flux MBE, MBE of Ill-V, II-VI, IV-VI compounds, group IV elements, MBE of metals, superconductors, insulators, magnetic and other materials, new approaches for atomic-scale control of surfaces, and interfaces, MBE growth mechanism, characterization, electronic, photonic, quantum and novel devices, including growth aspects, in situ processing and characterization, MBE production technology including safety problems.
Request for further information, please contact: Professor Shun-ichi Gonda, MBE-VIII, Chairman The Institute of Scientific and Industrial Research, Osaka University, 8-1, Mihogaoka, Ibarakl, Osaka 567, Japan Teh +81-6877-5111 (ext. 3575); Fax: + 81-6-877-6447
Important Dates: Manuscript deadline Late News deadline Conference
July 1, 1994 August 10, 1994 August 29 - September 2, 1994
There will be a commercial exhibition of equipments and accessories paralleling the technical sessions.
IHtlemJ~l
277
Microelectronics Journal, 25 (1994) 253-277
"t
Sigma-delta modulators for high-resolution and wide-band A/D converter applications V.F. Dias 1, V. Liberali 2 and G. Palmisano 3 IINESC, R. Alves Redol 9-3°A, 1000 Lisbon, Portugal 2UniversitY1di Pavia, V. Abbiategrasso209, 27100 Pavia, Italy 3Universit3 di Catania, DEES, V. A. Doria 6, Catania, Italy
High-resolution and wide-band sigma-delta (HA) A/D converters are based on high-order single-stage or cascade modulators and, more recently, also on multibit topologies. This paper reports a comparative study of the most promising modulator topologies available today, paying special attention to a new class of cascade multibit topologies that we have developed which do not require multibit D/A converters. Comparisons are made in terms of design and implementation complexity, sensitivityto amplifier dcgain and matching between components, thermal noise, amplifier slew-rate and bandwidth, and D/A converter linearity. Design examples are given showing that 12-bit, 14-bit and 16-bit HA A/D converters with 4MHz, 1 MHz and 150 kHz output rates respectively are possible using state-of-the-art silicon technologies. 1. Introduction
he three basic concepts behind sigma-delta (HA) A/D converters are oversampling and noise-shaping, on the one hand, and digital decimation on the other. Signals are first oversampled and coarsely quantized inside a loop
T
0026-2692/94/$7.00 © 1994 Elsevier Science Ltd
(modulator), and then lowpass filtered and decimated down to the Nyquist rate (decimator). The advantages are known: possibility o f efficiently trading speed for resolution, and relaxed accuracy and matching requirements imposed on the analogue components. This is in line with the trend towards sub-micron technologies optimized for digital circuitry. Figure 1 shows the two basic modulator architectures available today: single-stage (Fig. la), and cascade (Fig. lb). Single-stage modulators have the same structure as a filter, and have one single quantizer and a D/A converter (see Fig. 2) [1-3]. The output signal in a single-stage modulator is given by Y ( z ) = X ( z ) . STF(z) + Q ( z ) . NTF(z)
(1)
where X ( z ) is the input, Q(z) is the quantization noise, and STF(z) and NTF(z) are the signal and
253
i
V.F. Dias et al./CA modulators for A/D converters
g 1¥1(z)
Ql(Z) h2Fl(Z) Q(z)
Vz)
g2Y2(z)
%(z) ' F2(z)
A/D
•
t
I hk
g kYk(z)
(a)
(b)
Fig. 1 Architectures of sigma-delta modulators: (a) single-stageand (b) cascade. the noise transfer functions, respectively. Equation (1) assumes the quantization noise is additive, uncorrelated with the input signal and white, having a power which depends on the quantization step 2A/2 N, where A and N are the quantizer input dynamic range and resolution, respectively. Usually, NTF(z) is highpass, either maximally-flat Butterworth or Chebyshev, or inverse-Chebyshev or elliptic, and the order L is usually made 3, 4 or 5 and rarely larger. The signal transfer function STF(z) is lowpass, with passband edge B0.
swing optimization. Filters Hi(z) are low-order F I R and allow the noise sources associated with the first ( k - 1 ) NSBs in the cascade to be cancelled. The remaining noise source, Qk(z), is highpass shaped by Hk(z). Cascade modulators implement noise transfer functions that are optimal highpass, i.e. NTF(z) = (1 - z-l) L, and have allpass signal transfer functions, i.e. STF(z) = z -p. As far as the modulator order is concerned, most applications use L = 3 because, for larger values o f L, c o m p o n e n t matching and accuracy becomes a critical aspect.
Figure lb shows the cascade architecture [4-11]. Cascade modulators are built up with low-order noise-shaping blocks (NSBi), whose transfer function can be zero-order multibit, first-order where N T F i ( z ) = ( 1 - z -1) and second-order where N T F i ( z ) = (1 - z - l ) 2 [8]. Each NSB in the cascade supplies to the following stage a signal, Fi(z), that can be scaled (hi) for signal
The in-band noise power in a sigma-delta modulator is given by the integral of I Q(f)12. I N T F ( f ) ]2 over the signal band, B0. For those cases where NTF(z) = (1 - z-l) L, this integral can be approximated by
254
4A 2 rc2L l 1 PQ ~ 3 2L 4- 1 " 2 2N " M 2L 4- 1
(2)
Microelectronics Journal, t/ol. 25
2. Single-stage modulator networks
where M is the oversampling ratio. Singlestage modulators have N T F ( z ) ¢ (1--z-7)L; this is because the noise transfer function is appropriately modified by adding a denominator function to guarantee stability. Stabilization of single-stage modulators leads to increased amounts of noise power respective to eq. (2)[11.
2.1 Single-bit Figure 2 shows the two most common singlestage modulator topologies reported in the literature, Type 1 (a) and Type 2 (b). We shall assume that I(z)= z - 1 / ( 1 - z -1) and that the quantizer and D/A converter are delayless.
Type 1 modulators have two sets of design parameters: coefficients Ai converging at the quantizer input node, and coefficients Bi converging at the modulator input node. From the point of view of the noise transfer function implemented, an equivalent topology results if the feedforward paths (Ai) are replaced by feedback branches subtracting from each integrator input the D/A converter output signal; this alternative has advantages in switched-capacitor implementations. The signal and the noise transfer function in Type 1 modulators are given by
Equation (2) indicates three degrees of freedom in the design of a modulator, namely the oversampling factor, M, the noise-shaping order, L, and the quantizer resolution, N. The choice of a suitable set of parameters is a key factor in sigmadelta design because technological constraints such as speed, thermal noise, matching and accuracy, on the one hand, and design complexity on the other have to be carefully considered. This paper reports a detailed study we have made of the most promising single-stage and cascade modulators available today. The paper focuses on the several trade-offs involved in the design, and explores the limits imposed on (2) by the technology. A main conclusion is that cascade pseudo-multibit modulators have advantages with respect to other topologies, and that 12-bit at 4MHz, 14-bit at 1MHz and 16-bit at 150kHz A/D converters are feasible at the present state-of-the-art.
Ao z-1 (1 -- Z-l) L L
+ y~Aiz-i(1-z-1) L-1 STF(z) =
,=1 (1 +A0z-1) (1 c
" ' "
A B I • A 22
(a)
~
(3/
+ Z (Ai ni) z-i (1 Z-l) L-i -
-
-
i=1
\c,
X(z),,-,,
z-') L
-
\c~
\c~,
\ c~
Bk
X(z)o Y(z)
[~~
=
Y(z)
(b)
Fig. 2. Topologiesof single-stagesigma-deltamodulators:(a) Type 1; (b) Type 2.
255
V.F. Dias et al./ A modulators for A/D converters
and
(1 - z - l ) L L
-- ~ - - ~ B , z - i ( 1 - z NTF(z) =
l)L-i
i= 1 (1 + A o z -1)(1 - z -1)L
(4)
L
+ ~7_~(Ai-Bi)z-'(1
-z
1)L i
i=1
respectively. The alternatives for synthesizing NTF(z) in (4) are two: one for B i = 0 and another for 8 i -7k O. In the former case, the numerator in (4) becomes an L-order differentiator, allowing maximally-flat Butterworth or Chebyshev nmse transfer functions to be synthesized. Poles are defined by A i coefficients, and are synthesized according to the stability condition established by Lee et al. [1]. Stability is achieved by decreasing the gain of NTF(z) over the high-frequency range, a decrease that results in increased amounts of in-band noise power respective to the optimal shaping case given by NTF(z) = (1 - z-l) L. The second design alternative assumes some or all B i 7/= O. This provides designers with the possibility for placing zeroes anywhere in the signal band, allowing inverse-Chebyshev and optimal elliptic filtering functions to be synthesized. Gains in resolution as large as 2-bit are possible with these alternative designs. In both designs, B i = 0 for all i and B i :fi 0 for some or all i, STF(z) is uniquely determined by t h e A i and Bi coefficients and is neither maximally-flat, equiripple or linear phase. This is one of the aspects of which the Type 2 topoplogy described next can take advantage. Type 2 topologies have three sets of coefficients, A i , B i and Ci (see Fig. 2b). In this case, Bi coefficients define second-order resonators from which pairs of transmission zeroes are namely
256
obtained and placed in the signal band rather than dc. T h e poles in NTF(z) are almost defined by the Ai coefficients and are again synthesized according to the stability condition referred to above. Finally, Ci coefficients have no effect on the noise transfer function implemented. This gives the designer more flexibility in the synthesis of the signal transfer function, STF(z), and allows better control over the amount of signal at the output of intermediate integrators. Type 2 and Type 1 topologies lead to different signal transfer functions. Figure 3 compares simulated power spectral density plots of the signal at the output o f Type 1 and Type 2 modulators. The Type 1 m o d u lator has been made maximally-flat Butterworth (T1-MF), while the Type 2 uses an optimal placement of one pair of transmission zeroes (T2-1Z). In the former case, all zeroes coincide at dc and the noise is lower near zero. In the latter case, a pair of complex transmission zeroes has been placed around 6.5 kHz. This results in a reduction in the noise level at that frequency. Figure 4 compares the simulated SNR, behaviour of three different designs of a fourth-order modulator (the input signal is sinusoidal, of frequency f < B0, and M = 64). The designs considered are Type 1 maximally-flat (T1-MF) and elliptic (T1-EL), and Type 2 with optimal placement o f one pair o f transmission zeroes (T2-1Z). Stability in high-order single-bit modulators imposes I N T F ( f ) ] < 6dB in the highfrequency range, provided no input signals larger than ~ - 6 d B are fed into the circuit (dB respective to A) [1]. In practical implementations, clipping circuits are used to limit the signal swing in the integrators, as well as overload detectors to control undesired unstable states [3]. Adams et al. [3] report a fifth-order modulator with 105 dB (18-bit) dynamic range in the digital audio band. This is considered an upper b o u n d limit to the HA technique in audio applications.
Microelectronics Journal, Vol. 25
0
PSD
(v 2/Hz)
i I I
-20 o o o i -40
- b u
. . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .
i
,. . . . . . . . . . . . . . . . )
,. . . . . . . . . . . . . . . . =
l = i o
l i ) i
~.
_o,-,
U~
. . . . . . . . . . . . . . .
,. . . . . . . . . . . . . . .
,. . . . . . . . . . . . . . .
j
I I I I
I I I I
,
,
,
,
t i
i t
'
r
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-120
. . . . . . . . . . . . . .
-140
. . . . . . . . . . . . . .
-160
.
-180
J ~
.
.
.
Ii! .
.
.
.
.
.
.
i
.
.
.
.
.
.
I
~..
*
.
.
.
I. . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
i
I
I I
I I
I
. . . . . . . . .
4.00e+03
~I,
.J ^ at,, ~lhlJ~filllil,l~tlll/lfllv"i
I I i l
Ii
~
'~•
'
i. . . . . . . . . . . . . . .
.
|
-200
'',
. . . . . . . . . . . . . . . .
"1 . . . . . . . . . . . . .
T1-MF
'
n-lz
a
. . . . . . . . . . . . . . .
I I I I
" . . . . . . . . . . . . . . .
j . . . . . . . . . . . . . . . .
I I I I
i t
-I00
=
I
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
i .
.
.
.
.
.
.
.
.
.
J
.
i
. . . . . . . . .
I
,,'
1 i i
.
.
.
. . . . . . . . . . . . . . . .
i .
.
.
.
.
.
.
I
i I
8.00e+03
l,
.
J
.J . . . . . . . . . . . . . . .
.
'WI'
.
I I
. . . . . . . . .
1.20e+04
I
.........
1.60e+04
2.00e+04 Frequency (Hz)
Fig. 3. Spectra o f the signal at the o u t p u t o f fourth-order single-stage modulators.
2.2 Multibit topologies
Instability in high-order single-bit modulators is due to an insufficient number of bits in the quantizer and D/A converter. Analytical and simulation results agree that high-order singlestage modulators with optimal shaping can still be implemented provided enough bits are used in the quantizer and D/A converter [12]. It has been found that in idle noise conditions the relationship between the shaping order and the number of transition levels required is (2 L -
1).
One principal drawback of single-stage multibit networks has been the required D/A converter
linearity. This is because the signal at the D/A converter output is not shaped, and non-linearity effects appear unchanged at the modulator output. Several solutions have been proposed to overcome this drawback: component trimming, digital error correction and dynamic matching [13]. The first two solutions are costly, while the latter one has proved to be inadequate for highresolution applications because harmonics are simply traded for white noise, (1/M)-th of which falls again inside the signal band. This is a severe limitation from the point of view of the linearity required from the D/A. Carley [13] reports a D/A converter that achieves 16-bit dynamic range and - 9 4 dB total-harmonic distortion.
257
V.F. Dias et al./ A modulators for A/D converters
Ii0
SNR (dB)
'i
'l
T
]
'l
'I
i I
t t
f t
I i
t l I
t t t
a i
i l
,
,
t
I g I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i00
i l
90
. . . . .
i
. . . . . .
.....
. . . i 1 . . . . . . . . . . . . . .
r ...... .
70
.
i
60
,
I
I I
I I
I I
. I ,. . . . . . .
. I r .
~.
.
I . . . . .
i
4
I
.a
.
. . . . .
~
I- . o i
.
.
.
.
.
. l
.
.
.
-/-'~V" .
.
/__ . .
.
I
.
/
" / .
.
T
"/I'--~ ~7f}'i
I
~
', i .
I. . . .~/~/D,./I,L ..
I I
, "1---
.
t i /
t.
i I
I I I
T1-EL 1
J . . . . . . .
. . . . .
.
I I I
I
i
.
.
. . . . . .
.
i I I
I
.
- - - ~
, M=64
k . . . . . .
.
I I I
. o
,
I. . . . . . .
. . . . .
.
I i i
i i
. . . . .
J . . . . . . . . . . . . . . I I
80
l i
[
.
I , I
.
.
.
.
.
.
,
,
I I I
I I I
', I
, t
I
.
T2-IZ'-I. 50
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
J
40
. . . . .
ii" .
.
.
.
.
.
.
.
.
.
.
m r i
30
I I
20
J i
. . . . . . .
I
-i00
.
.
'. . . . . . .
T . . . . . . i i o o
I.
t J i I
I i i I L. . . . . . .
i I I I L . . . . . .
.
-90
-80
.
.
.
.
'. . . . . . .
.
.
.
.
• . . . . . .
I I I I • . . . . . . I I i I
.
L . . . . . .
"I . . . . . . . l t l I I I I I a . . . . . . .
.
J . . . . . . .
~ i
-70
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
~"TI-MF' .
i i
0 -ii0
.
I i I I
I I
jy
I0
. . . . . . .
.
.
-60
-50
-40
i. . . . . . . i i i I
I" . . . . . . I i I I
I"
I I I I I. . . . . . . I I I I
I I I i I. . . . . . . I I I I i. . . . . . . . . i . . . . . .
I I
I i
-30
-20
-I0
0
Input (dB) Fig. 4. Signal-to-noise ratio in fourth-order single-stage modulators.
More recently, Leung and Sutarja [12] proposed a set of alternative dynamic matching techniques designated as clocked and individual-level averaging. In clocked averaging the unit-elements of a parallel D/A converter are grouped and permuted at different clock rates (sub-multiples of the sampling frequency). The visible effect is modulation of harmonics, being translated to frequencies around sub-multiples of the sampling frequency. This technique has several drawbacks: it requires a minimum oversampling and permuting clock-rate, and it is inherently inefficient from the anti-alias filtering point of view. Indeed, with this algorithm, out-of-band tones are modulated exactly
258
as harmonics of the signal and are resulting, in certain conditions, in spurious signals inside the signal band. In the second algorithm, individual-level averaging, the D/A converter remembers the different D/A unit-element combinations used to synthesize a given digital code. Since the errors associated with each code are averaged, harmonic distortion is converted into white noise, which is highpass shaped. However, although interesting for wide-band low oversampling ratio applications, these techniques can lead to quite complex hardware implementations. This fact makes them less attractive with respect to other muhibit topologies, described below.
Microelectronics Journal, Vol. 25
3. Cascade modulator networks
In a recent w o r k we proposed a systematic approach to the design of cascade modulators [8] (Fig. lb). There we assume cascade modulators are built up from three basic noise-shaping blocks (Fig. 5), namely (a) zero-order multibit, (b) first-order single-bit and (c)second-order single-bit. Each block has two input signals, X ( z ) and Q(z), and two output signals, Y ( z ) and F(z) (Fig. 6), and is modelled with a set of four
X(z)
Y (z)
Q(z)
F (z)
X(z)~
Fig. 6. Modelling noise-shaping blocks.
Y(z)
transfer functions. These are S(z) and N ( z ) for the signal and noise transfer functions for the output, Y(z), and Fs(z) and FN(z) for their equivalent for the feedforward signal, F(z). Table 1 summarizes the whole set o f transfer functions of zero-order, first-order and second-order NSBs.
I F(z)
Type-A (a)
X(z),
Assume each of the noise-shaping blocks in Fig. lb is replaced by the corresponding model given in Fig. 6. T h e signal and noise transfer functions are then given by
Y(z)
TypicalDesigns (1)k=1
STF(z) = $1 (z) "gl • H~ (z)
~__!
(2)k=]/2
+ F s l ( z ) " h2 " S2(z) "g2 " H2(z) + . . .
F(z)
Type-A
Type-B
Co)
X(z)=
k la ~ klb
k2a k2b
~
Y(z)
and NTFi(z) = gi " N i ( z ) " Hi(z) TypicalDesigaxs (1)k*=1/2 (2) kla=klb=l/4 k2a=l,k2b=l/2
% TypeA
+ FNi(Z)" hi + 1 "Si + 1 (Z) "gi + I" Hi + 1(z)
TypeB
(c) Fig. 5. Noise-shaping blocks (NSB) used in cascade modulators: (a) zero-order N-bit; (b) first-order; (c) second order.
259
V.F. Dias et al./ A modulators for A/D converters
TABLE 1 Transfer functions of zero-order, first-order and second-order noise-shaping blocks NSB order
Feed type
S(z)
N(z)
Fs(z)
zero (0) first (F) second
A A B A
1 z 1 z ' z 2
1 (1 z -1) (1 - z -1) (1 - z 1)2
1 z 1 0 z - 9-
(S)
B
z 2
(1 -
respectively• Since L - o r d e r modulation means that S T F ( z ) = z -p, N T F i ( z ) = 0 for i = l , . . . , k- 1 and NTFk(z) = g k • (1 - z - l ) L, the following digital filters result: FNi(Z) Hi(z ) = _ _ _ Ni(z)
• (hi+l
"
Si+l(z)
"gi+l
z-l) 2
FN(z) ! m z
-1
-1 z 1 ( - 2 + z i) -1
0
3.1 Single-bit m o d u l a t o r s Figure 7 shows the two most promising cascade single-bit modulators available today [5, 9-11]• B o t h consist o f the cascade o f a second-order (S) and a first-order (F) modulator, and will be referred to as SAF and SBF (subscripts A and B stand for the type o f the first modulator). Table 2 summarizes the corresponding transfer functions
• Hi+ 1 (z) + hi+ 1 " Fsi+ 1 ( z ) . hi+ 2
xI
• Si+2(z) "gi+2 " H i + 2 ( z ) + . . .
z
)
'
-
-
h2 ~ • Sk(z)'gk
"Hk(z)
?
~
~
Y(z)
(7)
for the first (k - 1) filters o f the cascade, and (a)
(1 - z - l ) L Ht,(z) --
Nk(z)
(8) X
Iz) a
for the last one. In practical implementations, input scaling factors hi are set by the designer on the basis o f voltage swing constraints in the integrators. O n e possible way o f designing H i ( z ) filters and gi coefficients is as follows: evaluate H i ( z ) assuming hi = g i ~ - 1 ; then, calculate coefficients gi according to the following nile:
Y(z)
(b) i
gi=Hhj-' j= 1 260
(9)
Fig. 7. Cascade second-order first-order modulators: (a) S^F and (b) SBF.
Microelectronics Journal, Vol. 25
TABLE 2 Digitalfilters required to build third-order cascade modulators (S*F and S*FN topologies) Topology
H1(z)
S^F St3F
z 2(2-z
1)
z -1
H2(z)
Signal
Noise
gi
(1 - z - l ) 2 (1 - z - l ) 2
z 3X(z) z 3 X(z)
( g 2 ) ( 1 - z 1)3Q2(z ) (g2)(l - z - i ) 3 Q2(z)
gl = 1 g2 = 1/h2
Hi(z ) and scaling factors gi. T h e output signal in
1/8, Q2(z) becomes amplified and the m a x i m u m achievable resolution is limited to
S*F modulators is given by (1 - z - l ) 3
Y ( z ) = X ( Z ) " Z -3 "Jog2" Q 2 ( z ) .
(10)
RQ ~ 3.5- log2(M ) - log2(g2) - 3.5
This means a gain of 7/2-bit per octave of M, and a net loss of 1-bit per octave of the scaling factor, g2. Figure 8 shows the simulated SNlk of
where Q2(z) is the noise source of the second NSB and g2 is the corresponding scaling factor. Because h2 is smaller than unity, usually 1/4 or
SNR (dB)
I u I I
ii0 ZOO
.
u I I i
. 1.
.
.
I I I I
.; . .. . . . .. . .
I I I I
I ! I O .l . . . . . . . o !
90
. - L
80
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . a i
,
- - r
.
..
I I I n u. . . . . . .
. . . . . .
I
. . . . . .
,
.
. . .. . ..
. . A. .
f I O I a. . . . . . . i !
.
. . . .i. .
I i I I /. . . . . . .
"I . . . . . . .
i I
a
..
.
..
. ..=. . . . .. ... . . . .
I I I I £ . . . . . . i !
,
! I I o l
. . . . . . .
,~.=~
I I u I .o . . . I I I o o. . . . . u u
o
o 8-
,
I
i I I I
e- . . . . . .
r
o I I o
I I I I
o ~.
o
. . . . . .
I / ~ ~ _ _ / _ . . . . . .
% ./t
I I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
- - -
-i I . . . . . .
--
I I
.
.
.
.
.
.
.
.
.
I
:
'/v ,,
L
I
I I
~u
I
?
'
sL. 50
..
I I I I
(- . . . . . . . . . . . . . . . . . . . . . . . .
,
o
..~
u n I i
I o n o
I I
,
.
I I i I
,
I o u I
I o
60
I I I I
,
I I I I
70
. .J . . .
(11)
.
.
.
.
'I M=32 ,
40
"
. . . .
30
20
. . . .
re . . . . . .
~l . . . . . .
o i
i i
Ia I I !
- - - , 4 I I o
1. .
"--
-1--i o i
~I
.
.
.
.
.
'
sF
"--
A
.
J _ .
--k
. . . . . .
i. . . . . . .
r" . . . . . .
:
:
:
,
,
,
I
t
I. . . . . . .
~. . . . . . .
l
'
,
A. . . . . . .
1' . . . . . .
I l
i i
I .
"I . . . . . . .
I i
.I . . . . . . .
i. . . . . . .
' I I I
n I n
I0
-Ii0
-I00
-90
-80
-70
-60
-50
-40
-30
-20
-i0
0
Input (dB) Fig. 8. Signal-to-noise ratio in S*F modulators: g2 =
l/h2
= 2 andg2 = h2 = 1 in SAF and SBF respectively.
261
V.F. Dias et al./ A modulators for A/D converters
two S*F modulators for oversampling ratios M = 32 and M = 64. T h e SBF modulator is not scaled (g2 = h2 = 1), while the S^F one assumes g2 = 1/h2 = 2. Ribner et al. [14] report a thirdorder cascade S , F modulator that achieves 15.5bit and 15-bit at sample rates o f 2 4 k H z and 80 kHz respectively. Y(z)
3.2 Multibit modulators
As was first noticed by Brandt and Wooley [11], cascade modulators have the peculiarity that some of the D/A.converters see a path to the output that is highpass; these NSBs can thus be multibit without regard for non-linear effects. Candidates for multibit topologies are the ones in Fig. 7 where the quantizer and the D/A converter in the second NSB are multibit rather than single-bit [11]. The same digital filters of Table 2 are valid for multibit topologies, but in this case the m a x i m u m achievable resolution is given by RQ = 3.5. log2(M ) + (N - 1) - 3.5 - log2(g2) (12) where N is the quantizer and D/A converter resolution. Brandt and Wooley [11] report a 12bit at 2 M H z rate ( M = 24) using an S^F3 topology (subscript '3' stands for the n u m b e r of bits o f the second modulator). This illustrates the potential the P,A technique has for achieving m e d i u m resolution A/D converters at relatively high sampling rates. 3.3 Pseudo-multibit modulators
Cascade pseudo-multibit topologies have one key advantage over their multibit counterparts: they avoid the use of multibit D/A converters in the feedback loop [15]. Figure 9 shows one possible third-order cascade pseudo-multibit modulator. This modulator is built up from three NSBs, one Type B secondorder (SB), another Type B first-order (FB), and
262
Fig. 9. Cascade third-order pseudo-multibit modulator (SBFBO3).
a final zero-order multibit (ON). NSB1 and NSB2 together give the noise-shaping implemented, while NSB3 alone is responsible for the quantization noise power handled. T h e dashed line indicates the separation between these two parts, indicating also that they can be implemented in different chips or dies without concern for noise or distortion. Pseudo-multibit modulators are designed in exactly the same way as single-bit and multibit modulators, i.e. by means of eqs. (7) to (9). Table 3 summarizes the filtering functions Hi(z) and the corresponding scaling factors for thirdorder topologies. T h e output signal is given by Y ( z ) = X ( z ) . z -3 +g3" Q3(z) - (1 - z-l) 3
(13)
while eq. (12) above, with g2 replaced by g3, gives the m a x i m u m achievable resolution in bits. Digital filter H3(z) is a third-order differentiator, and is alone responsible for the shaping implemented over Q3(z); this is w h y disturbances that enter or are generated internally in the multibit quantizer can be ignored from noise calculations. Figure 10 shows simulation results comparing the S N R behaviour of S^F, SAF 3 and SBFBO3
Microelectronics Journal, Vol. 25
TABLE 3 Digital filters required to build third-order cascade pseudo-multibit modulators (S*F*ON topology) Topology
Hi(z)
H2(z)
H3(z)
Signal
Noise/Q3 (z)
SAFAO N SAFBON SBFAON SBFBi~JN
z - 2 ( 2 -- Z 1) Z-2(2 -- Z - i ) Z -1 Z -1
z - l ( 1 -- z - l ) 2 (1 -- Z - I ) 2 z-l(1 --z-l) 2 (1 -- z - l ) 2
(1 (1 (1 (1
z-3X(z) z-3X(z) z-3X(z)
(g3)( 1 (g3)(1 (g3)(l (g3)(1
modulators.
The
-- z - l ) 3 -- Z 1)3 --z-l) 3 -- z - l ) 3
SBFB(~3 m o d u l a t o r is not
I I
II0
I I
.
100
. . . .
90
o !
.
.
. . . .
. I
I
e
o
I
I I
I |
I I
I I
!
I.
,
,
,
,
,
,
,
,
t L . . . . . .
I I . . . . . . ! I I I
I
! I. . . . . . . I I I !
I L . . . . . . ! ! ! I
I I . . . . . . ! I I I
|
I I. . . . . . .
r . . . . . . 1 I i i r . . . . . . I I
T . . . . . . I ! I I
. . . . . .
I
.
.
. . . . . . .
I
'
I
. . . . . .
'I
I
i. . . . . . . I I ! i r
. . . . . .
I i
'
. . . . . . . . . . . . . . . . . . .
', S g I : B O 3
.......
,'-#
I I. . . . . .
.
I ~ _ _ _~
.
1
I I I
. . . . . .
~
.
.
.
.
.
.
.
_~
.
I
-ii0
1
.
.
I i
.
.
.
.
.
.
.
.
I. . . . . . .
i" . . . . . .
I
I I
~
-I
.
.
! I
I
r ! I I I
.
.
~,~
' .
.
.
.
.
.
,
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
4
r
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
*
. . . . . .
"1 . . . . . . .
,.
.
.
.
.
.
.
.
I I
I I
I I I. . . . . . . I I
I
I
:
.
.
.
.
.
.
.
.
.
.
I I
i- . . . . . .
~
I I
I I
I I . . . . . .
•
. . . . . .
-I . . . . . . .
I I
)
I
I
I. . . . . . . I
I. . . . . . . I
I . . . . . . i
.
.
.
J . . . . . . . I
.
.
.
.
.
.
.
.
.
.
i
I
|
t
)
I
I
I
I
I
I
I
I
. . . . . .
I
~ . . . . . . .
.
.
.
i- . . . . . .
.
.
+
.
.
. . . . . .
I I I
I. . . . . . . . . . . . . . . . . . . I
t I
I
.
I
I
) I
,. . . . . . .
,. . . . . . .
T . . . . . .
T
i
I
I
I
I
!
I
)
I I
I I
I I I
I I I
I I I
I I I
I I 1
I I I
I I I
-90
-80
-70
-60
-50
-40
-30
]00
. . . . . . .
I
.
.
SAF3
. . . . . .
I I
.i . . . . . . .
.
'
*
J _ _ _
' .
I
I
.
. . . .
!
.
I
.
T
I t
.
I
.
T - I I i I
I
.
I
.
. . . . . .
'
I
,.
I
,
~
I
i'" I I
I
i
]U
.
"l . . . . . .
I
:y .
i
I
I I .
,
I
I I
.
~
I
I I .
I
I L I t
II
", .
I I
I
',
,.
¢
, ' . . . . .
J . . . . . . . I I I I
T
'I .
--'~"
I
[.
gl = 1
g2 = 1/h2 g3 = 1/h2h3
.
-I . . . . . . .
t t
. . . = ~
.
i. . . . . . . I i ! i
! I
50
20
I I
I
. . . . . . . . . . . . . . . . . .
30
I |
I
r . . . . . . I I
......
i I
I I
J . . . . . . . I I I I
3 3 3 3
.
I I
60
40
.
|
r
. . . .
I I
.
I
I I I I
70
I I
.
I I
.
80
I I
.
- z-l) - z-l) -z-l) - z-I)
Figure 11 summarizes the state-of-the-art in IC implementations of high-order single-stage and cascade modulators. The range of application of the sigma-delta technique spans from very-highresolution and low sampling rates such as 20-bit
scaled and shows an improved 12 dB performance respective to its SAF 3 counterpart; in practical implementations scaling should be applied to S ' F ' O N modulators as well.
SNR (dB)
Z 3X(z)
gi
*. . . . . . . . . . . . . .
-20
T
......
-Ill
0
lnpul (did Fig. 10. S N R in cascade single-bit, m u l t i b i t a n d p s e u d o - m u l t i b i t modulators: g2 = g3 = 1 in SBFuO3, g2 = 1/h2 = 2 in SAF3 a n d g 2 = h2 = 1 in S^F.
263
V.F. Dias et al./ AA modulators for A/D converters
Rbit
Co
2o
18
D
=ill
16
Fig. 12. N o n - i n v e r t i n g
[]
14
r
12
I(z) I
//
0.5
I
I
I
I
32
64
128
256
I
I
I
I
I
512 1024 2048 4096 O u t p u t Rate (kHz)
[]
IC
S=single-stage, Cl=cascade l-bit, CM=cascade multibit
O
Predicted
CPM=cascade pseudo-multibit
Fig. 11. State-of-the-art in IC implementations of singlestage and cascadesigma-deltamodulators. at 500 Hz, passing through digital audio and up to 12-bit at 2 MHz. With the advent o f pseudomultibit topologies (CPM) a shift upwards in bandwidth is to be expected, making possible the realization o f 12-bit at 4 M H z , 14-bit at 1 M H z and 16bit at 150kHz sigma-delta A/D converters with available sub-micron silicon technologies. This is an increase o f a factor o f two in the state-of-the-art.
4. Integrator gain and pole error effects In the following, integrator gain and pole error effects in cascade and single-stage modulators are analysed. Integrator gain and pole errors are responsible for spurious noise transfer functions that limit the dynamic range.
4.1 Integrator model Let us consider the switched-capacitor integrator in Fig. 12 and define A0 as the amplifier dc gain and r = CffCo as the ratio between the sampling and integrating capacitors. The integrator transfer function is
264
J._J,"
m
=
switched-capacitor integrator.
-- ~)Z-1
(14)
1 - (1 - 6 ) z -I
where e and 6 are the gain and the pole error, respectively, and are given by _~ Ar + (1 + r)/Ao(Ao >> 1) and 6 ~_ r/Ao (Air is the mismatch assumed between Cs and C0). The analysis that follows considers gain and pole errors separately and o f small value; hence we shall assume ~ << 1 and 6 = 0 for the analysis o f the gain error, and c~ << 1 and 0~= 0 for the analysis o f the pole error; we shall also assume f <~ Bo << M F ,
4.2 Cascade topologies Gain and pole errors in NSBs are modelled as indicated in Fig. 13 [8]. We define two sets of transfer functions, respectively for gain (a) and pole (b) error analysis, whose values relate the NSB inputs X(z) and Q(z) to the spurious outputs Y~,(z) and F=(z) for (0~ # 0, ~ = 0), and Ya(z) and Fa(z) for (6 ¢ 0, ~ = 0). A complete description o f a given NSB is thus achieved with three sets o f transfer functions, one nominal for its ideal behaviour and two spurious ones that take integrator gain and pole error effects into account. Consider the example o f a Type B first-order NSB (Fig. 5b). Using (14) with ~ # 0 and 6 = 0 we obtain
Y(z) ~ X(z) . z -1 + Q(z)- (1 - z -I)
(15)
and
F(z) ~ X ( z ) . z -1
-
Q(z). (1
-
~z -1)
(16)
Microelectronics Journal, I/ol. 25
X(z)
for the output and feedforward signals respectively, where less significant terms have been discarded. Equations (15) and (16) indicate that in a Type B first-order modulator So(z) "~ O, No(z) ~-- O, Fso (z) ~ 0 and Ffo (z) ~-- o~z- 1. Similarly, for & # 0 and 0~ = 0, we obtain Sa (z) ~ 0, Na lz) -~ 6 - z -1 , Fsa(Z)'~O and F N a ( Z ) - - ~ - - 6 . z - . Table 4 summarizes the whole set of spurious transfer functions in first-order and second-order noiseshaping blocks. Delays and signs have not been considered because they are not significant in the noise calculations.
~z)
Q(z)
{z)
Tables 1-4 allow a quick analysis of integrator gain and pole error effects in cascade modulators to be made. Consider the example o f a thirdorder S*F modulator (Fig. 7) whose integrators have a gain error, ~. With the help of Table 4, we identify the only signficant spurious path as being the one that includes FN(z) in the first NSB, S(z) in the second NSB, and the filter H2(z). Because H2(z) is a second-order differentiator the excess noise respective to (2) is
(a)
x,z,
i
Q(z)
PQ~
--
167r4 1 -0~ 2 15 M~
(17)
A similar analysis can be carried out for the integrator pole error (6), and we obtain
(b)
PQa
Fig. 13. M o d e l l i n g integrator gain and pole e r r o r in l o w o r d e r n o i s e - s h a p i n g blocks: (a) gain error; (b) pole error.
TABLE 4
-
4g 2
1
9
M 3
--
52
(18)
as the excess noise respective to (2).
Spurious noise transfer functions in N S B s Gain error
Pole error
Order
Feed
S= (z)
N= (z)
Fs~ (z)
FN=(z)
Sa (z)
Na (z)
Fs~(z)
FNa(z)
First (F)
A B
~ 0 ~ 0
~-, 0 ,-~ 0
~ 0 ~ 0
~ o~ ~ ~
~ 0 ~ 0
~3 ~a
~0 ~0
~0 ~5
Second (S)
A B
~ 0 ~ 0
,-~ 0 ,-~ 0
,-, 0 ~ 0
~ 40~ ,-~ 4~
,- 0 ,,~ 0
~ 2 6 ( 1 - z -1) ~ 2 6 ( 1 - z -*)
~0 ~0
~2~ ~2~
265
V.F. Dias et al./EA modulators for A/D converters
4.3 Single-stage topologies It is well-known that single-stage modulators exhibit a small sensitivity to component mismatch and amplifier non-idealities [1]. Typically, matching tolerances as large as 10% and amplifier gain values as low as 50 dB can be used in Type 1 and Type 2 topologies without significantly degrading the modulator performance.
Figure 14 shows eqs. (17) and (18) added together with (2) for N = A = 1. These plots indicate that gain and pole errors have to be smaller than M -1 and M -2, respectively, to ensure negligible excess noise. Consider now the case of a third-order pseudomultibit modulator (Fig. 9) where the sources of excess noise are three, namely the first, second and third NSBs. Consider first NSB2 and NSB3 together with digital filters H2(z)= ( 1 - 2 - 1 ) 2 and / - / 3 ( z ) = ( 1 - z - l ) 3. Because H2(z) and /-/3 (z) are high-order differentators, in-band noise or distortion coming along with their input signals can be discarded. Thus, only the excess noise due to NSB1 has to be considered, as in the single-bit modulator analysed earlier. Hence, we can conclude that single-bit, multibit and pseudomultibit topologies are all equivalent from the point of view of integrator gain and pole error effects, and that eqs. (2), (17) and (18) can be used in each case. Simulation results, shown in Fig. 15, illustrate this conclusion for the case of an SBFBO3 modulator; gain error is given in percentages (1% = - 4 0 dB) and pole error is given as a function of the amplifier dc gain (8 "~ r/Ao).
Let us consider the modulator in Fig. 2b and assume all coefficients U i a r e zero (note that coefficients Csi do not affect NTF(z)). U n d e r these conditions, NTF(z) is given by NTF(z) =
1
1 + ~ Ag Ii(z)
-
(1 -
z
D(z)
1)L
(19)
i
where (1 - z -1)a and D(z) provide, respectively, the shaping and the stability desired. The denominator D(z) in (19) inserts no poles in the signal band; in the low frequency range D(z) simply amplifies or attenuates the shaping defined by the numerator. Assume the integrators are affected by a gain error, as indicated
VQ. %~ (dB) --70
--80
.............. 3.2.---!........................... --90
........
1100
i ..........
: .........
......
........
--110
-120
....................................
-90
-80
i .........
-70
-60
-50
i .........
-40
I .........
-30
-20 8,c~ ( d B )
Fig. 14. In-band quantization noise power m S*F modulators as a function of integrator gain (c~)and pole (3) errors.
266
Microelectronics Journal, VoL 25
I I I I
Ii0 SNR (dB)
I00
..I.
. . . . . .
I I I I .I . . . . . . I I I
80
70
.I . . . . . . . I I I I
,
90
I I I I
. . . . . . . . .
J . . . . . . l I I I
. . . . . . . . .
4 . . . . . . . . . . . . .
--I"
. . . . . . I
, , I
I I I ! 'I . . . . . . I
, , I
60
...................,
50
.........................
J . . . . . . .
"I . . . . . . . I
, ,I
I I I I I.
. . . . . .
I I !
30
. I I I
It_ . . . . . .
i I I I I
~ . . . . . .
;" . . . . . . . . . . . . . .
r-' . . . . . . I
I I
.
, . . . . . .
~ . . . . . .
I I
I I
I
' . . . . .
I I I I,- . . . . . . I I I I i. . . . . . .
I
I I
J . . . . . . . . . . I I ! I
I I
I I I I I I ,I
. . . . . . .
. .. .. .. .. .
I I
I I I I p . . . . . . I I I I i.
I
, ! I
-i00
-90
-80
-70
-60
!......
ratio o f an
Consider now the case o f non-zero Bi coefficients. These coefficients lead to transmission zeroes in the numerator, while no specific action results from their presence in the denominator. Assume these coefficients are affected by a mismatch ABi. Transmission zeroes will change slightly with respect to nominal conditions, but
- - . , I
I T . . . . . . I I I I ÷ . . . . . . I I I l J. . . . . . .
"1 . . . . . . . I I I I ,,t . . . . . . . I I I I d . . . . . . .
I. . . . . . . I I I I I. . . . . . . I I I I I. . . . . . .
I" . . . . . . I I I I I,- . . . . . . I I I I I.. . . . . . .
-50
-40
-30
-20
T I I l I -*. I I I I JL I I I I I I I I I I
-i0
0
I n p u t (dB)
SBFBO3 m o d u l a t o r
in (14), and that coefficients Ai are implemented with a mismatch Z£4i. It is easy to show that the numerator in (19) is unchanged while the denominator is slightly changed into D'(z). A key point is that D'(z) does not introduce spurious low-order-shaped noise transfer functions, as was the case with cascade modulators.
I I I I
5%
(a)
Fig. 15. S i g n a l - t o - n o i s e
•
I I
J .......
I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I I I I I
--II
!
I I
,
',
! I r . . . . . . I I ! I t- . . . . . . I I I I I. . . . . . . I I I |
I I I I I. . . . . .
.-|
:__.__/_ i ......
10
-II0
I I
,
I I
I I "1 . . . .
I I J . . . . . . .
.II . . . .
.
,,
. . . . .
20
.
I I I I ..I . . . . . . .
I I I I f" . . . . .
,Id.,O.l%, ,, \
S
I
I I I I #. . . . . . .
' SBI~ JL ~ 1¢.13 °l I I ~ _ --~ I
I I I
40
! I I I I. . . . . . .
w i t h (a) integrator gain and (b) pole errors.
will not be removed; optimal placement becomes non-optimal. However, no spurious paths are created for the quantization noise. Simulation results, shown in Fig. 16, prove this conclusion for a Type 2 modulator with an optimal placement o f one pair o f transmission zeroes. The following mismatches have been considered: &/lis in the range 1 ( ~ 1 0 % and AB/s < 30%. N o w we analyse the effect o f an error in the integrator pole. W e shall refer to the same modulator as in Fig. 2b and assume an error 6L in one o f the integrators, say the one at the end o f the cascade. After expanding the summation in (19), we obtain
267
V.F. Dias et al./ZA modulators for A/D converters
ii0 SNR
(dB)
100
90
i i i i
i i i i
I i i i
i i i i
I i i
!'
t
t ' t
!'
I'SBFBO3
; " J
,
,
,
, M=6,4
,
., . . . . . . . ! t I !
,. . . . . . . ! l i I
,. . . . . . . ! i t
, . . . . . . t o t !
., . o ! t i
4.
("
T
"1 .
,. . . . . . . M l l - - - r
70
.
.
i
• . . . . . . ! o t I
!
80
!
I i i !
.
.
'
.
.
.
.
.
I
I
I
i
I
i
i
i
i
i
- - - r
. . . . . .
I
. . . . . .
.
.
o
.
.
. . . . . .
.
r
. . . . . .
i i i
i I i
i
i
t ' i
M'
l'
,
,
i
. . . . . .
t , .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
,__ ! i i l
.
.
.
1
.
I
I
I
i
i
i
i
I ! i
i
i
i
i
i
i
-1 . . . . . . .
~
. . . . . .
r
.
.
.
.
.
.
.
.
.
.
.
.
i i
i. . . . . . .
P
. . . . . .
i.
. . . . .
i
i
i
'I
60
,
I'
i.
. . . . .
l
i
Id "l 1 0 0 d B #.8 0 d B
i
I'
'I
'I
4 . .
-
. . . . .
I
i
i
I'
'I
'I
I. . . . . . .
I. . . . . . .
i
. . . . . . . .
. . . . .
50
........
i t f. i i
. . . . . . . . . . . . . . . . . .
.
.
¢
.
i X .
.
i .
.
......... .
.
.
- ' - r
. . . . . .
iI
I
.
.
.
# I
.
.
.
.
.
.
.
i .
/---'
20
.
.
i i
/:
.
.
.
.
,
.
r
II
.
.
.
.
.
.
.
.
i
.
. .
.
.
. .
.
.
' .
. .
.
.
.
.
.
'
...........
. . . . . .
II
T
. . . . . .
|I
I
"1 . . . . . . .
II I
P
II
II
. . . . . .
T
. . . . .
II
I
I
I
i i- . . . . . .
•
i i. . . . . . .
i i- . . . . . .
i ÷ . . . . .
i i
i i
l i
l i
l i
i i
i I
i i
i i
i i
i I
I i
. . . . . .
I
I. . . . . . .
i I
i i-
.
i i I
.
I .
.
o i .
I
! . .
.
/
.
I
30
.
. i
! !
40
.
i . . . . . .
....................
i .4 . . . . . . .
...............
i i
...... ,
.
.
.
.
.
10 ,
i t i
-ii0
-i00
-90
-80
-70
-60
-50
-40
-30
-20
(b)
-i0
0
I n p u t (dB)
Fig. 15. Signal-to-noise ratio of an SBFBQ)3 modulator with (a) integrator gain and (b) pole errors.
NTF(z) -
(1 - z - t )
D'(z)
L
+
fL(1--Z-1)
D"(z)
L-1
5. Thermal noise and settling (20)
Apart from the fact that D(z) has been changed into D"(z), an additional path has been created for the quantization noise. This path provides only ( L - 1)-order differentiation of the quantization noise; for this reason pole errors (3) lower than M -1 should be used. This same conclusion can be extended to mismatches ai over the remaining integrators in the circuit. T o illustrate this result, Fig. 17 shows the simulated SNP,. behaviour of the same modulator as in Fig. 16 for different values of the amplifier dc gain (M = 64).
268
In the following section we shall consider switched-capacitor ~ A modulators since they are probably the ones most often used for implementing high-resolution and wide-band A/D converters [16-18]. The design o f the first integrator in high-resolution applications requires large sampling and integrating capacitors, while the load capacitor due to the following stage is negligible. If we assume single-stage amplifiers, such as cascode, folded cascode etc., which have a single high-impedance node placed at the amplifier output, we find that the integrator bandwidth (BW) is given bygm/Cs, wheregm is
Microelectronics Journal, Vol. 25
ii0
I00
90
80
70
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I l I. . . . . . .
I I I. . . . . . .
I I • ......
l I I. . . . . . .
SNR (dB)
I
......
. . . . . .
I I 4 ......
I
I
I
,
,
,
I
I
I
,
,
,
i.
60
.
.
.
.
.
50
30
.
.
.
.
.
-e .
I I I
I I l
I
I
.
-ii0
.
.
.
I
'
'
I
I
I
I I I
"I"
4 . . . . . .
' I
,
2 .......
I
.....
'I
I I- . . . . . .
I 4
'~
.
i-
.
.
.
.
.
.
Id.
.
.
.
.
.
.
! t. .
.
.
f .
' ' . I I, ~ ~~
.
.
.
.
',l ,
=
. . . . . I I I I
.
.
.
.
I I I
I ~ _
I-. . . . . . . . . .
"''-
I I
I I
I I
T
i
T . . . . . .
I I I
I.
.
.
.
I I .
.
.
I" .
,
,
'
I
I
I
,
', : .........
i
"= . . . . . . . . . . . . . .
'I
'I
I I- . . . . . .
! ~- . . . . . .
I .I. . . . . . .
I
I
I I I
'I
'I
'I
I I
I I
I I
I
I
I
I
,~ . . . . . .
f ......
; ......
,---
I
I
,I
I I
I I
I I
,
e
,
I. . . . . . . . . . . . . . I
I I I I
M
I
I I
| I i'-'I
____, . . . . . .
T
.
I ~i
'I
I
.
I I I
'I
I I
.
I L. . . . . . . I
'I
......
4-10%
.
I I. . . . . . .
I .a . . . . . . . I
T ......
1
.
I I I
I I I I . . . . . . .r
~
.
I I I
I I I I . . . . . . . T . . . . . . . . "1
d
~ .......
~ . . . . . . . I
.
l
.......
I
.
~5~
# /~7
r- .
I I I
"~
___,
.
.
~
Tf
'
I I
I . . . . . . . . . . . I-
I ~ I ~
'I
.
.
:......
= I I I I
.
.
.a-.
,
......
.
I
I
I
I
~
'
4
#e# - ~I . . . . .
I
I I I
I
I
/-
.
'
=
.
.
,
L
.
.
I
.......
.
.
'
'i
.
,
I
I I
. . . . . . . . . . . . r
.
,
,
I i
I
I0
, I
I !
I
20
I
~
r
.......
I
i I
I s I I
40
~
!
,
.
I I .l . . . . . . .
*,
. . . . . . . . . .
. . . . . . . . . . . . . . . . . . .I . . . . . . . . . . . . . . .
I. . . . . . .
. . . . . .
M=64
I I I. . . . . . .
I
i I
r
. . . . . .
T2-1Z
,~
l
. . . . . . . . . . . . . .
.
I I ..I . . . . . . .
4 . . . . . . . I I I
'
j
I
. . . .
.......
J
i
. . . .
I I
I. . . . . . .
I I-. . . . . . .
'I
'I
I
I I
I I. . . . . . .
I
I. . . . . . .
i
I
I I
I
~.
,
I I
L
I
I +I I I
'
,I
'. . . . . . .
t
I I I I T"
i I
......
"i
,
,
,
,
,
,
,
,
,
!
-i00
-90
-80
-70
-60
-50
-40
-30
-20
-i0
0
Input (dB) Fig. 16. Signal-to-noise ratio of a fourth-order modulator for different values of the mismatch between the filter coefficients (T2-1Z, Type 2 with one pair of transmission zeroes).
the amplifier transconductance and Cs is the sampling capacitor. Thermal noise and settling error are responsible for two bound limits in EA modulators: maximum achievable dynamic range, on the one hand, and maximum allowable oversampling frequency, on the other. Noise sources in SC circuits are M O S switches and operational amplifier broad-band and flicker noise. Flicker noise can be reduced through an increase in the gate area of the amplifier input transistors, or by using special integrator schemes such as chopper stabilization and
offset compensation [19]. In contrast, broadband noise can be reduced only by increasing the sampling capacitor or the oversampling ratio, increases that unfortunately degrade the integrator settling behaviour. Incomplete settling, due to a combined effect of slew-rate (SR) and bandwidth, implies loss of proportionality between input samples and settling error, a fact that leads to an increase in the noise power. Hence, for a given technology, the maximum achievable resolution is mainly a trade-off between thermal noise, dictated by M and Cs, and settling error dictated by SI~ and BW.
269
V.F. Dias et al./CA modulators for A/D converters
I ! I I
Iio
SNR (dB)
1 ¢ I I
I ! I I
I ! I I
I I I I
I
I
I I_ . . . . . . I I
M=64 I L . . . . . . I I
I I I I
I ! I I
I I I I
I
I
'
:
I
/
I00
.
.
I
90
80
. . . . . . .
.I . I. . . . . . .
. . . . . . . . . . . . . .
I
.
.
I . J . . . . . . ! I
.
.
.
'
1 .
.
.
.
=,I
. . . . . .
. .
.
.
.
.
n]z'
'
', JL . . . . . . I I
. .
I I i I
.
1-
.
.
.
.
.
! ! i I
.
~
.
.
.
.
.
I I i I
~
.
.
.
.
.
I I I I~
_
.
.
I I. . ~ 1
.
.
.
.
.
.
.
.
JL_.. I I
/
_
] ~ '
,
.
.
'
.
.
.
.
.
,
b .
.
.
'
.
T-"
I i i I
r I I
~1~
~
,
:
'
I J . . . . . . . ! I
I ! ~
I I
I i i I
70 i
.'
I
i
.
.I'
I
.
I
. 'I
60
i
za.
60- - dB Jo ~
_ _ _
!
i
I
.
do dB
.
I
. . . . .
l I
40
. . . . . . . . . . . . . . . . . . . . . . . .
I
I ~
....... r ...... !
i I I
1 ...... o ~ I ~ • I I ~
-, ~
i
i
',
',
I
4.
I
!
i
I
I
I ,
I I
I I
i i
I I
I
I
I
I I I I I -_.-, T--'" I I I I
I I I I
! I I I I .., T I i I I
I
I
. . . ._ •r ....... . . .
"1
.
i
I t ! I I
_~_.;.,c_
~
. ',
|
40 dB
I 50
: .
. .
I I I I
...... . . .
. . .
I I I I
I I I I
I I ! ! ,_, r I I I I
I
!
I
-,"I ....... . . . . . . .
,I.. .. .. .. . . . .. .
...... . . .
. . .
J
30 ¢
20
....... [ ...... !
I
j
!
::
!
I
I
! I
I
I
I
I
I ! I r . . . . . . I
i I I
I I I T . . . . . . I
I I I
I I I £' . . . . . . I
I I I T .... i
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ _ I i I I i I
10
I
I
I !
I ! I
I
i
I I
I I
I I
I I
I I
I I
I I
I I
-90
-80
-70
-60
-50
-40
-30
-20
-i0
:
-I00
..-,
I
I I
....
-Ii0
i ....
i
I ! I i. . . . . . . I
i
/
i I I "I . . . . . . . I
¢ I
.
.
.
.
r
. . . . . .
I
.
.
.
3. .
. . . . . .
0
Input (dB)
Fig. 17. Signal-to-noise ratio of a fourth-order modulator for different values of the amplifier gain (T2-1Z). 5.1 Thermal noise Thermal noise in SC modulators is c o m m o n l y evaluated from the simplified relationship Pth = kT/C~M, which accounts only for the noise power due to sampling switches. This relationship can be applied to SC integrators in which the noise of integrating switches and operational amplifiers is heavily filtered by the amplifier itself, giving a negligible contribution to the overall noise power. This is, however, not the case with high-resolution and wide-band P~A modulators, where the need o f speed optimization leads to particular SC integrator designs. In such applications a more accurate formulation o f the broad-band noise power is
270
required. The following relationship was proposed by the authors in a previous work [16]:
PTh
_
1
kT
M C~
[41 2+
(1+c~)
(21)
This relationship accounts for the noise o f sampling and integrating switches as well as the amplifier broad-band noise. Equation (21) was derived assuming transconductance amplifiers, as mentioned above, with the frequency compensation performed by a series o f sampling and integrating capacitors. Parameter c~ is a noise coefficient which characterizes the particular
Microelectronics Journal, Vol. 25
amplifier and is dependent on the ratio between the transconductance o f load and input transistors. For an optimal design (0c << 1), eq. (21) leads to a 10/3 increase in the in-band noise power. This means a 5 dB increase in the thermal noise floor, i.e. a loss of about 1 bit in the modulator resolution respective to that given by the simplified equation Pth = k T / C ~ M . For instance, a I pF sampling capacitor and an oversampling ratio M = 100 lead to a thermal noise power o f ~ - 1 0 0 dB, which, on its own, defines an upper bourfd limit o f ~-,16bit to the maxim u m achievable resolution. An 18-bit m o d u lator would require an ~ 1 6 p F capacitance, while a 20-bit one would require a 2 5 6 p F sampling capacitor. 5.2 Settling error Settling error in E A modulators has been largely studied via computer simulations [1, 14]. Software tools available today [20, 21] provide users with accurate behavioural models which, with other facilities, allow the effects of slew-rate and bandwidth to be analysed. Such models consider both slewing and linear-mode settling conditions, which generally occur in real operation. Typically, results obtained from the use o f finitesettling models indicate that settling-error effects increase rapidly with oversampling frequency. In a recent work we proposed a simplified relationship for evaluating setding-error effects on HA modulators [16]. After some algebraic simplifications, that relationship can be written as
P~t = 35 •
- 27.BW-
- 20 • log10
10.1ogl0(M
in normalized values with respect to the oversampling ratio, i.e. B W = B W / M F ~ and S R = SR/MF~ with S R in V/s and B W in Hz. Equation (22) is plotted in Fig. 18 as a function of (a) B W and (b) SR. For a given slew-rate the excess noise decreases linearly with integrator bandwidth; conversely, for a given bandwidth the decrease of Pst with slew-rate saturates for high values o f SR. This means that the integrator is never slew-rate limited, and the case for which the model was developed is no longer valid. Simulations made with T O S C A [21] indicate that eq. (22) is a good predictor of settling-error effects for B W and S R values___larger than three, and that for a good design S R should be larger than B W and both larger than five. 6. Discussion
In this section we consider three different applications o f a third-order pseudo-multibit topology. These are intended to achieve 12-bit at a 4 M H z rate (Design 1), 14-bit at a 1 M H z rate (Design 2) and 16-bit at a 1 5 0 k H z rate (Design 3). T h e design methodology follows from eq. (12), which gives the m a x i m u m achievable resolution as a function of the quantization noise, eqs. (17) and (18) for the excess noise due to gain and pole errors in the integrators, and eqs. (21) and (22) for the excess noise due to thermal and settling effects; these are repeated in (23) to (26), expressing the resolution in bits of an S*F*ON topology with scaling factors gl = 1, g2 = 1 / h 2 = 4 and g 3 = 1/h2 • h3 = 4. RQ --~ 3.5 - log2(M ) + N - 6.5
) - 27
(22)
where the so-called excess noise due to settling error is expressed in dB as a function of bandwidth and slew-rate parameters; for simplicity's sake, bandwidth and slew-rate are expressed
RTh
"~
(23)
0"5" log2(M ) + 0.5 • log2(CpF ) + 12.4 (24)
R= ~_ 2.5 • log2(M ) - 3-33. log10(00 - 4
(25)
R~ -~ 1.5. log2(M ) - 3.33. log10(&) - 1.9
(26)
271
V.F. Dias et al./ A modulators for A/D converters
-50
%, (dB) -70
__J
...............
.J. . . . . . . . . . . . . . .
.J. . . . . . . . . . . . . . . . I I I I I I
SR. =2
!
I I I I
-90 ---I
. . . . . . . .
=1 .
.
.
.
.
.
.
.
.
.
.
.
.
"1 .
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . . . . . .
\,
!
SR =4 I" !
-Ii0
.
I
.
.
.
.
.
.
.
.
.
.
.
.
.
I I I I
~'~ -130
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
=lO .
.
.
.
. . . . .
.
ii . . . . . . . . . . . .
-150
2
3
4
5
6
BW
These four relationships are depicted in Fig. 19 as a function of the oversampling ratio. Where settling is an issue, we shall assume SR(v/~ ) ~>BW(Hz)>~SMF~. For a real prediction of the noise performance of HA modulators, technological constraints have to be considered which set a relation between the allowable bandwidth and sampling capacitor size. As mentioned before, high-resolution GA modulators use single-stage amplifiers where the effective bandwidth (BW) during the integrating phase is inversely proportional to the sampling
272
(a) amplifier bandwidth and (b) slew-rate.
capacitor. Conversely, wide-band modulators require very high values of B W with small sampling capacitors, making the non-dominant pole and the capacitor of the following stage important parameters. Figure 20 shows one possible speed characteristic of a sub-micron silicon technology. Three particular operating points of Fig. 20 will be considered here: C~ = 0.25 pF and B W = 2 5 0 M H z for Design 1; Cs = I pF and B W = 150MHz for Design 2; and C~ = 3pF and B W = 5 0 M H z for Design 3. This sets the
Microelectronics Journal, Vol. 25
-501
PSt
(dB)-70 . ~ ~ : ~
...................
a................................
-90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
............... i.............. , ............... ] I !, I I I I I
...... -130
I ,
.=4
I I I I a
~
. . . . . . . . . . . . . . .
BW
I I, I I I , I
,. . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
a ...............
a ...............
=6
-150
I 2
I
I "l
I
I
I
I
I
i
I
I
I
I=I
I
I
I
3
I
i 4
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
l
I
5
SR
(b) Fig. 18. Settling-error noise power in switched-capacitor modulators as a function of (a) amplifier bandwidth and (b) slew-rate.
allowable oversampling frequency to 50MHz, 30 MHz and 10 MHz, respectively, in Designs 1, 2 and 3. One basic rule of the design methodology is that wide-band modulators are mainly limited by quantization noise (low oversampling ratios and wide-band amplifiers), while highresolution modulators are mainly limited by thermal noise (large sampling capacitors and slew-rate amplifiers). First, consider Design 1 (quantization noise constrained). Twelve bits of resolution at a 4 MHz rate set the oversampling ratio at 12 and
the topology to S*F*O7 (eq. (23) and Fig. 19a); Figs. 19b-d indicate that neither thermal noise nor excess noise due to integrator gain and pole errors constitutes a limit. A 60 dB operational amplifier and a 0.25 pF sampling capacitor with 0-5% matching accuracy is enough to guarantee the performance desired. Consider now the opposite case of Design 3 (thermal noise constrained). Sixteen bits at a 150 kHz rate set the oversampling ratio to 64 (MFs = IOMHz) with a sampling capacitor of 3pF (eq. (24) and Fig. 19b). Equation (23)
273
V.F. Dias et al./ A modulators for A/D converters
Rbit(Th)
Rbi t (Q) 9
7
18
5
3
N=I
....--- 64
18
/16 /
16
4
~
16
Cs=l pF 0.25
D2
14 12
14 O D1
12
3.6 4
5
6
@
D1
I
I
I
I
I
I
7
3.6
4
5
6
7
Log 2(M)
Log 2(M)
(a)
(b)
Rbit(c0
Rbit(8) 0.01%
16 18 ~
o
D
0.1%
2
cx=l%
-4 10
18
-3 10
/
16
• D3
8 =10-2 14
14
12
12
3.6
4
I
I
I
5
6
7 Log 2(M)
(c)
|
3.6 4
5
6
7 Log 2(M)
(d)
Fig. 19. Resolution in bits in cascade S*F*C)* modulators as a function of the oversampling ratio: (a) quantization noise; (b) thermal noise; (c) and (d) excess noise due to integrator gain and pole errors respectively.
(Fig. 19a) indicates that an S * F ' O 2 topology guarantees 12 bit, while (24) and (25) indicate that 1% matching in the integrated capacitors and 60 dB amplifiers are sufficient to reach the desired performance. Design 2 is mixed quantization-thermal constrained. Starting with a 1 pF sampling capa-
274
citor, we obtain that the m a x i m u m allowable oversampling frequency is 3 0 M H z and that a m i n i m u m oversampling ratio o f 16 is required to o v e r c o m e the thermal noise constraint. This limits the output rate to about 2 M H z . From (23) we see that an S * F ' O 8 modulator is required, i.e. quite a complex design. A reduction in the quantizer complexity to about 4 bit
Microelectronics Journal, Vol. 25
simulation obtained with T O S C A , using the parameters o f Table 5.
Cs(pF)
D3
7. Conclusions 132
0.5 I D1 0.25 I SO
I 100
I 20O
BIN
(MHz)
Fig. 20. Integrator speed characteristicof sub-micron silicon single-stageamplifiers. (S*F*O4) is possible provided an oversampling ratio o f five octaves is allowed. This increase in M reduces the m a x i m u m allowable output rate to 1 MHz, giving however the possibility to decrease the sampling capacitor to 0.5pF and increase the integrator bandwidth. This procedure can be iterated until a good trade-off between complexity and performance is achieved. O n e possible solution consists o f using an S*F*Q) 4 topology with a sampling capacitor o f 0.75 pF to obtain 14-bit resolution at a 1 M H z rate. Table 5 summarizes the design parameters for the three designs considered. Figure 21 shows a
This paper has reported a comparative study o f HA modulator topologies which are suitable for high-resolution and wide-band A/D converter applications. W e have revisited the single-stage and the cascade architecture and stressed the fact that cascade modulators have optimal noiseshaping, are easy to design, are unconditionally stable and are relatively insensitive to integrator gain and pole errors. W e have concluded that cascade pseudo-multibit topologies provide designers with three degrees o f freedom, namely the oversampling ratio, the noise-shaping order and the quantizer resolution, all o f this without requiring N-bit D/A converters. W e have also concluded that cascade pseudo-multibit topologies have increased design, application and testmg flexibility, allowing external multibit quantizers to be used without concern for noise or distortion. Finally, we have described the design procedure o f three pseudo-multibit topologies. The speed characteristic o f an SC integrator has been derived from the parameters o f a modern C M O S process. O n this basis we have shown that pseudo-multibit topologies have the potential o f achieving 12-bit at 4 M H z , 14-bit at 1 M H z and 16-bit at 150 kHz.
TABLE 5 Modulator and amplifierparameters for Designs 1, 2 and 3 Design 1 12-bit @ 4MHz
Design 2 14-bit @ 1 MHz
Design 3 16-bit @ 150kHz
S*F'O7 M = 12 MFs = 48 MHz B W = 250MHz S R >>-250 W/as A0 -~ 60dB Cs = 0.25 pF(~ 0.5%)
S*F*O4 M=32 MFs = 32 MHz B W = 150MHz S R >/- 150 V/ps A0 -~ 60dB Cs = 0.75 pF(~ 0.5%)
S*F*O2 M=64 MFs = 9.6 MHz B W = 50MHz S R >1 50 V/#s A0 --~60dB Cs = 3 pF(~ 0.5%)
275
V.F. Dias et al./ A modulators for A/D converters
SNR (dB)
i00 90
80
. . . . . . .
70
. . . . . . .
60
50
. . . . . . .
I
I
I I I I I. . . . . . . . I I I I I . . . . . . . I I I I I I_ . . . . . . . I I I I I
I I I I I. . . . . . . . . . . . . . . . I I I I I_ . . . . . . . . . . . . . . I I I I I I I_ . . . . . . . I. . . . . . . I I I I I I I I I I
i i '
I I '
I I
I I I-
I I I-
I I I I I
. . . . . . .
. . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . I
_I . . . . . . . I I
,SF~
' BB2 I
f -
,.,/
I
I
I, I /
. . . . . . . . . . . . . . . . . . . . . . .
I---I
/
"I . . . . . . .
. . . . . . . .
.
SBB4F.~.....
-'---,,
," . . . .
F
I
30
. . . . . . . . . . . . . . .
I_. I I
.
I
.
.
.
.
.
I I I I
20
I I
-I . . . . . . . . I I I i !
-I00
-90
-80
-70
I I I- . . . . . . . i I i I I
-60
.
.
.
.
O I I I. . . . . . . I I I I I I. . . . . . . I I I I I
. . . . . . . . .
10
"--S'
-50
I
I I
/.' 40
I I I I I "I-- ----
I I I I I --i . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.I . . . . . . . I I I I I -I . . . . . . . I I I I I
-40
I I I "I . . . . I
I
SF~
' BB7
i "1 . . . . . . . . I I I I I. . . . . . . I I I I I J . . . . . . . I I I I I -I . . . . . . . I I I I I
-30
. . . . . . .
I I "l . . . . . . I I I I
j
. . . . . . . I I I I I
J
. . . . . . . I I ! I I -4 . . . . . . . I I I I I
-20
j
. . . . . . I I O I I
J . . . . . . / I I I I -I . . . . . . I I I I I
-i0
o
Input(dB) Fig. 21. Sinmlated SNR of 1)esigns 1, 2 and 3 with real parameters for the amplifiers (Table 5).
References [1] K.C.-H. Chao et al., A higher order topologT for intcrpolative modulators for oversampling Aft) converters, IEEE Trans. Circuits and Systems, CAS-37 (Mar. 199{}) 309-318. [2] B. Signore, D. Kerth, N. Sooch and E. Swanson, A monolithic 20-b delta sigma Aft) converter, IEEEJ. Solid-State Circuits, SC-25 (6) (Dec. 1990) 1311-1316. [3] R.W. Adams et al., Theory and practical implementation of a fifth-order sigma delta A/D converter, J. Audio Eng. Soc., 39 (7/8)-(July/Aug. 1991) 515-528. [4] Y. Matsuya et al., A 16-bit oversampling A-to-D conversion technology using triple integration noise shaping, IEEEJ. Solid-State Circuits, SC-22 (6) (Dec. 1987) 921-929. [5] L. Longo and M. Copeland, A 13-bit ISDN-band
276
161
[7] [8] [9]
A1)C using two-stage third-order noise-shaping, Proc. 1988 Custom Integrated Circuits Conf., June 1988, pp. 21.2.1-4. C.D. Thompson et al., A monolithic 50kHz 16-bit A/D-1)/A converter using sigma-delta modulation, Proc. IEEE Int. Syrup. Circuits and Systems, 1990, pp. 906-909. M. Rebeschini et al., A high-resolution CMOS sigmadelta A/D converter with 320 kHz output rate, IEEEJ. Solid-State Circuits, SC-25 (2) (Apr. 1990) 431-440. V.F. Dias and V. Liberali, Cascade pseudo-nmltibit noise-shaping modulators, IEE Proc.-G., 140(4) (Aug. 1993) 237-246. D.B. Ribner, A comparison of modulator networks for high-order oversampled SD analog-to-digital converters, IEEE Trans. Circuits and Systems, 38 (2) (Feb. 1991 ) 145-159.
Microelectronics Journal, Vol. 25
[10] L.A. Williams III and B.A. Wooley, Third-order cascade sigma-delta modulators, IEEE Trans. Circuits and Systems, CAS-38 (May 1991) 489-497. [11] B.P. Brandt and B.A. Wooley, A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion, IEEEJ. Solid-State Circuits, SC-26 (12) (Dec. 1991) 1746-1755. [12] B.H. Leung and S. Sutarja, Multibit E - A A/D converter incorporating a novel class of dynamic element matching techniques, IEEE Trans. Circuits and Systems-ll, 39 (1) (Jan. 1992) 35-51. [13] L.R. Carley, A noise-shaping coder topology for 15 + bit converters, IEEEJ. Solid-State Circuits, SC-24 (Apr. 1989) 267-273. [14] D. Ribner eta/., A third-order multistage sigma-delta modulator with reduced sensitivity to non-idealitics, IEEEJ. Solid-State Circuits, SC-26 (12) (Dec. 1991) 1764-1773. [15] T. Leslie and B. Singh, An improved sigma-delta modulator architecture, Proc. IEEE Int. Symp. Circuits and Systems, 1990, pp. 372-375.
[16] V.F. Dias, G. Palmisano, P. O'Leary and F. Maloberti, Fundamental limitations of switched-capacitor sigma-delta modulators, IEE Proc.-G, 139 (Feb. 1992) 27-32. [17] V.F. Dias, G. Palmisano and F. Maloberti, Noise in mixed continuous-time sigma-delta modulators, IEE Proc.-G, 139 (6) (Dec. 1992) 680-684. [18] V.F. Dias, G. Palmisano and F. Maloberti, Harmonic distortion in SC sigma-delta modulators, to appear in IEEE Trans. Circuits and Systems. [19] K. Hsieh et al., A low-noise chopper-stabilized differential switched-capacitor filtering technique, IEEEJ. Solid-State Circuits, SC-16 (6) (Dec. 1981) 708-715. [20] B. Boser et al., Simulating and testing oversampled analog-to-digital converters, IEEE Trans. CAD, 7 (6) (June 1988) 668-674. [21] V. Liberali, V.F. Dias, M. Ciapponi and F. Maloberti, TOSCA: a simulator for switched-capacitor noiseshaping A/D converters, IEEE Trans. CAD lnteg. Circ. Syst., 12(9) (Sept. 1993) 1376-1386.
August 29- September 2, 1994 Senri Life Science Center, Osaka, Japan The scope of MBE-VIII will cover the entire spectrum of molecular beam epitaxyo 1) 2) 3) 4) 5) 6) 7) 8)
element-, hydride-, and metalorganic-source MBE, modulated-flux MBE, MBE of Ill-V, II-VI, IV-VI compounds, group IV elements, MBE of metals, superconductors, insulators, magnetic and other materials, new approaches for atomic-scale control of surfaces, and interfaces, MBE growth mechanism, characterization, electronic, photonic, quantum and novel devices, including growth aspects, in situ processing and characterization, MBE production technology including safety problems.
Request for further information, please contact: Professor Shun-ichi Gonda, MBE-VIII, Chairman The Institute of Scientific and Industrial Research, Osaka University, 8-1, Mihogaoka, Ibarakl, Osaka 567, Japan Teh +81-6877-5111 (ext. 3575); Fax: + 81-6-877-6447
Important Dates: Manuscript deadline Late News deadline Conference
July 1, 1994 August 10, 1994 August 29 - September 2, 1994
There will be a commercial exhibition of equipments and accessories paralleling the technical sessions.
IHtlemJ~l
277