Silicon nanocrystal based memory devices for NVM and DRAM applications

Solid-State Electronics 48 (2004) 1463–1473 www.elsevier.com/locate/sse

Silicon nanocrystal based memory devices for NVM and DRAM applications R.A. Rao *, R.F. Steimle, M. Sadd, C.T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S.G.H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E.J. Prinz, B.E. White Jr., R. Muralidhar Technology Solutions Organization, Motorola SPS, Austin, TX 78721, USA

The review of this paper was arranged by Dr. B. De Salvo and Dr. S. Lombardo

Abstract Si nanocrystal based devices have shown potential in reducing the operating voltages used in continuous floating gate FLASH devices. We discuss the critical aspects of this technology––nanocrystal formation by CVD, nanocrystal passivation, and HCI/FN mode of operation of non-volatile memory bitcells fabricated using a 0.13 lm CMOS process technology. The superior FN erase characteristics of nanocrystal memory compared to a SONOS device are demonstrated, which enables the use of thicker tunnel oxides in nanocrystal memory devices as required to mitigate READ disturb. It is shown that nanocrystal area coverage of <25% is optimal for effective charge isolation and for 2-bit/cell applications. Finally the potential of this technology for use in a 1-transistor PMOS DRAM cell is discussed.
2004 Elsevier Ltd. All rights reserved.

1. Introduction Memory devices with charge storage in discrete traps such as SONOS [1,2] and Si nanocrystal memory [3,4], have potential in both volatile and non-volatile memories. Non-volatile memory (NVM) devices with discrete trap storage provide opportunity to operate at lower voltages compared to continuous floating gate (FG) flash devices because the former are less vulnerable to charge loss through isolated defects in the bottom oxide. These devices also offer potential to be used as single transistor storage devices for volatile memory using thin tunnel oxide and tunneling charge transport. A small cell size (
10f 2 ) and process simplification compared to conventional 1T1C type DRAM devices can be achieved. In this paper, we discuss both NVM and DRAM applications of devices with silicon nanocrystals. Fig. 1 shows a schematic cross-section of three different thin film storage devices. The outline of this paper is as follows: in

*

Corresponding author.

Section 2, we discuss the unique features of nanocrystal memory and contrast it with the well studied SONOS case; in Section 3, we review the bit-cell integration emphasizing the deposition of silicon nanocrystals by CVD and their subsequent passivation; in Section 4, we discuss memory bit cell data characteristics; in Section 5, we highlight the potential of nanocrystal based DRAM and in Section 6, we summarize the paper. 2. Features of nanocrystal memory In this section, we summarize some of the salient aspects of nanocrystal memory devices such as that shown in Fig. 1. The threshold voltage shift due to electron storage is given by [3] as   npq eox tnc DVt ¼ tcntrl þ 2eSi eox where, n is the nanocrystal number density, p is the average number of electrons stored per nanocrystal, q is the electronic charge, e represents the medium

0038-1101/$ - see front matter
2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.03.021

1464

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

50-90A Sio2

50-90A Sio2

50-90A Sio2

10-70A Sio2

40-50A Sio2

40-50 Sio2

SONOS

Nanocrystal

Hybrid

Fig. 1. Schematic cross-section through the gate stack for SONOS, nanocrystal and hybrid memory bitcells.

permittivity and t represents the thickness. Clearly, for storing a given number density of electrons, np, susceptibility to isolated defects in tunnel oxide is mitigated by having a higher density, n, of nanocrystals and minimizing the number, p, of electrons stored per nanocrystal. For nanocrystals to be sufficiently electrically isolated with respect to tunneling transport, their typical separation must be greater than about 4 nm from one another. Having the minimal area fraction of nanocrystals mitigates the probability of defects underlying any nanocrystal. However, charge confinement effects or Coulomb blockade effects to be briefly discussed, increase the energy levels when multiple electrons are stored and this becomes pronounced below a nanocrystal size of about 3 nm. This adversely limits charge retention characteristics and limits the size to be greater than about 4 nm. A nanocrystal density of about 1e12 cm2 and a mean size of around 5 nm are optimal and ensure that there are sufficient nanocrystals to minimize statistical variations and also the charge confinement or Coulomb blockade effects from multiple electron storage are limited. The raising of energy levels may be approximately computed from the reversible work needed to charge the nanocrystal with the additional electron and may be computed from the self capacitance of the nanocrystal which is given by Cnc ¼ 2petnc The increase in energy for a nanocrystal on addition of the nth electron is given by DEn;n1 ¼

q2 2 ðn  ðn  1Þ2 Þ ¼ nq2 =C  q2 =2C 2C

This implies that the electrochemical potential change due to the addition of each electron is given by Dl ¼ DEn;n1  DEn1;n2 ¼ q2 =C Since, the self capacitance of nanocrystals of size range of interest is in atto farads (1018 F) or smaller, this change in energy level is significant. For example, for a 5 nm silicon nanocrystal, the self capacitance is approximately 0.7 atto farads and the above energy level increase is of the order of a few tenths of 1 eV. In a nanocrystal memory, the capacitance of a nanocrystal is

higher due to capacitive coupling to other nanocrystals and substrate and the presence of a dielectric medium. As such, the energy level for a 5 electron nanocrystal is about 0.5 eV above ground state. This raising of energy levels adversely impacts tunneling mediated charge loss through the bottom oxide and limits the number of electrons that can be stored. The raising of energy levels however, facilitates erasure of the memory as it is easier to remove the charges by Fowler–Nordheim injection. We now contrast the nanocrystal memory characteristics with SONOS type memories. A significant advantage of SONOS type memories is the significantly smaller process complexity compared to forming nanocrystals of correct size and density and preserving them during subsequent processing. However, nanocrystal memory brings device advantages. Deeper electron storage traps (
3 eV) compared to nitride traps (1–2 eV) improves electron retention within the nanocrystal. The ability to physically observe the trap centers and obtain their number density and size somewhat mitigates the process complexity. Furthermore, local field effects as well as Coulomb blockade discussed above are central to superior FN erase characteristics compared to SONOS that enables standard HCI-FN NOR architecture. In SONOS, as the gate bias is increased, the FN erase proceeds faster but saturates at a higher erased threshold voltage [5]. This erase saturation arises from a balance between the current through the bottom oxide and competing electron injection from the gate. In contrast, FN erase in a nanocrystal memory leads to a saturation threshold voltage that is independent of the gate bias. Fig. 2 compares the band diagrams for SONOS and nanocrystal memory under FN erase. In SONOS, the erase current through the bottom oxide is less responsive to the field, but attenuates more rapidly with increasing tunnel oxide thickness than the competing back injected current through the top oxide. As a result, the saturated threshold voltage at which the competing currents balance each other increases with both erase bias and tunnel oxide thickness, so that it is not practical to erase a SONOS bitcell with a tunnel oxide thicknesses greater than 5 nm with tunneling. Hence, hole injection [2] has to be used and the reliability of tunnel oxides has to be established. For nanocrystal memory the erase current through the bottom oxide and the competing back injection from the gate

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

1465

6

6

5

5

4

4

3

-14V -13V

2 1 -6 10

(a)

Vt (V)

Vt (V)

Fig. 2. (a) Band diagram of SONOS under negative gate bias FN erase. The various arrows represent the electron current from the gate, electron de-trapping from the nitride and hole injection from the substrate. (b) Band diagram of nanocrystal memory under negative gate bias FN erase.

-12V 10

-4

-2

10

10

0

10

Time (sec)

2

-14V

-10V -12V

3 2

-18V -16V

1 -6 10 (b)

10

-4

-2

10 10 Time (sec)

0

10

2

Fig. 3. (a) Simulation showing gate bias dependence of FN erase of SONOS bitcell with 25 A/120 A/50 A bottom oxide/nitride/top oxide thickness. (b) Simulation showing gate bias dependence of FN erase in nanocrystal memory with 50 A tunnel oxide and 100 A control oxide.

have identical dependence on the field and experience similar barriers. Therefore, as long as the nanocrystals are charged with electrons the field in the bottom oxide is higher than the field in the top oxide, which facilitates electron removal from the nanocrystal to the substrate. As the electrons are removed from the nanocrystals, the field across the top oxide increases while the field across the bottom oxide decreases until a steady state is reached when both fields and hence both FN currents are equal. This steady state implies that there is no effective transfer of charge to/from the nanocrystals. Fig. 3 compares the erase models for SONOS [6] and nanocrystal memory, which have been simulated using a WKB tunneling based model [7] that also incorporates gate injection and Coulomb blockade effects. Finally, the deeper electron traps in nanocrystals makes data retention substantially less temperature sensitive compared to SONOS where charge transport within the nitride layer is Frenkel–Poole emission that is temperature sensitive.

3. Bitcell fabrication As has been discussed in the previous section, crucial to making a nanocrystal memory is the ability to form

nanocrystals at densities around 1012 cm2 and size around 5 nm. Numerous efforts have focused on obtaining a high density of nanocrystals through a variety of techniques including aerosol technique, ionimplantation, direct chemical vapor deposition (CVD) and recrystallization anneal of amorphous-Si. Direct CVD of silicon is preferred over ion implantation and recrystallization anneal due to the difficulty in obtaining the required amount of Si in the stack. Further, nucleation and growth by CVD provides appropriate simpler processing controls to manipulate the size and density of nanocrystals. Si nanocrystals with number density between 1e11 and 1e12/cm2 have been deposited on various dielectrics such as SiO2 , Si3 N4 and Al2 O3 using CVD [8–10]. Si island growth during CVD on amorphous dielectrics such as SiO2 and Si3 N4 is believed to proceed by atomistic nucleation, with a critical size of between 1 and 4 atoms [11]. Fig. 4(a) shows a typical nucleation and growth curve for Si nanocrystal formation during CVD along with SEM images of the surface during various phases of the nucleation and growth curve. During the initial incubation phase, there are not enough adatoms formed on the surface for nucleation to occur and the surface adatom concentration increases with time. Once a sufficient surface concentration of

1466

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

Fig. 4. (a) Typical nucleation and growth curve along with SEM images showing the evolution of nanocrystals on SiO2 surface during CVD of Si. (b) Atomistic nucleation of Si nanocrystals on a dielectric surface. Major processes include SiH4 adsorption, adatom reevaporation and diffusion as well as H2 desorption.

adatoms is attained, nucleation occurs as adatoms diffusively encounter each other to form small clusters. During this nucleation phase, the number of nanocrystals increases rapidly as fresh nuclei are formed. The nanocrystals formed by nucleation grow by adatom attachment by surface diffusion. Initially, the growth phase overlaps with the nucleation phase. However, once a certain saturation nanocrystal density is attained, then fresh nucleation is shut off as all incoming adatoms are captured by existing nanocrystals. Eventually, the growing clusters merge with adjacent ones by coalescence and the nanocrystal density decreases as a continuous network of clusters is formed. Fig. 4(b) depicts the major processes occurring on the dielectric surface during formation of Si nanocrystals by SiH4 CVD. An incoming SiH4 molecule from the gas phase is adsorbed on the surface at a physisorption site of surface energy minima and dissociates to form a Si adatom accompanied with H2 desorption. The formed Si adatom then either contributes to the formation a fresh nanocrystal through atomistic nucleation or is consumed by an existing nanocrystal through surface diffusion. To obtain high

Density (#/cm2)

0.78Torr 0.4Torr

1011

500C SiH4on SiO2 1010 0

(a)

B -2

1012

where R is the flux of adatoms, i is the critical size and Ei , Ea and Ed are respectively the binding energy of a cluster of i atoms, the adsorption energy and diffusion activation energy. In general Ei is greater than Ed and hence the saturation density increases with adatom flux and decreasing temperature. Fig. 5(a) shows the effect of precursor partial pressure on Si nanocrystal deposition in CVD at a fixed temperature. As the precursor partial pressure is increased, the timescales for incubation and

Nanocrystal density (cm )

B B

nanocrystal density, a high adatom flux and low surface diffusion is preferred. In addition, fast surface H2 desorption and low adatom evaporation are also desired. Therefore, by controlling the partial pressure of precursor and surface temperature, Si nanocrystals of desired size and density can be deposited. In an MBE type deposition, the saturation nanocrystal density, Ns , is given by Venables [12] for initially incomplete condensation and 3d island growth as:   2 ðEi þ ði þ 1ÞEa  Ed Þ Ns
R2i=5 exp 3 kT

200

400

600

Time (sec)

800 1000

1011

560C 580C 600C 650C

1010

109 0

(b)

5

10

15

20

25

30

Deposition time (min)

Fig. 5. (a) Effect of precursor partial pressure on nucleation curve for Si nanocrystal deposition by SiH4 CVD on SiO2 surface. (b) Effect of surface temperature on nucleation curve for Si nanocrystal deposition by SiH4 CVD on SiO2 surface.

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

peak nanocrystal density decrease, indicating an acceleration of the entire nucleation and growth process. This is due to the increased adatom flux at higher partial pressures. However, the peak nanocrystal density itself does not show significant dependence on partial pressure, suggesting a small critical size for nucleation of the order of 1 atom. In CVD deposition the adatom flux is strongly dependent on temperature leading to a complex dependence of nucleation on temperature. Fig. 5(b) shows the effect of wafer temperature on the nucleation curves for SiH4 based deposition on SiO2 . As the wafer temperature is increased, the dissociation of adsorbed precursor molecule on the surface increases resulting in higher adatom flux and shorter incubation and nucleation timescales. However, surface diffusion of adatoms also increases with temperature, resulting in increased adatom capture by existing Si nuclei, which in turn reduces fresh nanocrystal nucleation. Therefore, the peak nanocrystal density decreases as temperature is increased. Thus, maximum nanocrystal density may be modulated by controlling the precursor partial pressure and temperature. Fig. 6 shows an SEM image of nanocrystals deposited on active and isolation oxides, using an optimal process that produces a nanocrystal number density of
1e12/cm2 with a mean size of 5 nm. As can be seen from the figure, the nucleation characteristics on both oxides are statistically equivalent, indicating that nanocrystal nucleation is not defect mediated. All devices shown in this paper have been fabricated using 0.13 lm CMOS technology. For NVM applications, read disturb and data retention criteria limit bot to suppress tom oxide thickness to the range of 50–70 A defect site mediated charge exchange with the channel. After tunnel oxide growth, the silicon nanocrystals were deposited at required densities using optimized CVD processes as described in the previous section. After nanocrystal deposition, the wafers were subjected to an 850 C anneal in NO ambient to passivate the nanocrystals by forming a thin shell of SiOx Ny around the Si nanocrystals, as shown in Fig. 7. This helps in preventing

1467

Fig. 7. Cross-section EFTEM images of passivated (a) and unpassivated (b) nanocrystals subjected to severe oxidizing ambient. The unpassivated nanocrystals oxidize partially forming a thick oxide shell around a Si core.

oxidation of nanocrystals during subsequent processing steps and also leads to a narrower size distribution [13].  high temperature control oxide was Subsequently, 100 A deposited on nanocrystals. A key aspect of the bitcell integration is the gate stack etch for removal of nanocrystals from the source/drain regions, without causing any silicon recess in the source/drain. In this paper, all Si nanocrystal memory cell data have been obtained from 0.13 lm channel length devices.

4. NVM bitcell characteristics Fig. 8 shows the FN erase behavior of nanocrystal memory under different gate biases. The data shows that a 100 ms block erase is possible using )12 V for a nominal stack of 50 A bottom oxide, nanocrystals and 100 A top oxide. Data from the erase model described earlier has also been superimposed in Fig. 8. Good agreement between the model and data is observed. Interestingly, the model predicts that if the nanocrystals

6 5

Vt (V)

4 3 Vg= -10V Vg= -12V Vg= -14V Vg= -16V Vg= -18V Vg= -18V

2 1

0 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 Time (s) Fig. 6. SEM image of nanocrystals deposited using optimized CVD process on active (top) and isolation (bottom) oxides.

Fig. 8. Gate bias dependence of FN erase speed. Measured data shown in open circles and modeling data in solid lines.

1468

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

Fig. 9. (a) Band diagram of nanocrystal memory under positive gate bias FN programming. (b) Gate bias dependence of FN program speed for memory bitcell with 38 A tunnel oxide and 100 A control oxide and with 15% area coverage of nanocrystals as shown in the inset. (c) Gate bias dependence of FN program speed for nanocrystal memory bitcell with 38 A tunnel oxide and 100 A control oxide and 50% area coverage of nanocrystals as shown in the inset.

were to be initially positively charged (e.g. by hot hole injection), FN erase increases the Vt to the stable erased value. Programming the nanocrystal bitcell is possible by uniform charge injection from the channel using tunneling as well as local charge injection using channel hot electrons. At a tunnel oxide thickness of less than 4 nm, programming nanocrystals by direct tunneling is possible at gate voltages between 6 and 10 V. However, the programming is limited by the capture cross-section of nanocrystals and Coulomb blockade. As the thickness of the tunnel oxide is increased to greater than 4 nm, programming by direct tunneling is impractical and one has to employ FN injection (Fig. 9a), which shows interesting characteristics depending on the area coverage of nanocrystals. Fig. 9(b) shows the tunneling program curves for a bitcell with 15% area coverage of nanocrystals. At low gate voltages (8–10 V) the device is in the direct tunneling regime and limited programming, albeit slowly, by direct tunneling is possible. At higher gate bias (12–14 V), the device is in the FN tunneling regime. However, at low area coverage (
15%) of nanocrystals, when electrons are injected into the nanocrystal from the substrate, the local control oxide field in the vicinity of the nanocrystal becomes greater than the tunnel oxide field. This facilitates removal of electrons from the nanocrystal to the gate, thus preventing any significant programming of memory cells. Fig. 9(c) shows the tunneling program curves for a bitcell with 50% area coverage of nanocrystals and with the same bottom and top oxide thicknesses. When the nanocrystal area coverage is large enough to form a network of nanocrystals, the local field in the floating gate is smaller than at lower nanocrystal area fractions for the same average charge density. Further, since electrons can rapidly tunnel from one nanocrystal to another making the gate resemble a continuous floating gate, the capacitive coupling of the control gate to the floating gate is stronger. Both these effects lead to FN

programming seen in Fig. 9(c) and not observed in the case of low areal coverage (Fig. 9(b)). However, saturation sets in when currents from the channel to the nanocrystal and from the nanocrystal to the poly-Si gate are in balance. Fig. 10 shows the effect of drain bias on hot carrier injection (HCI) program speed. Increasing the drain bias increases the lateral field, which is responsible for hot carrier generation. As a result the program speed improves even for small changes in drain bias. Increasing the gate bias increases the number of carriers in the channel and the gate field, which attracts the hot electrons to the gate. However, the gate bias has a lesser impact on HCI program speed than the drain bias. It is evident that a 2 V threshold voltage shift can be obtained with sub 10 ls programming time. A typical erase curve is shown for the same bit and indicates that 100 ms block erase can be achieved. Fig. 11 shows the HCI program and FN erase cycling  tunnel oxide and 100 A  endurance of the cell with a 50 A control oxide. The program and erase threshold voltages drift up by approximately 1 V after 10,000 cycles due to charge trapping in the control oxide. Unlike a floating gate device that captures all hot electrons injected towards the gate, the nanocrystal layer has less capture cross-section and hence only a portion of the injected electrons are captured by nanocrystals while the rest are either trapped in the control oxide or reach the gate. Therefore, improvement in endurance behavior can be obtained by optimizing control dielectric to minimize charge trapping. Fig. 12 shows data retention at 150 C as well as read disturb characteristics for a memory cell with 50 A  control oxide before and after tunnel oxide and 100 A cycling under conditions described in Fig. 11. While the uncycled device shows good data retention of the high Vt state, the cycled device shows some initial charge loss presumably due to detrapping of oxide charges. The read disturb measurements were conducted with a gate

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473 5.5

7

4.5V

5

Tbot = 50Å, T top = 100Å

6

4.0V

4.5

5

3.5V V (V)

4

t

Vt (V)

1469

3.5

HCI Programming: Vg = 6 V, Vd = 4V, Vb = 0 V

4 3

Vg=-15V

FN Eras e: Vg = -1 4V, Vd = Vs = Vb = 0 V

2

3 2.5 -7 -6 -5 -4 -3 -2 -1 10 10 10 10 10 10 10 Time (sec)

1 10

0

1

2

10 10 10 # of P -E cycles

3

10

4

Fig. 10. Influence of drain bias on HCI programming speed at Vg ¼ 10 V for a bit cell with 50 A tunnel oxide and 100 A control oxide. A FN erase curve from the same bit is superimposed.

-4

7

10 Tbot = 50Å, Ttop = 100Å

6

fwd read

-6

HCI Programming: V = 6V, V = 4V, V = 0V

4

g

d

b

-8

10

d

t

V (V)

I (A)

10 5

3

-10

10 FN Erase: Vg = -14V, Vd = Vs = Vb = 0V

2

rev read

-12

10

1 0

10

1

2

3

4

10 10 10 # of P-E cycles

10

7

5

Data Retention @ 150 ˚ C

Uncycled

4

cycled Read Disturb @ 2 5˚C

3

10 yea rs

Vt(V)

6

Uncycled

2 10

0

10

2

4

10 10 Time (s)

6

0

0.5

1

1.5

2

2.5

3

Vg (V)

Fig. 11. HCI program and FN erase cycling endurance behavior of a memory cell with 50 A tunnel oxide and 100 A control oxide.

cycled

-14

10

10

8

Fig. 12. 150C Data retention of high Vt state and 25C Read disturb before and after HCI-FN cycling under conditions shown in Fig. 11, for bitcell with 50 A tunnel oxide and 100 A control oxide.

stress of 1 V overdrive over the erase Vt state and with Vd ¼ 1 V. There is practically no read disturb of the erase state even after 10000 HCI-FN cycles, due to the thick and high quality thermally grown tunnel oxide.

Fig. 13. Id –Vg curves at t ¼ 0 (solid circles) and t ¼ 65 h (open squares) showing local storage data retention at 150C after localized CHE programming for 55 A tunnel oxide with
20% areal coverage of nanocrystals.

The isolated nature of charge storage centers (low area fraction of nanocrystals) and the energy well (3.1 eV to silicon dioxide) makes the nanocrystal memory cell a good candidate for local storage. Fig. 13 shows the asymmetric threshold voltages obtained by forward and reverse reading operations [2] in a 0.13 lm channel length device with nanocrystal area coverage of 20%, which has been programmed by HCI. It is seen that at such low area coverage, excellent local storage and data retention is observed. As the nanocrystal area coverage is increased to 50%, lateral tunneling transport prevents local charge storage [14].

5. 1-T DRAM application The use of silicon nanocrystals as replacements for DRAM requires operating the memory cells in a different programming mode (direct tunneling) and with a thinner tunnel oxide. The endurance of a DRAM cell requires that up to 1012 program/erase cycles be

1470

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

performed during the lifetime of the device. Programming using either hot electron injection or Fowler– Nordheim would damage the tunnel oxide of the cell. Direct tunneling causes little or no damage to the tunnel oxide. But, to achieve the speed (10’s of nanoseconds) needed for a DRAM application the tunnel oxide  thickness must be on the order of 10–12 A. Both nanocrystal, and silicon nitride or SONOS type devices have been examined in the past as potential DRAM candidates [3,15]. Nanocrystal devices, which are programmed by direct tunneling, are usually limited to storage of one to two electrons per nanocrystal due to the Coulomb-blockade effects that become significant at DRAM like programming voltages. Basically, the raising of energy levels in nanocrystal due to multiple electron storage makes these states inaccessible by direct tunneling from inversion layer unless the gate voltage is further increased. To obtain the most favorable data retention, a device with one electron stored per nanocrystal will have the nanocrystal states aligned with the band gap of the substrate. Charge loss from the nanocrystal will be due to thermal emission of the electron to higher energy states and subsequent tunneling of the electron through the tunnel oxide to the substrate conduction band. If more than one electron is stored in a nanocrystal, the electrons are stored in higher energy states due to the Coulombblockade. These electrons are lost almost immediately to the substrate through direct tunneling through thin tunnel oxide that is virtually transparent. For example, let us consider an NMOS case using 12 A tunnel oxide, 50 A diameter nanocrystals, 80 A control oxide with a substrate doping of 5 · 1017 cm3 at room temperature. When only 1 electron is stored in a nanocrystal, this electron energy level is about 0.05 eV below the substrate conduction band and substrate states are inaccessible (in the absence of interface states). When 2 electrons are stored however, the net impact of Coulomb blockade and electrostatics makes the nanocrystal conduction band edge be about 0.03 eV above the substrate conduction band and immediate tunneling loss is possible. Thus the voltage shift of a direct tunnel programmed nanocrystal device is limited to the storage of one electron per nanocrystal for optimal refresh time. Even with thin tunnel oxides, SONOS devices have better data retention than nanocrystal devices. Although nitride also looses charge by direct tunneling to the channel, conduction of the charge through the nitride is the rate limiting transport mechanism for nitride type devices. More specifically, the charge stored deep in the nitride has to approach the tunnel oxide interface by Poole– Frenkel emission. However, SONOS devices are not easily programmed by direct tunneling and instead rely on modified Fowler–Nordheim injection. This necessitates the use of higher programming voltages for SONOS devices and it also subjects the tunnel oxide to greater stress, compromising the reliability of the oxide.

A hybrid silicon nanocrystal silicon nitride device, henceforth referred to as simply a hybrid device, has potential to overcome the above limitations. This device is shown in Fig. 1. It consists of a thin tunnel oxide, nanocrystals, a layer of silicon nanocrystals and a silicon nitride layer on top of which is the control dielectric. The presence of nanocrystals in the hybrid device modifies the band diagram from a SONOS type device. This significantly modifies the transport coefficients of electrons, which tunnel into the nitride, and results in an increase in transport obtained in SONOS type devices. Furthermore, the hybrid device stores charge in both the nanocrystals and the nitride resulting in an increase in data retention and refresh time over a purely nanocrystal type device. In an NMOS nanocrystal or hybrid device the write and erase speeds are not symmetrical for the same magnitude of write and erase voltage. The built in potential, caused by differences in the doping between the polysilicon gate and the silicon substrate is a fundamental cause of this asymmetry. Further the conduction band offset between silicon and silicon dioxide is significantly smaller than the valence band. Therefore, the direct tunneling rate of electrons is greater than the tunneling rate of holes. Injection of holes for erase is not favored in an NMOS device for this reason and the devices primarily erase by electron emission. This in turn causes difficulty in erasing electrons trapped in deep nanocrystal surface states. However, for a PMOS device, holes are injected into the valence band of the nanocrystal for programming and electrons can tunnel into the conduction band for erase. This not only makes the program and erase speeds more symmetric compared to NMOS but also provides opportunity for holes trapped in nanocrystal surface states to recombine with electrons during erase. PMOS Hybrid, SONOS and silicon nanocrystal de tunnel oxide thickness were fabrivices with an 18 A cated to investigate their suitability for use as DRAM cells. PMOS devices were chosen because they are programmed by hole injection from inverted channel and erased by electron injection from accumulation layer. This makes the program and erase more symmetric compared to NMOS and also mitigates the impact of any deep nanocrystal oxide surface states. To obtain program and erase speeds comparable to contemporary  tunnel oxide would be required. But, DRAM, 10–15 A at these thin tunnel oxide thicknesses non-circuit bitcell characterization becomes very difficult. Conventional Id –Vg measurements typically used for NVM type devices would significantly alter the state of the device (thin tunnel oxide permits charge exchange with the substrate) and so a novel test setup (See Fig. 14) was developed to determine the program and erase characteristics of the different devices. This method senses the drain current instead of using a direct mea-

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

1471

Pulse Gen

HP 4156

Drain Current (A)

410 -6 310 -6 210 -6 110 -6 0 0

0.1

0.2

Pulse Train

0.3 0.4 Time (sec)

0.5

0.6

6V 0V -2.25 V -6V

Fig. 14. Experimental setup showing pulse train with ±6 V, 1 ms program/erase and transient response of hybrid transistor.

Drain Current

10-5

10-6

Drain Current

10-7 10 -5

10 -6

10 -7 10-5 Drain Current

surement of the threshold voltage. A pulse generator was connected to the gate of the transistor and an HP4156 semiconductor parameter analyzer was used to sense the drain current with the drain held at a constant bias of )0.5 V. The pulse train contains large positive and negative pulses to erase (positive pulse) and program (negative pulse) the PMOS devices. Smaller negative read pulses, chosen to minimize disturb of the device, are used to sense the drain current in the programmed/erased states and to give an indication of data retention time. A typical pulse train in is shown in Fig. 14 along with the resultant measured drain current from a hybrid device. A large increase in the drain current occurs with an erase pulse of 6 V for 1 ms as electrons are injected into the storage sites (both nanocrystals and nitride) making the threshold voltage more positive. After the pulse a rapid decay in the current occurs, as charge is lost from the nanocrystals to the substrate by direct tunneling. Likewise when a )6 V programming pulse is applied, the drain current jumps up rapidly as the transistor is driven into strong inversion with the spike represents the programming current. Afterwards, the device retains the programmed charge and correspondingly lower drain currents are subsequently read using the read pulses. This reflects the fact that the threshold voltage of the cell has become more negative due to the hole injection into the nitride and the nanocrystals. The programming and short-term data retention characteristics of SONOS, silicon nanocrystal and hybrid devices are compared in Fig. 15. All three devices were subjected to the same pulse train. There is very little difference between drain current in the programmed and erased states for SONOS at these voltages. Direct tunneling into nitride traps is ineffective (misalignment of nitride traps to inversion layer) and the

10-6

10-7 0

0.1

0.2 0.3 0.4 Time (sec)

0.5

0.6

Fig. 15. Program/erase characteristics (±6 V, 1 ms) of SONOS (top), nanocrystal (middle), and hybrid (bottom) devices.

programming voltage is not high enough for modified Fowler–Nordheim charge transport. The nanocrystal device, which programs by direct tunneling, shows a larger memory window. This memory window is perhaps limited by the coulomb-blockade charge injection. Furthermore the program and erase states decay rapidly and are indistinguishable in 0.2 s. Finally the hybrid

1472

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

device shows a much large programming window than either the SONOS or nanocrystal devices. It retains much of its stored charge due to the fact that the charge layer is comprised of both nanocrystals and nitride. The transport of charge from nanocrystals to the substrate is rather rapid. But, the nitride conduction mechanism and data retention is similar to SONOS devices. Thus, the hybrid device achieves a greater threshold voltage shift than either the nanocrystal or SONOS device under equivalent programming conditions. The programming window increase possible with a hybrid device is a direct consequence of the addition of nanocrystals on the band structure of SONOS. Fig. 16 shows a direct comparison of the band diagrams of NMOS SONOS (top) and Hybrid (bottom) devices. Both of the devices are biased with a positive 6 V. The hybrid device nanocrystals are loaded with the equivalent of 4 electrons of charge. The dotted line in both figures indicates the path an electron must travel to tunnel into the nitride conduction band. A WKB calculation (based on effective masses from Ref. [16]) of the transmission coefficients for the hybrid versus the SONOS case has been performed and shows that the hybrid device has a transmission coefficient 106 higher than for the SONOS case. Thus, the nanocrystal energy levels 4 2

Energy (eV)

0 -2 -4 -6 -8 -10

-25

25

75

125

175

-12 Position (Å)

-14 4 0 -25 -2

25

75

125

175

225

1.4 10-6

-4

1.2 10-6

-6

1 10-6

Current (A)

Energy (eV)

2

serve as intermediate states for transport into the nitride and result in a large threshold voltage shift that comes predominantly from nitride storage and also storage in nanocrystals. Interface states generated at the oxide nanocrystal oxide interface have been previously reported in literature [17]. These interface states could also be possible in a hybrid type device. Because of their close proximity to gate oxide, they could also result in short programming and long data retention times. If the density of the states is much higher for a nitride–silicon interface than for an oxide–silicon interface then they could account for the differences seen between the nanocrystal devices and the nitride type devices. However, long-term data retention tests performed on hybrid NMOS capacitors has shown that the behavior of these devices is much like SONOS [18]. As discussed earlier, PMOS devices are expected to be more immune to such surface states. Longer term data retention characteristics of the hybrid device are shown in Fig. 17. The device is first erased and data retention is monitored for about 30 s. Next the device is subsequently programmed and monitored for another 30 s. It is clear that after the initial charge loss from the nanocrystals, little change in either of current state occurs during the duration of the 30 s test. Finally, Fig. 18 shows the cycling endurance of the hybrid device. The program/erase pulses were ±8 V and 5 ls long. No difference in seen in the program or erase characteristics after 256,000 pulses. Because these pulses are in the direct tunneling regime and the storage medium consists of direct traps, it is expected that damage to tunnel oxide by hot electrons or holes will not limit the lifetime of this device. Tests of the hybrid device have demonstrated that it exhibits a larger threshold voltage shift than either silicon nanocrystal or SONOS type devices. Data retention for the hybrid DRAM is closer to a SONOS device than to a silicon nanocrystal device. In order to match the speed of contemporary DRAM, the tunnel oxide thickness must be scaled from that reported in this

-8 -10 -12 -14

Position (Å)

Fig. 16. Band diagrams for the SONOS (top) and hybrid (bottom) devices biased at +6 V. The nanocrystals in the hybrid device are charged with four electrons each. The dashed line shows the tunneling path along which the transmission is calculated.

8 10-7 6 10-7 4 10-7 2 10-7 0 0

10

20

30 40 Time (sec)

50

60

70

Fig. 17. Longer term (30 s) data retention of hybrid device in program and erase states.

R.A. Rao et al. / Solid-State Electronics 48 (2004) 1463–1473

Current (A)

2 10-6 1.5 10-6 Erase Current Program Current -6

1 10

5 10-7 0 1

10

100

1000

10 4

10 5

10 6

Cycle Fig. 18. Program/erase endurance cycling of hybrid device ±8 V, 5 ls.

 It is expected that programming experiment to 10–15 A. times in the 10’s of nanoseconds will be possible and that data retention times will not decrease drastically due to SONOS like data retention characteristics. By appropriately scaling the stack thickness and taking advantage of high K dielectrics further scaling in the program and erase voltages is possible. The hybrid device has potential to be an attractive DRAM replacement.

6. Summary In this paper, we have reviewed two potential applications of nanocrystal based memory devices. They provide an opportunity to scale conventional floating gate NOR Flash by mitigating the vulnerability to isolated tunnel oxide defects, which in turn enables one to scale oxide thicknesses and reduce operating voltages. Superior Fowler–Nordheim erase characteristics compared to SONOS type memories enable one to erase with conventional Fowler–Nordheim at oxide thicknesses that are needed to mitigate READ disturb without resorting to hot hole injection. Further, deeper energy trap levels, permit local storage and 2 bit per cell operation for small gate lengths. A key aspect for NVM applications is possible charge trapping in the oxide stacks during HCI/FN operation that manifests as threshold voltage increase of programmed and erased states during repeated program/erase operations. This must be mitigated by development of high quality oxides and/or design solutions. For 1T DRAM applications that use tunneling transport with thin tunnel oxides, both SONOS and nanocrystal memories have limitations in that the former needs higher operating voltages for modified FN tunneling into nitride whereas the latter has limited threshold voltage shift and data retention. A hybrid nanocrystal SONOS architecture that employs

1473

nanocrystals as intermediate states to accelerate tunneling into the nitride layer is shown to improve programming speed by orders of magnitude (about 106 times) compared to SONOS at lower voltages and also offer good threshold voltage shifts and refresh time. Key to these memory technologies is the ability to form silicon nanocrystals of required size and densities and preserving them during subsequent processing. CVD methods have so far yielded the highest nanocrystal densities on oxide and also offer process knobs for controlling size and density. Nitridation of silicon nanocrystals offers a way to passivate them during subsequent processing. Nanocrystal NVM and hybrid DRAM may provide an opportunity to alleviate the challenges of embedding capacitor based DRAM and floating gate NVM on the same chip. This paper does not go into modeling aspects of nanocrystal memories. For this, the reader is referred to excellent discussions in the literature [6,7,19].

References [1] White MH et al.. In: Brown WD, Brewer JE, editors. Nonvolatile semiconductor memory technology. IEEE Press; 1998. [2] Boaz E. In: Intl Conf Solid State Dev Mater, Japan, 1999. [3] Tiwari S et al. IEDM Technical Digest, 20.4.1, 1995. [4] De Blauwe J et al. International Electron Devices Meeting, 2000. [5] Swift C et al. IEDM 2002. [6] Sadd M et al. In: Proceedings of the IEEE Non Volatile Semiconductor Memory Workshop, 2003. [7] Sadd M et al. In: Proceedings of the IEEE Non Volatile Semiconductor Memory Workshop, 2001. [8] Mazen F, Baron T, Bremond G, Buffet N, Rochat N, Mur P, et al. J Electrochem Soc 2003;150:G203. [9] Madhukar S et al. In: Mater Res Soc Symp Proc, 638, F.5.2.1, 2001. [10] Baron T, Fernandes A, Damlencourt JF, De Salvo B, Martin F, Mazen F, et al. Appl Phys Lett 2003;82:4151. [11] Kamins T. Polycrystalline silicon for integrated circuits and displays. Massachusetts: Kluwer Academic Publishers; 1998. [12] Venables JA. Introduction to surface and thin film processes. Cambridge, UK: Cambridge University Press; 2000. [13] Scheer KC et al. J Appl Phys 2003;93:5637. [14] Hradsky B et al. IEEE Non-Volatile Memory Workshop, 2003. [15] Wann CH-J, Hu C. IEDM Technical Digest, 34.6., 1995. [16] Bachhofer H et al. J Appl Phys 2001;89:2791. [17] Wahl J, Silva J, Gokirmak A, Kumar A, Welser JJ, Tiwari S. Int Electron Devices Meeting Tech Dig, 1999. p. 375. [18] Muralidhar R et al. IEEE Silicon Nanoelectronics Workshop, 2003. [19] De Salvo B. IEDM 2003 Technical Digest. p. 597.