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Simulation of time-dependent tunneling characteristics of MOS structures
Solid-State Electronics Vol. 34, No. 3, pp. 291-299, 1991
0038-1101/91 $3.00 + 0.00 Copyright © 1991 Pergamon Press plc
Printed in Great Britain. All rights reserved
SIMULATION OF TIME-DEPENDENT T U N N E L I N G CHARACTERISTICS OF MOS STRUCTURES R. RA~SWAm and H. C. LfN Department of Electrical Engineering, University of Maryland, College Park, MD 20742, U.S.A. (Received 15 May 1990; in revisedform 25 August 1990) Abstract--A detailed model has been developed to simulate the Fowler-Nordheim tunneling and degradation characteristics of thermal oxides on silicon incorporating geometry effects, trapping at pre-stress and post-stress trap sites, and field dependent charge to breakdown. For the first time, the effect of gate edge on the time-dependent tunneling characteristics has been quantitatively analyzed, using the Schwarz-Christoffel transformation method. It is found that gate edge region can enhance the tunneling current significantly and also accelerate oxide degradation and breakdown. One application of this model is to remove geometry effects in the oxide parameters extracted using ramp-stress measurements. Another application is to use the asymmetry in gate and substrate injections to electrically characterize the gate geometry and obtain an effective edge curvature.
NOTATION
tt t2
Or, 02 J
J,o,~ J~,, In,, i, F
i% Q~
Q~
do, Be
e,.i
Ek
No % gt % tltp ntg nt
v~ Vox
V
v~ q~ m m* ms~
h £s ~'ox
Eo
length of the capacitor/transistor width of the capacitor/transistor gate oxide thickness field oxide thickness gate tapering angles over the gate to field oxide transition region tunneling current density tunneling current density from gate tunneling current density from substrate tunneling current density in planar region total current from planar region total current from nonplanar region total gate current injected fluence effective injected fluence breakdown fluence in planar region charge to breakdown for oxide reference charge to breakdown for oxide breakdown coefficients reference cathode electric field for breakdown calculation field at cathode surface volume density of pre-stress traps capture cross-section of pre-stress traps electron trap generation rate capture cross-section of generated traps trapped charge density at pre-stress trap sites trapped charge density at generated trap sites total trapped charge density applied gate voltage voltage drop across oxide fiat-band voltage silicon surface potential gate voltage ramp rate starting voltage for Fowler-Nordheim tunneling electron charge free-electron mass electron effective mass in oxide electron effective mass in silicon barrier height Planck's constant silicon dielectric constant oxide dielectric constant lowest sub-band energy of confined inversion
layer electrons Fermi level substrate doping concentration No analytic function mapping z--,w plane f(z) g(w) analytic function mapping w--,z plane 2, h~,h2 transformation parameters geometry factor originating from electrode non% planarity
291
1. INTRODUCTION
Many floating gate nonvolatile memory devices-FLOTOX, TPFG etc., use high field tunnel injection to transport charges across thin oxides. This process degrades the oxide due to charge trapping, and eventually leads to breakdown. As the dimensions of these devices are scaled down for VLSI applications, trapping effects, dielectric strength and reliability of thin oxides has been extensively studied. Several authors have suggested that thermal oxides can be characterized from ramp-voltage stressed I - V characteristics, i.e. parameters such as capture crosssection, trap density etc., can be extracted from a single measurement[l,2]. However, because of calculational complexity, geometry effects on the tunneling current characteristics have been neglected. By quantifying the geometry effects, oxide parameters can be extracted more accurately. Also, since oxide degradation and breakdown is a field dependent phenomenon, it is necessary to be able to calculate the fields accurately to predict the reliability of thin oxides. In this paper, we develop a method to calculate the time-dependent tunneling current from gate edges in MOS structure. The motivation behind this effort was to study the reliability of FLOTOX cells where the geometry nonplanarity is introduced by floating gate transition from tunnel oxide to gate and field oxide regions. Edge effects are not negligible in small
292
R. RAMASWAMIand H. C. LIN
Ec 3.15e
C-
EFM AI
EF$
P-Si
SiO2
Ev
f
EFM - -
(a)
(b)
Fig. I. Energy band diagram of MOS system: (a) at equilibrium, (b) during electron tunneling from substrate. geometry devices as evidenced by narrow-channel effect, where field reduction at the channel surface under the gate edge region increases the transistor threshold voltage[3,4]. Since tunneling current strongly depends on the cathode field, we expect the comers in the transition region to affect the conduction characteristics. All the analyses so far for tunneling conduction have not taken into account quantitatively the field enhancement at gate edge corners. The use of uniform geometry assumption may be reasonable when transition from tunnel to gate oxide region is gradual but should fail for sharp transitions. This problem is not amenable to standard numerical analysis, because the comers in the transition region depend on the fabrication process and cannot be considered to have uniform shapes, hence, accurate numerical solution of Poisson's equation near these regions may require extremely fine mesh intervals. Additionally, the asymmetric tunneling characteristics can be used to extract an effective gate edge curvature. 2. DETAILED CELL MODEL
When high voltage is applied across the oxide in a MOS system, electrons can be transported via the tunneling mechanism. For thermal oxides thicker than about 70 A, electron transport occurs between
Lg
the gate Fermi level and the Si conduction band, and can be described by the Fowler-Nordheim mechanism[5,6]. In our experiments we used 312 A oxides, in which case current due to direct, valence band and interface state tunneling is negligible[7,8]. The band diagram for Al/SiO2/p-Si system at equilibrium, and during electron injection from the substrate is shown in Fig. 1. During substrate injection, since inversion layer electrons are confined to a narrow potential well at the interface, their energy is quantized normal to the interface as shown in Fig. lb, and the tunneling current is dominated by the electrons from the lowest sub-band with energy E019]. Image-force barrier lowering can be neglected, because it rounds the top of the barrier only and hardly affects the tunneling distance[10]. The geometry of the MOS transistor is shown in Fig. 2, along the length and width directions of the channel, where we have used the tapered oxide approximation to model the device structure. From Fig. 2b, it is seen that due to symmetry, only one-half of the structure needs to be analyzed, as shown in Fig. 3a. Our primary aim in this paper is to include the current component from gate edges in the calculation of the tunneling I - V characteristics. To accomplish this we have used the conformal mapping technique. The cell geometry, defined in the physical domain or z-plane (Fig. 3a), is mapped to a model
Field Oxide
Itl
I~
Wg
e Oxide
r1
n+ P-Si (a)
n+
I tl
(b) Fig. 2. MOS cell geometry: (a) length cross-section; (b) width cross-section.
293
Tunneling characteristics of MOS structures Y
t.Q
,,
v®
®
:\v
ilt
F
In (I0 I
H
hI
E ''~x F
(a)
E D
I H
h2 1 i G
i B
xl
D
A ~
Hp
H
Co)
A~ u
O
(c)
Fig. 3. Schwarz-Christoffel transformation sequence. domain or w-plane (Fig. 3c), using a transformation function, w = f ( z ) , chosen so that the model domain has a regular shape. The relevant equations for the Schwarz-Christoffel transformation sequence, shown in Fig. 3, are derived in the Appendix. Three parameters are needed to define the transformations~2, hi and h2, which influence the geometry scaling, and the shape/curvature of the gate over the gate to field oxide transition region including values of r~ and r 2, as shown in Fig. 2b. h I and h2 are the transformed locations of the initial and terminal points of the gate edge rounding arc, H and G respectively, and A determines the shape of the rounding arc. The actual shape of the rounding arc GH (Fig. 3a) can be determined by solving eqns (A5-A12) simultaneously. In this paper we used 2 = 1 and varied h2 to adjust the gate edge curvature. Table 1 shows the variation of rt and r2 with parameter h2, for t~ = IOOA, t2=3100]k, and 2 = 1. It is found that as he approaches the lower limit in eqn (A13), a sharp corner is obtained with r~ ~ t2 - t~
nonplanar region, shown as shaded area in Fig. 3c, is given by: ln(lO-Shl)<~u<<.ln(h2),
O<<.v<~x.
Using eqns (A2, A5-A12), the calculated electric field along the gate and substrate surface in the nonplanar region, segments A D and EF respectively, is shown in Fig. 4, for t] = 100 A, Vox = 1 V, 2 = 1, and h2 = 0.0015, as a function of u in the w-plane. The boundaries of the nonplanar region are shown by dotted vertical lines labeled Hp and G. It is seen that the cathode field drops rapidly as corner B is approached. For thermal oxides on silicon, the injected tunneling current from the gate and substrate has been found to follow the Fowler-Nordheim mechanism[5], although for injection from the substrate, due to
2.5
'''1
....
a n d r 2 ~ 0.
t1= 100A
To reduce computational effort, the cell is divided into planar region (where electric field is constant) and nonplanar region (under the gate edge where fields are spatially varying), with injection from each region calculated separately. Numerical calculations for the nonplanar region are performed in the w-plane. The boundaries of the nonplanar region are given by electric field considerations. From Fig. 3b and eqns (A2), (A5) and (A6), it is seen that at a point x~ on the segment DH, 0 < x~ < hi, the electric field is close to the planar region values, and this is used to define the extension of the nonplanar edge region under the gate oxide; we used xm= 10-Sh~. For extension under the field oxide region, we let Xl = h2, since the electric field rapidly goes to zero as the concave comer B is approached. In the w-plane, the
Vox= 1Volt
I''''
I''
;k=l.0 h2=O.O015
v w
Cote surface
1.5
/
o
\
Substrate\.
8
surface ~
.6
Table 1. Variation of gate edge curvature with transformation parametersh 2 Transformation SegmentGB SegmentCH parameter, h 2 length,r I (#m) length,r2 (~m) 0.0015 0.2993 0.000834 0.002 0.2982 0.002465 0.004 0.2940 0.02248
(1)
p -20
i Ii i i -I,5
-10
-5
u
Fig. 4. Electric field at gate and substrate surface.
294
R. RAMASWAMIand H. C. LIN
confinement of inversion layer electrons in silicon, most of the tunneling current arises from the lowest sub-band at energy E019,10]. The current density for gate and substrate injections is given by:
Jg,~,<=
q 3e
2
m
j
(. qeh
E.oxEk~213
E°=~a\2rrx//~,,
"]sub = 0
E2°~/'"
r t_ 1 +
;
l
2q~m*_
x e x p (l - 83n
F =
(5)
where, depending on the injecting electrode, J refers to either J,a,, or ,/sub. From first-order kinetics, the electron trapping rate is given by[13,14]:
dntr = Op(No -- ntp) dF
(6)
E2 -~
~
O'g
(7)
-
"
Ig'(Um, V)[ dv
E0)J
~ q2m*(4~b t _ ~ , - Eo)312.}
J dt
(3)
/
m: o m~i(dPb --
(2)
fluence F at time t, defined as the total number of electrons injected per unit area is given by:
n, = n+ + n,g
(8)
(4)
where, 0 = 0.626 at 300 K is the fraction of inversion layer electrons at energy Eo, Ek is the field at the cathode, ~bb is the barrier height, m is the free electron mass, ms,.= 0.916 m and m * are the electron effective masses in silicon and oxide respectively, h is the Planck's constant, Z0 = 2.338 is the first zero of the Airy function, and E~, Eox are the silicon and oxide dielectric constants. Although eqns (3-4) have been derived from planar interfaces[10], the physical justification for using these equations in the nonplanar regions is that the substrate tunneling current is almost independent of gate edge curvature. For sharp gate edge corner, the current from nonlinear region is very small compared to planar region current, and for diffused corners the cathode electric field is almost spatially invariant. Electron transport through the oxide causes trapping at pre-stress and generated trap sites which causes oxide degradation and affects the conduction characteristics. To simplify the numerical solution we assume that: (a) change in the current density due to charge trapping is neglible, div J ~ 0 and electrons flow along field lines[11]; and (b) trapped electrons are totally imaged by the anode and do not interact with each other[12]. Assumption (b) can be justified on the grounds that the magnitude of the field of the trapped charges is very small compared to the applied fields necessary for tunneling. Using the above approximations, the model for trapping in oxide is developed to obtain the time dependence in the tunneling characteristics. Let N Obe the volume density of uniformly distributed pre-stress electron trap sites with capture cross-section trp and let g, denote the constant electron trap generation rate (number of traps generated per injected electron) with cross-section %. In the w-plane (Fig. 3c), the electric field becomes uniform and the following eqns (5-17) can be readily derived for electron injection from a point u =Um on the cathode. The
where n,p, n,g are the trapped charge density at pre-stress and post-stress trap sites, and g is the inverse transformation function described in the Appendix. To exactly calculate the cathode field Ek, we have to solve the transformed 2-D Poisson's equation, which incorporates the effect of electrode nonplanarity and oxide trapping:
V~kw =
qen'lg'(u' v)12 - a(u,__v) ; £ox
(9)
£ox
where #(u, v) can be considered the transformed charge density. Approximations (a-b) given earlier reduce eqn (9) to a 1-D problem in the w-plane. The electric field due to trapped charges at a point (u, v) in the w-plane, and the resulting change in the cathode electric field, ¢~Ek due to the oxide trapped charges at u = u,,, v ranging from 0 to n are given in eqns (10-11). Subscripts a, k refer to anode and cathode respectively. For substrate injection va = 0, Vk = ~ and for gate injection v~ = ~, Vk = O. e , [ g ( u ~ , v)] =
a(Um)D)f#[g(um,V)]
(lO)
Eox
~*)]1f~ f~'° q
=
× If'[g(Um,V)lg'(um, r)ldrdv;
(11)
where f is the transformation function described in the Appendix. Defining geometry factor Xg as:
xe(u,,) =
'f"°iz '
(u,~, v)]g'(u,,, r)l
x lg'(Um,V)12dr dr;
(12)
allows the geometry effects to be separated. For a given geometry, this term needs to be calculated only
Tunneling characteristics of MOS structures once initially. For ramped gate voltage Vg = vt, the oxide drop Vox and cathode field Ek are given by:
295
dF.~.[g(u,,,,vk)] dr
FSolf'L~(..,v0]l = Q~ Le,
x(dVo,, qdc,(u-) dnt)] \'~ %x "~
(13)
Vox qen~Kg where v is the ramp-rate, Vfb is the flat-band voltage and ~,, is the Si surface potential. Using eqns (2-4) the planar and nonplanar region currents are calculated below. In the planar region, the cathode field is simply given by Ek = Vo~/tt, which is used to calculate the planar region current density Jpt~. Adding the displacement current component, total current in each region is given as:
I.,t=2L, /
dln(10-Shl)
Jt (u.,
V
It(,,., v,) I
Vk)]!~ du~
+ Eox
(l 5)
Ip~ = (Jp~ + %xV)Lg{ Wg - 2g[ln(10-Sh~), vk]} (16) Ig = Ip~ + I~pt
(17)
where Ipl~, I, m and lg are the planar region, nonplanar region and total gate current. In this analysis we have assumed that the gate and substrate surface are equipotentials. During substrate injection, depending on the cell geometry, this may not be exactly correct in the nonplanar region , and thus we may slightly overestimate I, pt. However, since Ig dependence on the gate edge is very weak, the error can be neglected. The degradation of oxide is known to depend on both the fluence and the cathode field Ek at which charges are injected. Charge to breakdown Qba (defined as the total charge per unit area injected through the oxide until breakdown), determined from substrate injection experiments, is given by [15]:
Qbd=AO exp(~k)
(18)
where Ao, Bo are constants. This relation has been compared with the impact-ionization breakdown model for thin oxides[16]. For time-varying Ek, q,F using F given in eqn (5) is not a true measure of the degradation. This is because Q~a is obtained from constant current stress measurements. Instead, F needs to be normalized to obtain an effective fluence F~o., using a reference breakdown charge Q ~ as follows:
Q~d = Aoexp( B° ~
(19)
(20)
(21)
where E,o, is an arbitrary reference field. Thus for E/ larger than E,¢, F,~ is larger than F and vice versa. This normalizing method is particularly applicable for easy calculation of oxide degradation in floating gate EEPROM cells, since Ek is a function of time during programming operations. 3. C O M P U T E R SIMULATIONS AND DISCUSSION
The above nonlinear differential equations are solved simultaneously using the Runge-Kutta-Verner fifth- and sixth-order method to obtain the timedependent I - V characteristics with oxide breakdown occurring when qF,~ reaches Q ~ . The simulations are done for A1/SiO~/p-Si capacitor dots of area 10-4crn 2. In Fig. 5, F(t) (curves 1,2) and F,R(t ) (curves 3, 4) have been plotted for substrate injection case, for m * = 0.3 m (1, 3) and 0.5 m (2, 4). We next consider the expected starting voltages for Fowler-Nordheim tunneling. Denote by V,+, the positive gate voltage at which the injected substrate current overcomes the noise and displacement currents; and similarly V,_, for gate injection. For p-Si, the flat-band voltage V~ should be negative. This implies a built-in field directed towards the substrate
1021 rn'=0.3m ~
1020
./
10TM
101e 101z
=o tOTM .7 ~_o to TM bJ ~" 10 TM E L~
10~3 1012 1011
/
/ / /
tl = 100A Area=l O-4cm2 Sub tnjection
tO 1o 4
F,s=
~
6
8 10 12 Gate Voltage, V~ (V)
t4
Fig, 5. Comparison of fluence and effective fluence for substrate injection.
296
R. RAMASWAMIand H. C.
which tends to lower V,+ while increasing V,_. The quantization of the inversion layer electrons increases their energy, which again tends to reduce V,+, since the average Si/SiO2 barrier height q~b is reduced. On the other hand, during substrate injection the surface potential is about 2~bI for MOS capacitors which tends to increase V~+. For tunneling experiments using MOSFETs, the source, drain and bulk are connected to ground and bias is applied to the gate. Once the channel surface becomes inverted, the surface potential goes to 2@I, and almost all the applied gate voltage is applied across the oxide since there is negligible drop in the substrate as for a capacitor. For poly/oxide/poly capacitors, Ellis[17] has shown that the observed gate injection current can be better explained by assuming that the undersurface of the upper poly has concave-like asperities, which reduce the cathode field compared to a planar undersurface. This is supported by evidence from SEM studies. This effect would again tend to increase V~_. The calculated tunneling current in MOS capacitors for planar gate and substrate injection, i.e. neglecting any edge effects, with substrate doping N o 4 x 1015cm -3, gate oxide thickness fl = 100 ~ , m * = 0 . 5 m , N0=101Scm -3, and % = 1 0 - ~ r c m 2 is shown in Fig. 6. It is seen that V,_ ~ 9 V and V,+ ~ 6 V. On the contrary, our experiments show that V,_ ~< V, +. Experimental data from others also show that for a given stress current the gate injection begins earlier than substrate injection[5,18]. We
LZN
10-z
,< v
10-6
m*=O.5m tl= 100A hz=O.O015 Ew=7.4MV/cm Sub Injection •
- lp~n
c~ i0 -9
Ig, Ipl n
8
c
g h-
g 10-'1
z
K
o
a_ tO-~2
=
10-z
i 0 -3
I
'
'
m*=O.5m t~= 100A =
'
'
I
'
'
'
'
I
'
'
'
Sub Inj / -
10 -4 /' tO-5
'
/
/
Gate Inj // // //
/
10 -6
10 -r
"5 10-s (.9
10-9
i 0 -Io
10-~
tO -12 i0 15 Gate Voltage, V~ (V)
20
Fig. 6. Substrate and gate tunneling I - V characteristics (neglecting edge effects).
10
' 1 0 -5
3x10 -5
10 -4
~ 3x10 -4
t0 -3
3x10 -3
10 -a
Area (am 2)
Fig. 7. Substrate tunneling current vs gate area, in planar and nonplanar regions, for constant cathode filled. believe this can be explained by edge effect considerations. Lenzlinger[5] studied the effect of edges on substrate injection by varying the area/perimeter (A/P) ratios. As we show in this paper, corner effects are minimal at the substrate surface as far as tunneling currents are concerned. In Fig. 7, I~, Ip/, and I,p t, calculated at a fixed cathode field Ek = 7.4 MV/cm, are shown for capacitors with A varying from 10 -5 to 10-2cm 2 and P = 2x/CA-~, for 2 = 1 and h 2 =0.0015. Although I,# varies with P, it is negligibly small compared to Ig, and hence only the Ig scaling with A is observed. The dependence of tunneling I - V characteristics on gate edge curvature for substrate and gate injections is shown in Figs 8-9, where h2 is varied from 0.0015 to 0.004, and the previously described values for m*, No, h, ap etc. have been used. It is seen that the gate edge curvature has little effect on the substrate injection but significantly affects the gate injection characteristics. Since Vs+ is primarily affected by rn* while Vs_ is affected by both m * and h2, the effective gate edge curvature can be obtained by adjusting h2 until V~_ from simulations matches the experimental value, using m* extracted from substrate injection experiments. Using the effective gate edge curvature, oxide parameters at the gate interface can now be extracted from gate injection experiments. In the analysis, we have assumed that the electron effective mass in the oxide is independent of the injecting electrode. We briefly mention the relevant papers to justify this. DiMaria[19] has shown from
Tunneling characteristics of MOS structures photoemission measurements that the average barrier height between poly/oxide and Si/oxide is same. The increased tunneling current for poly/oxide structures was attributed to local enhancement at convex asperities. Other models for tunnel injection from poly/oxide/poly and poly/oxide/Si structures have explained the I - V characteristics by attributing it to local surface topology[12,20-24]. In this paper, this idea has been extended to study edge conduction in MOS structures. We use ~b~= 3.15 eV for AI and 3.2 eV for Si and polysilicon respectively[25] with m * obtained from substrate injection experiments. Furthermore, it has been experimentally observed that there is asymmetry in Qbd for gate and substrate injection. In this discussion Qbd- stands for gate injection and Qbd+ for substrate injection. For both poly/oxide/Si and Al/oxide/Si structures, Qbd- is less po~y[2 6]. For poly/oxide/poly than Q~+ with Q~_ < Q~_ capacitors, the situation is reversed. It is observed that Qbd- /Qba+ "~ 50 even though the average field is much higher than injection from the upper gate[27]. In this case, the lower poly exhibits strong localized field enhancement due to convex asperities on the upper surface, and it can be concluded that the dominant failure mechanism is determined by localized current density, rather than the average field. This Qbd asymmetry in MOS capacitors has been assumed to be due to different oxide parameters at the gate and substrate interface[24]. We believe this
10 -4
m*=0.Sm
tl= 100A Area= 10-4cm 2 Sub ' '
/ / /
10-5
I 0 -s
10 - r C_)
o
10 -3
10-4
m*=O.5m t~= 100A Area= 10-4crn 2 Gate Injection
10-5
i 0 -e
10-r I
o
/
I / I
lO-S
8 10-9
/ / ,"/ /I
2,,';,
/
/
I/
10 -lo
/
/i ///
i0-11
10-Iz 4
6
8 10 12 Gate Voltage, Vg (V)
14
16
Fig. 9. Gate tunneling 1-V curves with gate edge curvature as parameter: (I) h= = 0.0015; (2) h2 = 0.002; (3) h= = 0.004.
explanation is not entirely correct because edge effects have been neglected. In Fig. 10, we compare the breakdown fluence Fbd in the planar region for gate and substrate injection, as a function of the edge curvature parameter h2. By planar region F u , we mean the fluence value in the planar region when oxide breakdown occurs. This Fbd value is used for comparison purposes because the nonplanar region fluence has spatial variation. F o r given material properties, it can be seen that F u is a strong function of curvature for gate injection and almost invariant for substrate injection. Since the normalized fluence values in both planar and nonplanar regions are calculated, breakdown at random defect sites is not neglected. We believe that our model is the most comprehensive to date and provides a consistent theoretical explanation for all the observed phenomena.
10-2
10-3
297
i 0 -a
10-9
4. EXPERIMENTS AND PARAMETER EXTRACTION 10-~o
I0-~
10-~2 I 4
6
8 10 12 Gate Voltage, Vg (V)
14
Fig. 8. Substrate tunneling I - I / curves with gate edge curvature as parameter (h: = 0.0015, 0.002, 0.004). The curves lie on top of one another.
Silicon p-type wafers for (100) orientation with a resistivity of 3-5 ~-cm were used as starting material. Gate oxide of thickness 312 k was grown at 900°C for 140min. Polysilicon gate of thickness 3000/~ was deposited and doped by phosphorus diffusion at 900°C to get a sheet resistance of 92 ta-cm. After metallization the wafer was sintered at 375°C for 45 min in nitrogen. Source/drain for MOSFETs was formed by 60 keV As implantation at a dose of
298
R. RAMASWAMI a n d H . C. LIN
10z4~ . . . . t02°~ -
I ....
~.
i i i
_~
'
~
Sub Injection
l
10 -4 . . . .
--_
10 -5
1049~
/,m
104a ~
/,/Gate Injection
/x
z
?E
l°4r --
u lO~e
/
/
tO 13
1012 tO lI
/
/
/
/
/
1040
109
'
'
'
I
10 -1°
10-11
iO -42 I i I 10
5
Fig. 10. Breakdown fluence in the planar region vs gate edge curvature.
. . . .
I
. . . .
I
'] '
| J ]
t1=312A hz=O.0157
[
10 -6
10 -7
~ tO-a o
10-9
10-4o
10 -44
i
I
I/
I
I
i
l
l
20 30 Gate Voltage, V~ (V)
i
i
Fig.
I
I
20 30 Gate Voltage, Vo (V)
I I I
40
12. Gate tunneling I-V characteristics under rampvoltage stress. ( 0 ) E x p e r i m e n t s ; ( - - ) s i m u l a t i o n s .
2 x 1015 cm -2 through 50 ,~, oxide. M O S F E T s with Lg/Wg of 5/50 and 10/50 # m were used in this study. The gate and substrata tunneling Ig-Vg curves were measured by applying a ramp voltage to the gate, effective ramp rate v = _+0.25 V/s, with source, drain and bulk grounded, and recording the gate current Ig on a HP4145 parameter analyzer. Substrate injection was done on 10/50#m device and m* obtained for this measurement applied to characterize gate injection on 5/50 # m device. The measured and simulated Ig-Vg characteristics for substrate and gate injections are shown in Figs I 1 and 12. For the substrata injection the following parameters were used in the simulation: rn* = 0.46 m, N O= 1017 c m -3, 0-, = l0 19cm 2, and A0 = 8 x 10 -3 C/ cm 2, B 0 = 5 . 8 x 107V/cm. For the gate injection, the parameter values were: N o = 1017cm -3, a , = 10-]9 cm 2, and A 0 = 0.7 C/cm 2, B 0 = 11.5 × 107 V/cm. By adjusting the corner rounding parameters until the starting voltage for gate injection V,_ matches the experiments, we obtained 2 = l, h2=0.0157, which gives rl = 2954.9 ~ and r 2 = 58.96 ,~. We see that excellent agreement between simulation and experiments is obtained.
'
!
Substrote Injection m*=O.46m L/W= 10#/50/~
I
•
m*=O.5m t~= 100A Area= 10-4cm a
2 3 4 Gate Edge Curvature Parameter, h2
I
•
10 -9
, I , , , , l L , , l l , , , I
10
'
10 -8
i
tO -~2
I
(D o
t
9
'
10 -7
/ /
=
t 0 -s
'
10-6
/ / / / / / / / / /
1014
10 -4
'
Gate injection m*=O.4-6m L/W=5#/50# ti=312A h2=O.O 157
///I/
b_~ 1046
[]
:
'
5. CONCLUSIONS
i
40
Fig. 11. Substrate tunneling I - V c h a r a c t e r i s t i c s u n d e r ramp-voltage stress. ( 0 ) E x p e r i m e n t s ; ( - - ) s i m u l a t i o n s .
The
main
objective
of this paper
was
to present
a detailed model to simulate the time-dependent tunneling I-V characteristics in MOS structures in-
299
Tunneling characteristics of MOS structures edge effects. Our results show that edge conduction is very important and cannot be neglected when studying the degradation and reliability of oxides using MOS capacitors. We have also presented a method of extracting an effective gate edge curvature from simple ramp-stressed Z-V measurements. corporating
Acknowledgements-This
work was partly supported by Westinghouse Electric Corporation, Baltimore, Maryland through the University of Maryland-Westinghouse Fellowship program. We thank Dr M. Peckerar, D. Ma and N. Saks at Naval Research Laboratory for providing the samples and allowing liberal use of their facilities for experiments.
conformally transformed to a model domain (w-plane), where w = (u, u), using an analytic function, w = f(z) with the inverse transform z = g(w). Then any function 4(x, y) defined in the z-plane can be transformed to Jl(u, v) such that:
$64 u) = 4k(u, r)l = 41X(&r), Y(% u)l.
(AlI
Typically 4(x, y) and Jl(u, u) would be potential distributions. The transformed relations between the gradients of these functions are given by: v~(x,Y)=v~(~,~)f’~(~,~)l~
(A2)
Let p(x, y) be a function defined in the z-plane, which satisfies the Poisson’s equation, Vt&x, y) = p(x, y) and let a(u, u) = p[g(u, u)] be the conformal transplant of p under the mapping. Then the Poisson’s equation in w-plane can be written as:
REFERENCES
%$(a, u) = u(u, u)(g’(a, r)12.
1. P. Solomon, J. Appl. Phys. 48, 3843 (1977). 2. D. J. DiMaria, R. Ghez and D. W. Dong, J. Appl. Phys.
Even though charge distribution may become more complicated under the transformation, the geometry becomes rectangular and hence numerical solutions can be obtained much faster than solving the problem directly in the z-plane. Let a domain D in the z-plane map to domain E in the w-plane. Then for any real valued function Q(x, y) with image $(u, u) we have:
51, 4830 (1980). 3. K. E. Kroell and G. K. Ackermann, Solid-St. Electron. 19, 77 (1976). 4. W. P. Noble and P. E. Cottrell. ZEDM Tech. Dia.. _ 582 (1976).
(A3)
5. M. Lenxlinger and E. H. Snow, J. Appl. Phys. 40, 278 (1969).
6. J. Masejian, J. Vuc. Sci. Technol. 11, 996 (1974). 7. B. Eitan and A. Kolodny, Appl. Phys. L&t. 43, 106 (19
).
8. S. Sze, Physics of Semiconductor Devices, 2nd edn. Wiley-Interscience, New York (1981). 9. Z. A. Weinberg, Solid-St. Electron. 20, 11 (1977). 10. Z. A. Weinberg, J. Appl. Phys. 53, 5052 (1982). 11. J. Bisschop, E. J. Korma, E. F. F. Botta and J. R. Venvey, IEEE Trans. Electron. Devices ED-33, 1809 (1986). 12. A. Bhattacharyya, Solid-St. Electron. 27, 899 (1984). 13. T. H. Ning and H. N. Yu, J. Appl. Phys. 45, 5373
&x,y)dudy = aS(u,u)lg’(u,u)l’dudu. (A4) ID s The cell cross-section in the physical and model domains is shown in Figs 2-3. The cell geometry is defined by t, , t,, 0, and 02, the gate and field oxide thickness, and oxide tapering angle over the transition regions. The transfonnation functions, w = f(z) and z = g(w), are given by eqns (AS-A6), and the boundary conditions by eqns (A7-A13). dz
~,(z,-h,)~+L(z,-h~)~
dz,
zr
_=-
(z,-1)Y
tI
w = ln(z,)
(A5) (A6)
(1974).
y=e,-1=1-e,
14. M. S. Liang and C. Hu, ZEDM Tech. Dig., 396 (1981). 15. A. Modelli and B. Ricco, ZEDM Tech. Dig., 148 (1984). 16. I. C. Chen, S. Holland and C. Hu, Proc. Znt. Rel. Phys. Symp., 24 (1985). 17. R. Ellis, H. A. R. Wegener and J. M. Caywood, ZEDM Tech. Dig., 749 (1982). 18. E. Harari. J. Aool. Phvs. 49. 2478 (1978). 19. D. J. DiMaria ‘and D: R. Kerr, Adpl. ihys. Lett. 27, 505 (1975). 20. R. Ellis, IEEE Electron Deoices Lett. EDW, 330 (1982). 21. H. A. R. Wegener, ZEDM Tech. Dig., 480 (1984). 22. R. Jolly et al., IEEE Trans. Electron. Devices ED-31,
(A7)
O
1>0
(A8)
@2/t,1
c’= -n(l+l) hi+I.hhq=
-;
I
(Al’3
767 (1984). 23. C-F. Chen and C-Y. Wu, Solid-St. Electron. 29, 1059 (1986).
24. C-F. Chen and C-Y. Wu, J. Appl. Phys. 60, 3926
-r2
+
i(t, - t,) cl t,
(1986).
25. R. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd edn (1986). 26. J. J. Van der Schoot and D. R. Wolters, Ins. Films Sem. INFOS 1983, 270 (1983). 27. L. Faraone, R. D. Vibronek and J. T. McGinn, IEEE Trans. Electron Devices ED-32, 577 (1985). 28. R. V. Churchill, Complex Variables and Applications, 3rd edn. (1976).
APPENDIX The complex transformation method is described in [28].As shown in Fig. 3, the cell geometry is described in the physical domain (z-plane) where I = x + iy = (x, y). This domain is SSE W-F
We used y = 0.5 in our analysis, which is equivalent to a sharp step over the transition regions. The curvature of the gate edge can be varied by the transformation parameters h,, h,, 1, of which only two can be chosen independently with the third defined by the cell geometry. In this analysis, we choose 1 and h, with h, derived from above equations. For a given I, h, is restricted by: (Al3)
0038-1101/91 $3.00 + 0.00 Copyright © 1991 Pergamon Press plc
Printed in Great Britain. All rights reserved
SIMULATION OF TIME-DEPENDENT T U N N E L I N G CHARACTERISTICS OF MOS STRUCTURES R. RA~SWAm and H. C. LfN Department of Electrical Engineering, University of Maryland, College Park, MD 20742, U.S.A. (Received 15 May 1990; in revisedform 25 August 1990) Abstract--A detailed model has been developed to simulate the Fowler-Nordheim tunneling and degradation characteristics of thermal oxides on silicon incorporating geometry effects, trapping at pre-stress and post-stress trap sites, and field dependent charge to breakdown. For the first time, the effect of gate edge on the time-dependent tunneling characteristics has been quantitatively analyzed, using the Schwarz-Christoffel transformation method. It is found that gate edge region can enhance the tunneling current significantly and also accelerate oxide degradation and breakdown. One application of this model is to remove geometry effects in the oxide parameters extracted using ramp-stress measurements. Another application is to use the asymmetry in gate and substrate injections to electrically characterize the gate geometry and obtain an effective edge curvature.
NOTATION
tt t2
Or, 02 J
J,o,~ J~,, In,, i, F
i% Q~
Q~
do, Be
e,.i
Ek
No % gt % tltp ntg nt
v~ Vox
V
v~ q~ m m* ms~
h £s ~'ox
Eo
length of the capacitor/transistor width of the capacitor/transistor gate oxide thickness field oxide thickness gate tapering angles over the gate to field oxide transition region tunneling current density tunneling current density from gate tunneling current density from substrate tunneling current density in planar region total current from planar region total current from nonplanar region total gate current injected fluence effective injected fluence breakdown fluence in planar region charge to breakdown for oxide reference charge to breakdown for oxide breakdown coefficients reference cathode electric field for breakdown calculation field at cathode surface volume density of pre-stress traps capture cross-section of pre-stress traps electron trap generation rate capture cross-section of generated traps trapped charge density at pre-stress trap sites trapped charge density at generated trap sites total trapped charge density applied gate voltage voltage drop across oxide fiat-band voltage silicon surface potential gate voltage ramp rate starting voltage for Fowler-Nordheim tunneling electron charge free-electron mass electron effective mass in oxide electron effective mass in silicon barrier height Planck's constant silicon dielectric constant oxide dielectric constant lowest sub-band energy of confined inversion
layer electrons Fermi level substrate doping concentration No analytic function mapping z--,w plane f(z) g(w) analytic function mapping w--,z plane 2, h~,h2 transformation parameters geometry factor originating from electrode non% planarity
291
1. INTRODUCTION
Many floating gate nonvolatile memory devices-FLOTOX, TPFG etc., use high field tunnel injection to transport charges across thin oxides. This process degrades the oxide due to charge trapping, and eventually leads to breakdown. As the dimensions of these devices are scaled down for VLSI applications, trapping effects, dielectric strength and reliability of thin oxides has been extensively studied. Several authors have suggested that thermal oxides can be characterized from ramp-voltage stressed I - V characteristics, i.e. parameters such as capture crosssection, trap density etc., can be extracted from a single measurement[l,2]. However, because of calculational complexity, geometry effects on the tunneling current characteristics have been neglected. By quantifying the geometry effects, oxide parameters can be extracted more accurately. Also, since oxide degradation and breakdown is a field dependent phenomenon, it is necessary to be able to calculate the fields accurately to predict the reliability of thin oxides. In this paper, we develop a method to calculate the time-dependent tunneling current from gate edges in MOS structure. The motivation behind this effort was to study the reliability of FLOTOX cells where the geometry nonplanarity is introduced by floating gate transition from tunnel oxide to gate and field oxide regions. Edge effects are not negligible in small
292
R. RAMASWAMIand H. C. LIN
Ec 3.15e
C-
EFM AI
EF$
P-Si
SiO2
Ev
f
EFM - -
(a)
(b)
Fig. I. Energy band diagram of MOS system: (a) at equilibrium, (b) during electron tunneling from substrate. geometry devices as evidenced by narrow-channel effect, where field reduction at the channel surface under the gate edge region increases the transistor threshold voltage[3,4]. Since tunneling current strongly depends on the cathode field, we expect the comers in the transition region to affect the conduction characteristics. All the analyses so far for tunneling conduction have not taken into account quantitatively the field enhancement at gate edge corners. The use of uniform geometry assumption may be reasonable when transition from tunnel to gate oxide region is gradual but should fail for sharp transitions. This problem is not amenable to standard numerical analysis, because the comers in the transition region depend on the fabrication process and cannot be considered to have uniform shapes, hence, accurate numerical solution of Poisson's equation near these regions may require extremely fine mesh intervals. Additionally, the asymmetric tunneling characteristics can be used to extract an effective gate edge curvature. 2. DETAILED CELL MODEL
When high voltage is applied across the oxide in a MOS system, electrons can be transported via the tunneling mechanism. For thermal oxides thicker than about 70 A, electron transport occurs between
Lg
the gate Fermi level and the Si conduction band, and can be described by the Fowler-Nordheim mechanism[5,6]. In our experiments we used 312 A oxides, in which case current due to direct, valence band and interface state tunneling is negligible[7,8]. The band diagram for Al/SiO2/p-Si system at equilibrium, and during electron injection from the substrate is shown in Fig. 1. During substrate injection, since inversion layer electrons are confined to a narrow potential well at the interface, their energy is quantized normal to the interface as shown in Fig. lb, and the tunneling current is dominated by the electrons from the lowest sub-band with energy E019]. Image-force barrier lowering can be neglected, because it rounds the top of the barrier only and hardly affects the tunneling distance[10]. The geometry of the MOS transistor is shown in Fig. 2, along the length and width directions of the channel, where we have used the tapered oxide approximation to model the device structure. From Fig. 2b, it is seen that due to symmetry, only one-half of the structure needs to be analyzed, as shown in Fig. 3a. Our primary aim in this paper is to include the current component from gate edges in the calculation of the tunneling I - V characteristics. To accomplish this we have used the conformal mapping technique. The cell geometry, defined in the physical domain or z-plane (Fig. 3a), is mapped to a model
Field Oxide
Itl
I~
Wg
e Oxide
r1
n+ P-Si (a)
n+
I tl
(b) Fig. 2. MOS cell geometry: (a) length cross-section; (b) width cross-section.
293
Tunneling characteristics of MOS structures Y
t.Q
,,
v®
®
:\v
ilt
F
In (I0 I
H
hI
E ''~x F
(a)
E D
I H
h2 1 i G
i B
xl
D
A ~
Hp
H
Co)
A~ u
O
(c)
Fig. 3. Schwarz-Christoffel transformation sequence. domain or w-plane (Fig. 3c), using a transformation function, w = f ( z ) , chosen so that the model domain has a regular shape. The relevant equations for the Schwarz-Christoffel transformation sequence, shown in Fig. 3, are derived in the Appendix. Three parameters are needed to define the transformations~2, hi and h2, which influence the geometry scaling, and the shape/curvature of the gate over the gate to field oxide transition region including values of r~ and r 2, as shown in Fig. 2b. h I and h2 are the transformed locations of the initial and terminal points of the gate edge rounding arc, H and G respectively, and A determines the shape of the rounding arc. The actual shape of the rounding arc GH (Fig. 3a) can be determined by solving eqns (A5-A12) simultaneously. In this paper we used 2 = 1 and varied h2 to adjust the gate edge curvature. Table 1 shows the variation of rt and r2 with parameter h2, for t~ = IOOA, t2=3100]k, and 2 = 1. It is found that as he approaches the lower limit in eqn (A13), a sharp corner is obtained with r~ ~ t2 - t~
nonplanar region, shown as shaded area in Fig. 3c, is given by: ln(lO-Shl)<~u<<.ln(h2),
O<<.v<~x.
Using eqns (A2, A5-A12), the calculated electric field along the gate and substrate surface in the nonplanar region, segments A D and EF respectively, is shown in Fig. 4, for t] = 100 A, Vox = 1 V, 2 = 1, and h2 = 0.0015, as a function of u in the w-plane. The boundaries of the nonplanar region are shown by dotted vertical lines labeled Hp and G. It is seen that the cathode field drops rapidly as corner B is approached. For thermal oxides on silicon, the injected tunneling current from the gate and substrate has been found to follow the Fowler-Nordheim mechanism[5], although for injection from the substrate, due to
2.5
'''1
....
a n d r 2 ~ 0.
t1= 100A
To reduce computational effort, the cell is divided into planar region (where electric field is constant) and nonplanar region (under the gate edge where fields are spatially varying), with injection from each region calculated separately. Numerical calculations for the nonplanar region are performed in the w-plane. The boundaries of the nonplanar region are given by electric field considerations. From Fig. 3b and eqns (A2), (A5) and (A6), it is seen that at a point x~ on the segment DH, 0 < x~ < hi, the electric field is close to the planar region values, and this is used to define the extension of the nonplanar edge region under the gate oxide; we used xm= 10-Sh~. For extension under the field oxide region, we let Xl = h2, since the electric field rapidly goes to zero as the concave comer B is approached. In the w-plane, the
Vox= 1Volt
I''''
I''
;k=l.0 h2=O.O015
v w
Cote surface
1.5
/
o
\
Substrate\.
8
surface ~
.6
Table 1. Variation of gate edge curvature with transformation parametersh 2 Transformation SegmentGB SegmentCH parameter, h 2 length,r I (#m) length,r2 (~m) 0.0015 0.2993 0.000834 0.002 0.2982 0.002465 0.004 0.2940 0.02248
(1)
p -20
i Ii i i -I,5
-10
-5
u
Fig. 4. Electric field at gate and substrate surface.
294
R. RAMASWAMIand H. C. LIN
confinement of inversion layer electrons in silicon, most of the tunneling current arises from the lowest sub-band at energy E019,10]. The current density for gate and substrate injections is given by:
Jg,~,<=
q 3e
2
m
j
(. qeh
E.oxEk~213
E°=~a\2rrx//~,,
"]sub = 0
E2°~/'"
r t_ 1 +
;
l
2q~m*_
x e x p (l - 83n
F =
(5)
where, depending on the injecting electrode, J refers to either J,a,, or ,/sub. From first-order kinetics, the electron trapping rate is given by[13,14]:
dntr = Op(No -- ntp) dF
(6)
E2 -~
~
O'g
(7)
-
"
Ig'(Um, V)[ dv
E0)J
~ q2m*(4~b t _ ~ , - Eo)312.}
J dt
(3)
/
m: o m~i(dPb --
(2)
fluence F at time t, defined as the total number of electrons injected per unit area is given by:
n, = n+ + n,g
(8)
(4)
where, 0 = 0.626 at 300 K is the fraction of inversion layer electrons at energy Eo, Ek is the field at the cathode, ~bb is the barrier height, m is the free electron mass, ms,.= 0.916 m and m * are the electron effective masses in silicon and oxide respectively, h is the Planck's constant, Z0 = 2.338 is the first zero of the Airy function, and E~, Eox are the silicon and oxide dielectric constants. Although eqns (3-4) have been derived from planar interfaces[10], the physical justification for using these equations in the nonplanar regions is that the substrate tunneling current is almost independent of gate edge curvature. For sharp gate edge corner, the current from nonlinear region is very small compared to planar region current, and for diffused corners the cathode electric field is almost spatially invariant. Electron transport through the oxide causes trapping at pre-stress and generated trap sites which causes oxide degradation and affects the conduction characteristics. To simplify the numerical solution we assume that: (a) change in the current density due to charge trapping is neglible, div J ~ 0 and electrons flow along field lines[11]; and (b) trapped electrons are totally imaged by the anode and do not interact with each other[12]. Assumption (b) can be justified on the grounds that the magnitude of the field of the trapped charges is very small compared to the applied fields necessary for tunneling. Using the above approximations, the model for trapping in oxide is developed to obtain the time dependence in the tunneling characteristics. Let N Obe the volume density of uniformly distributed pre-stress electron trap sites with capture cross-section trp and let g, denote the constant electron trap generation rate (number of traps generated per injected electron) with cross-section %. In the w-plane (Fig. 3c), the electric field becomes uniform and the following eqns (5-17) can be readily derived for electron injection from a point u =Um on the cathode. The
where n,p, n,g are the trapped charge density at pre-stress and post-stress trap sites, and g is the inverse transformation function described in the Appendix. To exactly calculate the cathode field Ek, we have to solve the transformed 2-D Poisson's equation, which incorporates the effect of electrode nonplanarity and oxide trapping:
V~kw =
qen'lg'(u' v)12 - a(u,__v) ; £ox
(9)
£ox
where #(u, v) can be considered the transformed charge density. Approximations (a-b) given earlier reduce eqn (9) to a 1-D problem in the w-plane. The electric field due to trapped charges at a point (u, v) in the w-plane, and the resulting change in the cathode electric field, ¢~Ek due to the oxide trapped charges at u = u,,, v ranging from 0 to n are given in eqns (10-11). Subscripts a, k refer to anode and cathode respectively. For substrate injection va = 0, Vk = ~ and for gate injection v~ = ~, Vk = O. e , [ g ( u ~ , v)] =
a(Um)D)f#[g(um,V)]
(lO)
Eox
~*)]1f~ f~'° q
=
× If'[g(Um,V)lg'(um, r)ldrdv;
(11)
where f is the transformation function described in the Appendix. Defining geometry factor Xg as:
xe(u,,) =
'f"°iz '
(u,~, v)]g'(u,,, r)l
x lg'(Um,V)12dr dr;
(12)
allows the geometry effects to be separated. For a given geometry, this term needs to be calculated only
Tunneling characteristics of MOS structures once initially. For ramped gate voltage Vg = vt, the oxide drop Vox and cathode field Ek are given by:
295
dF.~.[g(u,,,,vk)] dr
FSolf'L~(..,v0]l = Q~ Le,
x(dVo,, qdc,(u-) dnt)] \'~ %x "~
(13)
Vox qen~Kg where v is the ramp-rate, Vfb is the flat-band voltage and ~,, is the Si surface potential. Using eqns (2-4) the planar and nonplanar region currents are calculated below. In the planar region, the cathode field is simply given by Ek = Vo~/tt, which is used to calculate the planar region current density Jpt~. Adding the displacement current component, total current in each region is given as:
I.,t=2L, /
dln(10-Shl)
Jt (u.,
V
It(,,., v,) I
Vk)]!~ du~
+ Eox
(l 5)
Ip~ = (Jp~ + %xV)Lg{ Wg - 2g[ln(10-Sh~), vk]} (16) Ig = Ip~ + I~pt
(17)
where Ipl~, I, m and lg are the planar region, nonplanar region and total gate current. In this analysis we have assumed that the gate and substrate surface are equipotentials. During substrate injection, depending on the cell geometry, this may not be exactly correct in the nonplanar region , and thus we may slightly overestimate I, pt. However, since Ig dependence on the gate edge is very weak, the error can be neglected. The degradation of oxide is known to depend on both the fluence and the cathode field Ek at which charges are injected. Charge to breakdown Qba (defined as the total charge per unit area injected through the oxide until breakdown), determined from substrate injection experiments, is given by [15]:
Qbd=AO exp(~k)
(18)
where Ao, Bo are constants. This relation has been compared with the impact-ionization breakdown model for thin oxides[16]. For time-varying Ek, q,F using F given in eqn (5) is not a true measure of the degradation. This is because Q~a is obtained from constant current stress measurements. Instead, F needs to be normalized to obtain an effective fluence F~o., using a reference breakdown charge Q ~ as follows:
Q~d = Aoexp( B° ~
(19)
(20)
(21)
where E,o, is an arbitrary reference field. Thus for E/ larger than E,¢, F,~ is larger than F and vice versa. This normalizing method is particularly applicable for easy calculation of oxide degradation in floating gate EEPROM cells, since Ek is a function of time during programming operations. 3. C O M P U T E R SIMULATIONS AND DISCUSSION
The above nonlinear differential equations are solved simultaneously using the Runge-Kutta-Verner fifth- and sixth-order method to obtain the timedependent I - V characteristics with oxide breakdown occurring when qF,~ reaches Q ~ . The simulations are done for A1/SiO~/p-Si capacitor dots of area 10-4crn 2. In Fig. 5, F(t) (curves 1,2) and F,R(t ) (curves 3, 4) have been plotted for substrate injection case, for m * = 0.3 m (1, 3) and 0.5 m (2, 4). We next consider the expected starting voltages for Fowler-Nordheim tunneling. Denote by V,+, the positive gate voltage at which the injected substrate current overcomes the noise and displacement currents; and similarly V,_, for gate injection. For p-Si, the flat-band voltage V~ should be negative. This implies a built-in field directed towards the substrate
1021 rn'=0.3m ~
1020
./
10TM
101e 101z
=o tOTM .7 ~_o to TM bJ ~" 10 TM E L~
10~3 1012 1011
/
/ / /
tl = 100A Area=l O-4cm2 Sub tnjection
tO 1o 4
F,s=
~
6
8 10 12 Gate Voltage, V~ (V)
t4
Fig, 5. Comparison of fluence and effective fluence for substrate injection.
296
R. RAMASWAMIand H. C.
which tends to lower V,+ while increasing V,_. The quantization of the inversion layer electrons increases their energy, which again tends to reduce V,+, since the average Si/SiO2 barrier height q~b is reduced. On the other hand, during substrate injection the surface potential is about 2~bI for MOS capacitors which tends to increase V~+. For tunneling experiments using MOSFETs, the source, drain and bulk are connected to ground and bias is applied to the gate. Once the channel surface becomes inverted, the surface potential goes to 2@I, and almost all the applied gate voltage is applied across the oxide since there is negligible drop in the substrate as for a capacitor. For poly/oxide/poly capacitors, Ellis[17] has shown that the observed gate injection current can be better explained by assuming that the undersurface of the upper poly has concave-like asperities, which reduce the cathode field compared to a planar undersurface. This is supported by evidence from SEM studies. This effect would again tend to increase V~_. The calculated tunneling current in MOS capacitors for planar gate and substrate injection, i.e. neglecting any edge effects, with substrate doping N o 4 x 1015cm -3, gate oxide thickness fl = 100 ~ , m * = 0 . 5 m , N0=101Scm -3, and % = 1 0 - ~ r c m 2 is shown in Fig. 6. It is seen that V,_ ~ 9 V and V,+ ~ 6 V. On the contrary, our experiments show that V,_ ~< V, +. Experimental data from others also show that for a given stress current the gate injection begins earlier than substrate injection[5,18]. We
LZN
10-z
,< v
10-6
m*=O.5m tl= 100A hz=O.O015 Ew=7.4MV/cm Sub Injection •
- lp~n
c~ i0 -9
Ig, Ipl n
8
c
g h-
g 10-'1
z
K
o
a_ tO-~2
=
10-z
i 0 -3
I
'
'
m*=O.5m t~= 100A =
'
'
I
'
'
'
'
I
'
'
'
Sub Inj / -
10 -4 /' tO-5
'
/
/
Gate Inj // // //
/
10 -6
10 -r
"5 10-s (.9
10-9
i 0 -Io
10-~
tO -12 i0 15 Gate Voltage, V~ (V)
20
Fig. 6. Substrate and gate tunneling I - V characteristics (neglecting edge effects).
10
' 1 0 -5
3x10 -5
10 -4
~ 3x10 -4
t0 -3
3x10 -3
10 -a
Area (am 2)
Fig. 7. Substrate tunneling current vs gate area, in planar and nonplanar regions, for constant cathode filled. believe this can be explained by edge effect considerations. Lenzlinger[5] studied the effect of edges on substrate injection by varying the area/perimeter (A/P) ratios. As we show in this paper, corner effects are minimal at the substrate surface as far as tunneling currents are concerned. In Fig. 7, I~, Ip/, and I,p t, calculated at a fixed cathode field Ek = 7.4 MV/cm, are shown for capacitors with A varying from 10 -5 to 10-2cm 2 and P = 2x/CA-~, for 2 = 1 and h 2 =0.0015. Although I,# varies with P, it is negligibly small compared to Ig, and hence only the Ig scaling with A is observed. The dependence of tunneling I - V characteristics on gate edge curvature for substrate and gate injections is shown in Figs 8-9, where h2 is varied from 0.0015 to 0.004, and the previously described values for m*, No, h, ap etc. have been used. It is seen that the gate edge curvature has little effect on the substrate injection but significantly affects the gate injection characteristics. Since Vs+ is primarily affected by rn* while Vs_ is affected by both m * and h2, the effective gate edge curvature can be obtained by adjusting h2 until V~_ from simulations matches the experimental value, using m* extracted from substrate injection experiments. Using the effective gate edge curvature, oxide parameters at the gate interface can now be extracted from gate injection experiments. In the analysis, we have assumed that the electron effective mass in the oxide is independent of the injecting electrode. We briefly mention the relevant papers to justify this. DiMaria[19] has shown from
Tunneling characteristics of MOS structures photoemission measurements that the average barrier height between poly/oxide and Si/oxide is same. The increased tunneling current for poly/oxide structures was attributed to local enhancement at convex asperities. Other models for tunnel injection from poly/oxide/poly and poly/oxide/Si structures have explained the I - V characteristics by attributing it to local surface topology[12,20-24]. In this paper, this idea has been extended to study edge conduction in MOS structures. We use ~b~= 3.15 eV for AI and 3.2 eV for Si and polysilicon respectively[25] with m * obtained from substrate injection experiments. Furthermore, it has been experimentally observed that there is asymmetry in Qbd for gate and substrate injection. In this discussion Qbd- stands for gate injection and Qbd+ for substrate injection. For both poly/oxide/Si and Al/oxide/Si structures, Qbd- is less po~y[2 6]. For poly/oxide/poly than Q~+ with Q~_ < Q~_ capacitors, the situation is reversed. It is observed that Qbd- /Qba+ "~ 50 even though the average field is much higher than injection from the upper gate[27]. In this case, the lower poly exhibits strong localized field enhancement due to convex asperities on the upper surface, and it can be concluded that the dominant failure mechanism is determined by localized current density, rather than the average field. This Qbd asymmetry in MOS capacitors has been assumed to be due to different oxide parameters at the gate and substrate interface[24]. We believe this
10 -4
m*=0.Sm
tl= 100A Area= 10-4cm 2 Sub ' '
/ / /
10-5
I 0 -s
10 - r C_)
o
10 -3
10-4
m*=O.5m t~= 100A Area= 10-4crn 2 Gate Injection
10-5
i 0 -e
10-r I
o
/
I / I
lO-S
8 10-9
/ / ,"/ /I
2,,';,
/
/
I/
10 -lo
/
/i ///
i0-11
10-Iz 4
6
8 10 12 Gate Voltage, Vg (V)
14
16
Fig. 9. Gate tunneling 1-V curves with gate edge curvature as parameter: (I) h= = 0.0015; (2) h2 = 0.002; (3) h= = 0.004.
explanation is not entirely correct because edge effects have been neglected. In Fig. 10, we compare the breakdown fluence Fbd in the planar region for gate and substrate injection, as a function of the edge curvature parameter h2. By planar region F u , we mean the fluence value in the planar region when oxide breakdown occurs. This Fbd value is used for comparison purposes because the nonplanar region fluence has spatial variation. F o r given material properties, it can be seen that F u is a strong function of curvature for gate injection and almost invariant for substrate injection. Since the normalized fluence values in both planar and nonplanar regions are calculated, breakdown at random defect sites is not neglected. We believe that our model is the most comprehensive to date and provides a consistent theoretical explanation for all the observed phenomena.
10-2
10-3
297
i 0 -a
10-9
4. EXPERIMENTS AND PARAMETER EXTRACTION 10-~o
I0-~
10-~2 I 4
6
8 10 12 Gate Voltage, Vg (V)
14
Fig. 8. Substrate tunneling I - I / curves with gate edge curvature as parameter (h: = 0.0015, 0.002, 0.004). The curves lie on top of one another.
Silicon p-type wafers for (100) orientation with a resistivity of 3-5 ~-cm were used as starting material. Gate oxide of thickness 312 k was grown at 900°C for 140min. Polysilicon gate of thickness 3000/~ was deposited and doped by phosphorus diffusion at 900°C to get a sheet resistance of 92 ta-cm. After metallization the wafer was sintered at 375°C for 45 min in nitrogen. Source/drain for MOSFETs was formed by 60 keV As implantation at a dose of
298
R. RAMASWAMI a n d H . C. LIN
10z4~ . . . . t02°~ -
I ....
~.
i i i
_~
'
~
Sub Injection
l
10 -4 . . . .
--_
10 -5
1049~
/,m
104a ~
/,/Gate Injection
/x
z
?E
l°4r --
u lO~e
/
/
tO 13
1012 tO lI
/
/
/
/
/
1040
109
'
'
'
I
10 -1°
10-11
iO -42 I i I 10
5
Fig. 10. Breakdown fluence in the planar region vs gate edge curvature.
. . . .
I
. . . .
I
'] '
| J ]
t1=312A hz=O.0157
[
10 -6
10 -7
~ tO-a o
10-9
10-4o
10 -44
i
I
I/
I
I
i
l
l
20 30 Gate Voltage, V~ (V)
i
i
Fig.
I
I
20 30 Gate Voltage, Vo (V)
I I I
40
12. Gate tunneling I-V characteristics under rampvoltage stress. ( 0 ) E x p e r i m e n t s ; ( - - ) s i m u l a t i o n s .
2 x 1015 cm -2 through 50 ,~, oxide. M O S F E T s with Lg/Wg of 5/50 and 10/50 # m were used in this study. The gate and substrata tunneling Ig-Vg curves were measured by applying a ramp voltage to the gate, effective ramp rate v = _+0.25 V/s, with source, drain and bulk grounded, and recording the gate current Ig on a HP4145 parameter analyzer. Substrate injection was done on 10/50#m device and m* obtained for this measurement applied to characterize gate injection on 5/50 # m device. The measured and simulated Ig-Vg characteristics for substrate and gate injections are shown in Figs I 1 and 12. For the substrata injection the following parameters were used in the simulation: rn* = 0.46 m, N O= 1017 c m -3, 0-, = l0 19cm 2, and A0 = 8 x 10 -3 C/ cm 2, B 0 = 5 . 8 x 107V/cm. For the gate injection, the parameter values were: N o = 1017cm -3, a , = 10-]9 cm 2, and A 0 = 0.7 C/cm 2, B 0 = 11.5 × 107 V/cm. By adjusting the corner rounding parameters until the starting voltage for gate injection V,_ matches the experiments, we obtained 2 = l, h2=0.0157, which gives rl = 2954.9 ~ and r 2 = 58.96 ,~. We see that excellent agreement between simulation and experiments is obtained.
'
!
Substrote Injection m*=O.46m L/W= 10#/50/~
I
•
m*=O.5m t~= 100A Area= 10-4cm a
2 3 4 Gate Edge Curvature Parameter, h2
I
•
10 -9
, I , , , , l L , , l l , , , I
10
'
10 -8
i
tO -~2
I
(D o
t
9
'
10 -7
/ /
=
t 0 -s
'
10-6
/ / / / / / / / / /
1014
10 -4
'
Gate injection m*=O.4-6m L/W=5#/50# ti=312A h2=O.O 157
///I/
b_~ 1046
[]
:
'
5. CONCLUSIONS
i
40
Fig. 11. Substrate tunneling I - V c h a r a c t e r i s t i c s u n d e r ramp-voltage stress. ( 0 ) E x p e r i m e n t s ; ( - - ) s i m u l a t i o n s .
The
main
objective
of this paper
was
to present
a detailed model to simulate the time-dependent tunneling I-V characteristics in MOS structures in-
299
Tunneling characteristics of MOS structures edge effects. Our results show that edge conduction is very important and cannot be neglected when studying the degradation and reliability of oxides using MOS capacitors. We have also presented a method of extracting an effective gate edge curvature from simple ramp-stressed Z-V measurements. corporating
Acknowledgements-This
work was partly supported by Westinghouse Electric Corporation, Baltimore, Maryland through the University of Maryland-Westinghouse Fellowship program. We thank Dr M. Peckerar, D. Ma and N. Saks at Naval Research Laboratory for providing the samples and allowing liberal use of their facilities for experiments.
conformally transformed to a model domain (w-plane), where w = (u, u), using an analytic function, w = f(z) with the inverse transform z = g(w). Then any function 4(x, y) defined in the z-plane can be transformed to Jl(u, v) such that:
$64 u) = 4k(u, r)l = 41X(&r), Y(% u)l.
(AlI
Typically 4(x, y) and Jl(u, u) would be potential distributions. The transformed relations between the gradients of these functions are given by: v~(x,Y)=v~(~,~)f’~(~,~)l~
(A2)
Let p(x, y) be a function defined in the z-plane, which satisfies the Poisson’s equation, Vt&x, y) = p(x, y) and let a(u, u) = p[g(u, u)] be the conformal transplant of p under the mapping. Then the Poisson’s equation in w-plane can be written as:
REFERENCES
%$(a, u) = u(u, u)(g’(a, r)12.
1. P. Solomon, J. Appl. Phys. 48, 3843 (1977). 2. D. J. DiMaria, R. Ghez and D. W. Dong, J. Appl. Phys.
Even though charge distribution may become more complicated under the transformation, the geometry becomes rectangular and hence numerical solutions can be obtained much faster than solving the problem directly in the z-plane. Let a domain D in the z-plane map to domain E in the w-plane. Then for any real valued function Q(x, y) with image $(u, u) we have:
51, 4830 (1980). 3. K. E. Kroell and G. K. Ackermann, Solid-St. Electron. 19, 77 (1976). 4. W. P. Noble and P. E. Cottrell. ZEDM Tech. Dia.. _ 582 (1976).
(A3)
5. M. Lenxlinger and E. H. Snow, J. Appl. Phys. 40, 278 (1969).
6. J. Masejian, J. Vuc. Sci. Technol. 11, 996 (1974). 7. B. Eitan and A. Kolodny, Appl. Phys. L&t. 43, 106 (19
).
8. S. Sze, Physics of Semiconductor Devices, 2nd edn. Wiley-Interscience, New York (1981). 9. Z. A. Weinberg, Solid-St. Electron. 20, 11 (1977). 10. Z. A. Weinberg, J. Appl. Phys. 53, 5052 (1982). 11. J. Bisschop, E. J. Korma, E. F. F. Botta and J. R. Venvey, IEEE Trans. Electron. Devices ED-33, 1809 (1986). 12. A. Bhattacharyya, Solid-St. Electron. 27, 899 (1984). 13. T. H. Ning and H. N. Yu, J. Appl. Phys. 45, 5373
&x,y)dudy = aS(u,u)lg’(u,u)l’dudu. (A4) ID s The cell cross-section in the physical and model domains is shown in Figs 2-3. The cell geometry is defined by t, , t,, 0, and 02, the gate and field oxide thickness, and oxide tapering angle over the transition regions. The transfonnation functions, w = f(z) and z = g(w), are given by eqns (AS-A6), and the boundary conditions by eqns (A7-A13). dz
~,(z,-h,)~+L(z,-h~)~
dz,
zr
_=-
(z,-1)Y
tI
w = ln(z,)
(A5) (A6)
(1974).
y=e,-1=1-e,
14. M. S. Liang and C. Hu, ZEDM Tech. Dig., 396 (1981). 15. A. Modelli and B. Ricco, ZEDM Tech. Dig., 148 (1984). 16. I. C. Chen, S. Holland and C. Hu, Proc. Znt. Rel. Phys. Symp., 24 (1985). 17. R. Ellis, H. A. R. Wegener and J. M. Caywood, ZEDM Tech. Dig., 749 (1982). 18. E. Harari. J. Aool. Phvs. 49. 2478 (1978). 19. D. J. DiMaria ‘and D: R. Kerr, Adpl. ihys. Lett. 27, 505 (1975). 20. R. Ellis, IEEE Electron Deoices Lett. EDW, 330 (1982). 21. H. A. R. Wegener, ZEDM Tech. Dig., 480 (1984). 22. R. Jolly et al., IEEE Trans. Electron. Devices ED-31,
(A7)
O
1>0
(A8)
@2/t,1
c’= -n(l+l) hi+I.hhq=
-;
I
(Al’3
767 (1984). 23. C-F. Chen and C-Y. Wu, Solid-St. Electron. 29, 1059 (1986).
24. C-F. Chen and C-Y. Wu, J. Appl. Phys. 60, 3926
-r2
+
i(t, - t,) cl t,
(1986).
25. R. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd edn (1986). 26. J. J. Van der Schoot and D. R. Wolters, Ins. Films Sem. INFOS 1983, 270 (1983). 27. L. Faraone, R. D. Vibronek and J. T. McGinn, IEEE Trans. Electron Devices ED-32, 577 (1985). 28. R. V. Churchill, Complex Variables and Applications, 3rd edn. (1976).
APPENDIX The complex transformation method is described in [28].As shown in Fig. 3, the cell geometry is described in the physical domain (z-plane) where I = x + iy = (x, y). This domain is SSE W-F
We used y = 0.5 in our analysis, which is equivalent to a sharp step over the transition regions. The curvature of the gate edge can be varied by the transformation parameters h,, h,, 1, of which only two can be chosen independently with the third defined by the cell geometry. In this analysis, we choose 1 and h, with h, derived from above equations. For a given I, h, is restricted by: (Al3)