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Simulation of transients in VLSI packaging interconnections
World Abstracts on Microelectronics and Reliability 6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , Design for manufacturability and yield. ANDRZE! J. STROJWAS. Microelectron. J. 21(2), 53 (1990). This paper focuses on the design strategies for VLSI circuits that are aimed at achieving manufacturable, high-yielding chips. The current status of statistical design methodologies is reviewed based upon statistically valid modeling and process characterization approaches. Both parametric and functional yield maximization strategies are covered. This paper argues that by providing a better starting point for manufacturing, the profitability and competitiveness can be significantly improved.
The use and evaluation of yield models in integrated circuit manufacturing. JAMESA. CUNNINGHAM.IEEE Trans. Semicond. Mfg 3(2), 60 (1990). The development and refinement of net-die-per-wafer yield models during the past 25 years or so are reviewed, and the models are tested for accuracy by comparison with actual yield data from seven separate chip companies. Depending on chip size, the more accurate models are the Poisson and the negative binomial. Several models for line yields in wafer fab are also covered. For predicting yields of larger die area very large scale integrations (VLSIs), the negative binomial model is the more accurate, but its use may require experimental determination of alpha, sometimes called the cluster parameter, versus chip area for the particular process and factory environment of interest. How an Insystems holographic wafer inspection machine can aid this process is described. Financial payback calculations for cleaner processing machines, and experience curve effects on yields are also discussed.
A cluster-modified Poisson model for estimating defect density and yield. ALBERT V. FERRIS-PRABHU.IEEE Trans. Semicond. Mfg 3(2), 54 (1990). A simple modification of the Poisson model is described that accounts for defect clustering when estimating the defect density and yield of a future product, in a manner that preserves the simplicity and computational convenience of the Poisson model, and provides more realistic estimates than does the unmodified Poisson model.
Very thin oxides in VLSI technology: properties and device implications. B. MAJKUSIAKand A. JAKUBOWSKI.Microelectron. J. 21(2), 21 (1990). The trend existing in MOS VLSI technology to reduce the oxide thickness is discussed. The basic reasons for the trend, further implications concerning the physical properties of the oxide layer and the performance of the MOS devices, as well as physical limitations, are considered.
EPAS: an emitter piloting advisory expert system for IC emitter deposition. YING-KUEI YANG. IEEE Trans. Semicond. Mfg 3(2), 45 (1990). Emitter piloting is a difficult diffusion process in IC manufacturing. The decision for the adjustment of piloting drive cycle is a very heuristic-oriented task. An expert system, emitter piloting advisory system (EPAS), is used at Harris Semiconductor to advise fab operators on how to adjust piloting cycle time for emitters based upon knowledge extracted from the most experienced engineer. EPAS consists of an input filter to validate the input parameter values, a knowledge base containing the knowledge extracted from the domain expert; a limited learning mechanism trying to calculate dynamically a better MR 31/I--N
SYSTEMS
AND
209 EQUIPMENT
estimate of initial drive time for the next lot; a convergence control mechanism to control the rule inference so that the result of an inference is always closer to the conclusion; a user facility module containing many LISP-based modules developed to let the expert engineers, and operators maintain the system by themselves; and a friendly interface to provide pleasant interactions with various kinds of users.
Fault-simulation programs for integrated-circuit yield estimations. C. H. STAPPER. I B M J. Res. Develop. 33(6) 647 (1989). Three programs are described here which have been used for integrated-circuit yield modeling at the IBM facility in Essex Junction, Vermont. The first program generates negative binomial distributions which are used to represent the frequency distribution of the number of faults per chip. Calculations with the generalized combination function A! B in APL are limited to simulations of up to 99,999 faults, and can take too much computer time to run. These limitations are eliminated when the calculations make use of the scan function. The second program simulates clustered fault locations on a map. The clusters are initially generated using a radial Gaussian probability distribution. Each fault location is stored as a complex number, which facilitates the use of cluster-shaping programs that are also described. In a third program, another simulator of fault maps, faults are added as a function of time. This program also results in fault distributions that are clustered. In addition, it produces frequency distributions that very closely approximate negative binomial distributions.
Evaluation of polyimides as dielectric materials for multichip packages with multilevel interconnection structure. A. W. LIN. IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 207 (1990). Using a Temperature-Humidity-Bias (THB) screening test, nine commercial polyimides were evaluated for applications of multichip packages with a multilevel interconnection structure. Among these polyimides, DuPont PI2555 performed best under the test conditions, i.e. 85°C/85%RH (relative humidity)/t80-V dc bias over 3-mil spacing. However, a slow increase of leakage current was observed in situ on the TiPdAu triple-track test samples coated with PI2555. This THB performance was improved by modifying PI2555 with a proprietary additive. However, the thermal stability of PI2555 was degraded by the additive. The dielectric constant of the modified P12555 was determined as 3.4 at 1 kHz similar to that of PI2555.
Simulation of transients in VLSI packaging interconnections. OLGIERD A. PALUSINSKI,J. C. LIAO, JOHN L. PRINCE and ANDREASC. CANGELLARIS.IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 160 (1990). An approach to electrical analysis of VLSI packaging interconnections via computer simulation is presented. Corresponding simulation software developed during the course of research on VLSI interconnections conducted at the University of Arizona is also described. Examples of application to prototypical interconnections (two transmission line systems joined by a lumped parameter network and a transmission line terminated by a network of bipolar and MOS transistors) are provided. The results of simulation of the above examples are presented and analyzed. Discussion of current status of work is also included and directions of future research delineated.
The use and evaluation of yield models in integrated circuit manufacturing. JAMESA. CUNNINGHAM.IEEE Trans. Semicond. Mfg 3(2), 60 (1990). The development and refinement of net-die-per-wafer yield models during the past 25 years or so are reviewed, and the models are tested for accuracy by comparison with actual yield data from seven separate chip companies. Depending on chip size, the more accurate models are the Poisson and the negative binomial. Several models for line yields in wafer fab are also covered. For predicting yields of larger die area very large scale integrations (VLSIs), the negative binomial model is the more accurate, but its use may require experimental determination of alpha, sometimes called the cluster parameter, versus chip area for the particular process and factory environment of interest. How an Insystems holographic wafer inspection machine can aid this process is described. Financial payback calculations for cleaner processing machines, and experience curve effects on yields are also discussed.
A cluster-modified Poisson model for estimating defect density and yield. ALBERT V. FERRIS-PRABHU.IEEE Trans. Semicond. Mfg 3(2), 54 (1990). A simple modification of the Poisson model is described that accounts for defect clustering when estimating the defect density and yield of a future product, in a manner that preserves the simplicity and computational convenience of the Poisson model, and provides more realistic estimates than does the unmodified Poisson model.
Very thin oxides in VLSI technology: properties and device implications. B. MAJKUSIAKand A. JAKUBOWSKI.Microelectron. J. 21(2), 21 (1990). The trend existing in MOS VLSI technology to reduce the oxide thickness is discussed. The basic reasons for the trend, further implications concerning the physical properties of the oxide layer and the performance of the MOS devices, as well as physical limitations, are considered.
EPAS: an emitter piloting advisory expert system for IC emitter deposition. YING-KUEI YANG. IEEE Trans. Semicond. Mfg 3(2), 45 (1990). Emitter piloting is a difficult diffusion process in IC manufacturing. The decision for the adjustment of piloting drive cycle is a very heuristic-oriented task. An expert system, emitter piloting advisory system (EPAS), is used at Harris Semiconductor to advise fab operators on how to adjust piloting cycle time for emitters based upon knowledge extracted from the most experienced engineer. EPAS consists of an input filter to validate the input parameter values, a knowledge base containing the knowledge extracted from the domain expert; a limited learning mechanism trying to calculate dynamically a better MR 31/I--N
SYSTEMS
AND
209 EQUIPMENT
estimate of initial drive time for the next lot; a convergence control mechanism to control the rule inference so that the result of an inference is always closer to the conclusion; a user facility module containing many LISP-based modules developed to let the expert engineers, and operators maintain the system by themselves; and a friendly interface to provide pleasant interactions with various kinds of users.
Fault-simulation programs for integrated-circuit yield estimations. C. H. STAPPER. I B M J. Res. Develop. 33(6) 647 (1989). Three programs are described here which have been used for integrated-circuit yield modeling at the IBM facility in Essex Junction, Vermont. The first program generates negative binomial distributions which are used to represent the frequency distribution of the number of faults per chip. Calculations with the generalized combination function A! B in APL are limited to simulations of up to 99,999 faults, and can take too much computer time to run. These limitations are eliminated when the calculations make use of the scan function. The second program simulates clustered fault locations on a map. The clusters are initially generated using a radial Gaussian probability distribution. Each fault location is stored as a complex number, which facilitates the use of cluster-shaping programs that are also described. In a third program, another simulator of fault maps, faults are added as a function of time. This program also results in fault distributions that are clustered. In addition, it produces frequency distributions that very closely approximate negative binomial distributions.
Evaluation of polyimides as dielectric materials for multichip packages with multilevel interconnection structure. A. W. LIN. IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 207 (1990). Using a Temperature-Humidity-Bias (THB) screening test, nine commercial polyimides were evaluated for applications of multichip packages with a multilevel interconnection structure. Among these polyimides, DuPont PI2555 performed best under the test conditions, i.e. 85°C/85%RH (relative humidity)/t80-V dc bias over 3-mil spacing. However, a slow increase of leakage current was observed in situ on the TiPdAu triple-track test samples coated with PI2555. This THB performance was improved by modifying PI2555 with a proprietary additive. However, the thermal stability of PI2555 was degraded by the additive. The dielectric constant of the modified P12555 was determined as 3.4 at 1 kHz similar to that of PI2555.
Simulation of transients in VLSI packaging interconnections. OLGIERD A. PALUSINSKI,J. C. LIAO, JOHN L. PRINCE and ANDREASC. CANGELLARIS.IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 160 (1990). An approach to electrical analysis of VLSI packaging interconnections via computer simulation is presented. Corresponding simulation software developed during the course of research on VLSI interconnections conducted at the University of Arizona is also described. Examples of application to prototypical interconnections (two transmission line systems joined by a lumped parameter network and a transmission line terminated by a network of bipolar and MOS transistors) are provided. The results of simulation of the above examples are presented and analyzed. Discussion of current status of work is also included and directions of future research delineated.