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Simulation study of the 20 nm gate-length Ge implant-free quantum well p-MOSFET
Microelectronic Engineering 88 (2011) 362–365
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Simulation study of the 20 nm gate-length Ge implant-free quantum well p-MOSFET K.H. Chan ⇑, B. Benbakhti, C. Riddet, J.R. Watling, A. Asenov Device Modelling Group, School of Engineering, University of Glasgow, G12 8LT, UK
a r t i c l e
i n f o
Article history: Available online 16 October 2010 Keywords: Germanium p-MOSFET Interface state trap density Hole Parasitic gate capacitance Mobility
a b s t r a c t In this paper a drift diffusion simulation study of a 20 nm gate-length implant-free quantum well germanium p-MOSFET is presented, which covers the impact of mobility, velocity saturation and density of interface states on the transistor performance. The parasitic gate capacitance was also studied. The simulations show that the 20 nm gate-length implant-free quantum-well transistor design has good electrostatic integrity and performance potential. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction
2. Simulation methodology and device design
In recent years there has been a strong interest in incorporating germanium (Ge) into p-MOSFET designs in order to improve channel mobility and transistor performance [1–3]. Ge channels offer the benefits of lower effective mass, higher mobility and higher injection velocity compared to silicon (Si). Here we study an implant-free quantum well (IF-QW) Ge p-channel MOSFET, which offers advantages in terms of simplified technology, in-situ doped source and drain, and improved electrostatic integrity in terms of a steeper subthreshold slope (SS). The use of overgrown source and drain regions doped during the epitaxial overgrowth eliminates the need for implantation and high temperature activation [4]. The thickness of the lateral gate spacer is critical to the electrostatic behaviour of the IF-QW transistors and their performance. After a careful scaling study conducted previously [5], which we have migrated into this design, the impact of the inversion layer mobility and the saturation velocity on transistor performance has been investigated. The impact of the relatively high interface state density, due to immature gate technology, on the subthreshold slope has also been studied. Fringing capacitances associated with the overgrown source/drain regions and the relatively thin gate spacers have also been examined. The mobility in the Ge channel was deduced from comprehensive Monte Carlo simulations taking into account the impact of strain and channel orientation on mobility [7] as well as available experimental data [1].
The IF-QW device was simulated using the Sentaurus TCAD simulator [6] incorporating Fermi–Dirac statistics, along with doping- and field-dependent mobility models. The structure of the IFQW transistor is illustrated in Fig. 1. The heavily p-doped source and drain overgrown regions sit on top of a lowly n-doped (to the magnitude of 1017 cm3) 5 nm thick channel. The Al2O3 (er = 11.5) gate oxide corresponds to an EOT of 0.8 nm. 5 nm-wide silicon nitride spacers separate the gate from the source/drain regions. Velocity overshoot plays an important role in determining the performance of such nano-scaled devices [8,9]. In the drift–diffusion simulations used in this paper we model the impact of velocity overshoot and the injection velocity at the virtual source, t = lE is modelled by appropriate adjustments of the saturation velocity in the field dependent mobility model. The Caughey–Thomas model [10] has been used in this study:
⇑ Corresponding author. E-mail addresses: [email protected], [email protected] (K.H. Chan). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.09.025
lðEÞ ¼ lmin þ
llow
E 1 þ ltlow Sat
b 1=b
ð1Þ
Here b is an adjustable temperature-dependent parameter, E is the field and the value of the saturation velocity was varied in order to evaluate the impact of the different magnitudes of injection velocity on the drain current at different values of channel mobility attainable in Ge. The impact of the interface trap density on the transistor performance was modelled using the technology described in [5] with the interface states distribution deduced from experimental data [11], a Si/SiO2 passivation layer at the oxide/semiconductor interface was also included in these simulations. The intrinsic and
K.H. Chan et al. / Microelectronic Engineering 88 (2011) 362–365
363
Fig. 1. 20 nm Ge IF-QW p-MOSFET.
extrinsic capacitances associated with the gate spacers are extracted from small signal capacitance simulations.
3. Mobility versus saturation velocity Constant low-field mobility is used in conjunction with the high-field Caughey–Thomas mobility model, which accounts for the velocity saturation effects. The low-field mobility values examined in these simulations were 50, 100, 200, and 400 cm2/V s. For each of the simulated low-field mobility values the saturation velocity was varied in the range of 0.6–3.0 107 cm/s. This covers the expected range of mobilities and injection velocities in Ge pchannel transistors for different levels of technological maturity. The simulation results are presented in Fig. 2. The results show that it is possible to achieve a high drain current of approximately 1000 lA/lm for a low-field mobility of 400 cm2/Vs. Such levels of low-field mobility are achievable within the mature Si-compatible process technology [1]. For such high performance a peak injection velocity of 3.0 107 cm/s is required. With the introduction of strain and use of a favourable substrate orientation, higher mobilities may be achieved [7] resulting in further ION improvements.
4. Impact of interface trap density Reducing the interface trap density, Dit, improves the SS and increases the effective mobility. While research in developing an optimum passivation process has been a continuing effort, guarantying a low density of active interface traps for Ge technology is underway; here we investigate the impact of the currently achievable density of states on the IF-QW device performance. The use of an ultra-thin Si-cap layer has so far gained popularity due to the familiar process inherited from Si technology [12]. This technology has been examined here, where Dit as a function of the energy within the bandgap has been extracted using the full conductance method as outlined by Martens et al. [11] and is shown as an inset in Fig. 3 for a 4 nm HfO2 gate dielectric and Si cap layer (EOT = 1.3 nm). The impact of the interface trap density is illustrated in Fig. 3 in comparison with a transistor without interface traps. A small change in the SS as a result of the interface states is observed. The small effect is due to the small EOT of the gate oxide and illustrates that the interface state density is of less concern in aggressively scaled transistors in respect of SS. However the charge trapping on the interface states may still result in significant statistical variability and this effect has to be examined carefully in the future.
Fig. 2. Id–Vg results for different saturation velocity at mobility (a) 50 cm2/V s (b) 100 cm2/V s (c) 200 cm2/V s (d) 400 cm2/V s at low (50 mV) and high (1 V) drain bias.
5. Parasitic gate capacitance In IF-QW transistors spacers are essential in order to reduce capacitive coupling, but must be thin to minimise the access resistance between the overgrown source/drain regions and the channel to secure sufficiently high drive current. A spacer width of 5 nm, equal to 1=4 of the device gate length was employed, as this ratio has been previously employed in the design of IF-QW III–V MOSFETs [5]. It is important to estimate the impact of the thin
364
K.H. Chan et al. / Microelectronic Engineering 88 (2011) 362–365
Fig. 3. Id–Vg at low (50 mV) and high (1 V) drain bias with and without Dit obtained using an experimentally extracted energy distribution, as shown in the inset.
Fig. 5. Id–Vg characteristic at low (50 mV) and high (1 V) drain bias on the design of spacer with angle 30°, 60° and 90°.
spacer on the gate capacitance in comparison with conventional Si transistors. The gate capacitance is generally defined as
C total ¼ C int þ C ext
ð2Þ
where Cint and Cext are the intrinsic and extrinsic capacitance, respectively. To reduce the magnitude of the extrinsic capacitance different designs of the overgrowth regions have been considered. The total capacitance (intrinsic and extrinsic) of different gatelengths 20 nm, 100 nm and 200 nm with different spacer angles (30°, 60°, 90°) as illustrated schematically in Fig. 4a, was simulated at a single frequency 1 106 Hz at each DC bias during the sweep of Vg performed in an AC simulation analysis. Results for 100 nm and 200 nm were used to calculate and cross-check the accuracy of the result for 20 nm, although not shown here. Fig. 4b shows that the total capacitance increases and saturates when Vg sweeps from 0 V through to 2.5 V. The device demonstrates a total capacitance that is compatible to a state-of-the art 18 nm Si p-MOSFET counterpart that may impose a bulk parasitic capacitance of 1.1 106 nF/ lm [13]. At 90° where the distance between the gate contact and the drain contact is smallest the fringing capacitance is at its highest value. Fig. 4c and d demonstrate that the extrinsic capacitance is the main factor that contributes to the change of the total capacitance. In order to reduce the fringing capacitance a 60° overgrowth angle is recommended because it has less effect on the drain current in the Id–Vg characteristic as shown in the Fig. 5. 6. Conclusions The IF-QW p-channel Ge device studied here possesses excellent electrostatic integrity and is promising for high performance design. The use of a small EOT makes the device resistant to the interface trap densities within the bandgap and the extrinsic capacitances can be minimised by the tapered overgrowth of the epitaxial source and drain regions. Acknowledgements The authors acknowledge the financial support of EPSRC Grant EP/F032633/1 and the FP7 project DUALLOGIC. References
Fig. 4. (a) The design of spacer with angle 30°, 60° and 90°, results of (b) total capacitance, (c) extrinsic capacitance and (d) intrinsic capacitance from simulations based on 3 different spacer angles.
[1] G. Eneman et al., Thin Solid Films 518 (6) (2010) S88–S91. [2] G. Eneman et al., IEEE Transactions on Electron Devices 55 (9) (2008) 2287– 2296. [3] D.P. Brunco et al., Journal of the Electrochemical Society 155 (2008) H552. [4] H. Zhu, H. Zhong, T. Kawamura, Q. Liang, E. Leobandung, S. Huang, Electron Device Letters IEEE 28 (2) (2007) 168–170. [5] B. Benbakhti, J. Ayubi-Moak, K. Karol, A. Asenov, Journal of Physics: Conference Series 193 (2009) 012122.
K.H. Chan et al. / Microelectronic Engineering 88 (2011) 362–365 [6] C. Riddet, J.R. Watling, K.H. Chan, A. Asenov, II Workshop on Theory, Modelling and Computational Methods for Semiconductor Materials and Nanostructures (2010) 17. [7] Sentaurus device, A-2008.09, Sypnosys Inc. [8] Lixin Ge, J. Fossum, Bin Liu, IEEE Transactions on Electron Devices 48 (9) (2001) 2074–2080. [9] G.C. Crow, R.A. Abram, Semiconductor Science and Technology 15 (2000) 7–14. [10] D. Caughey, R. Thomas, Proceedings of the IEEE 55 (12) (1967) 2192–2193.
365
[11] K. Martens et al., Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs, in: Solid-State Device Research Conference, 2008, ESSDERC, 38th European, 2008, pp. 138–141. [12] P. Zimmerman et al., High performance Ge pMOS devices using a Sicompatible process flow, in: Electron Devices Meeting, IEDM’06, International, 2006, pp. 1–4. [13] X. Wang, Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs, Ph.D. Thesis, Glasgow Uni, 2010.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Simulation study of the 20 nm gate-length Ge implant-free quantum well p-MOSFET K.H. Chan ⇑, B. Benbakhti, C. Riddet, J.R. Watling, A. Asenov Device Modelling Group, School of Engineering, University of Glasgow, G12 8LT, UK
a r t i c l e
i n f o
Article history: Available online 16 October 2010 Keywords: Germanium p-MOSFET Interface state trap density Hole Parasitic gate capacitance Mobility
a b s t r a c t In this paper a drift diffusion simulation study of a 20 nm gate-length implant-free quantum well germanium p-MOSFET is presented, which covers the impact of mobility, velocity saturation and density of interface states on the transistor performance. The parasitic gate capacitance was also studied. The simulations show that the 20 nm gate-length implant-free quantum-well transistor design has good electrostatic integrity and performance potential. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction
2. Simulation methodology and device design
In recent years there has been a strong interest in incorporating germanium (Ge) into p-MOSFET designs in order to improve channel mobility and transistor performance [1–3]. Ge channels offer the benefits of lower effective mass, higher mobility and higher injection velocity compared to silicon (Si). Here we study an implant-free quantum well (IF-QW) Ge p-channel MOSFET, which offers advantages in terms of simplified technology, in-situ doped source and drain, and improved electrostatic integrity in terms of a steeper subthreshold slope (SS). The use of overgrown source and drain regions doped during the epitaxial overgrowth eliminates the need for implantation and high temperature activation [4]. The thickness of the lateral gate spacer is critical to the electrostatic behaviour of the IF-QW transistors and their performance. After a careful scaling study conducted previously [5], which we have migrated into this design, the impact of the inversion layer mobility and the saturation velocity on transistor performance has been investigated. The impact of the relatively high interface state density, due to immature gate technology, on the subthreshold slope has also been studied. Fringing capacitances associated with the overgrown source/drain regions and the relatively thin gate spacers have also been examined. The mobility in the Ge channel was deduced from comprehensive Monte Carlo simulations taking into account the impact of strain and channel orientation on mobility [7] as well as available experimental data [1].
The IF-QW device was simulated using the Sentaurus TCAD simulator [6] incorporating Fermi–Dirac statistics, along with doping- and field-dependent mobility models. The structure of the IFQW transistor is illustrated in Fig. 1. The heavily p-doped source and drain overgrown regions sit on top of a lowly n-doped (to the magnitude of 1017 cm3) 5 nm thick channel. The Al2O3 (er = 11.5) gate oxide corresponds to an EOT of 0.8 nm. 5 nm-wide silicon nitride spacers separate the gate from the source/drain regions. Velocity overshoot plays an important role in determining the performance of such nano-scaled devices [8,9]. In the drift–diffusion simulations used in this paper we model the impact of velocity overshoot and the injection velocity at the virtual source, t = lE is modelled by appropriate adjustments of the saturation velocity in the field dependent mobility model. The Caughey–Thomas model [10] has been used in this study:
⇑ Corresponding author. E-mail addresses: [email protected], [email protected] (K.H. Chan). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.09.025
lðEÞ ¼ lmin þ
llow
E 1 þ ltlow Sat
b 1=b
ð1Þ
Here b is an adjustable temperature-dependent parameter, E is the field and the value of the saturation velocity was varied in order to evaluate the impact of the different magnitudes of injection velocity on the drain current at different values of channel mobility attainable in Ge. The impact of the interface trap density on the transistor performance was modelled using the technology described in [5] with the interface states distribution deduced from experimental data [11], a Si/SiO2 passivation layer at the oxide/semiconductor interface was also included in these simulations. The intrinsic and
K.H. Chan et al. / Microelectronic Engineering 88 (2011) 362–365
363
Fig. 1. 20 nm Ge IF-QW p-MOSFET.
extrinsic capacitances associated with the gate spacers are extracted from small signal capacitance simulations.
3. Mobility versus saturation velocity Constant low-field mobility is used in conjunction with the high-field Caughey–Thomas mobility model, which accounts for the velocity saturation effects. The low-field mobility values examined in these simulations were 50, 100, 200, and 400 cm2/V s. For each of the simulated low-field mobility values the saturation velocity was varied in the range of 0.6–3.0 107 cm/s. This covers the expected range of mobilities and injection velocities in Ge pchannel transistors for different levels of technological maturity. The simulation results are presented in Fig. 2. The results show that it is possible to achieve a high drain current of approximately 1000 lA/lm for a low-field mobility of 400 cm2/Vs. Such levels of low-field mobility are achievable within the mature Si-compatible process technology [1]. For such high performance a peak injection velocity of 3.0 107 cm/s is required. With the introduction of strain and use of a favourable substrate orientation, higher mobilities may be achieved [7] resulting in further ION improvements.
4. Impact of interface trap density Reducing the interface trap density, Dit, improves the SS and increases the effective mobility. While research in developing an optimum passivation process has been a continuing effort, guarantying a low density of active interface traps for Ge technology is underway; here we investigate the impact of the currently achievable density of states on the IF-QW device performance. The use of an ultra-thin Si-cap layer has so far gained popularity due to the familiar process inherited from Si technology [12]. This technology has been examined here, where Dit as a function of the energy within the bandgap has been extracted using the full conductance method as outlined by Martens et al. [11] and is shown as an inset in Fig. 3 for a 4 nm HfO2 gate dielectric and Si cap layer (EOT = 1.3 nm). The impact of the interface trap density is illustrated in Fig. 3 in comparison with a transistor without interface traps. A small change in the SS as a result of the interface states is observed. The small effect is due to the small EOT of the gate oxide and illustrates that the interface state density is of less concern in aggressively scaled transistors in respect of SS. However the charge trapping on the interface states may still result in significant statistical variability and this effect has to be examined carefully in the future.
Fig. 2. Id–Vg results for different saturation velocity at mobility (a) 50 cm2/V s (b) 100 cm2/V s (c) 200 cm2/V s (d) 400 cm2/V s at low (50 mV) and high (1 V) drain bias.
5. Parasitic gate capacitance In IF-QW transistors spacers are essential in order to reduce capacitive coupling, but must be thin to minimise the access resistance between the overgrown source/drain regions and the channel to secure sufficiently high drive current. A spacer width of 5 nm, equal to 1=4 of the device gate length was employed, as this ratio has been previously employed in the design of IF-QW III–V MOSFETs [5]. It is important to estimate the impact of the thin
364
K.H. Chan et al. / Microelectronic Engineering 88 (2011) 362–365
Fig. 3. Id–Vg at low (50 mV) and high (1 V) drain bias with and without Dit obtained using an experimentally extracted energy distribution, as shown in the inset.
Fig. 5. Id–Vg characteristic at low (50 mV) and high (1 V) drain bias on the design of spacer with angle 30°, 60° and 90°.
spacer on the gate capacitance in comparison with conventional Si transistors. The gate capacitance is generally defined as
C total ¼ C int þ C ext
ð2Þ
where Cint and Cext are the intrinsic and extrinsic capacitance, respectively. To reduce the magnitude of the extrinsic capacitance different designs of the overgrowth regions have been considered. The total capacitance (intrinsic and extrinsic) of different gatelengths 20 nm, 100 nm and 200 nm with different spacer angles (30°, 60°, 90°) as illustrated schematically in Fig. 4a, was simulated at a single frequency 1 106 Hz at each DC bias during the sweep of Vg performed in an AC simulation analysis. Results for 100 nm and 200 nm were used to calculate and cross-check the accuracy of the result for 20 nm, although not shown here. Fig. 4b shows that the total capacitance increases and saturates when Vg sweeps from 0 V through to 2.5 V. The device demonstrates a total capacitance that is compatible to a state-of-the art 18 nm Si p-MOSFET counterpart that may impose a bulk parasitic capacitance of 1.1 106 nF/ lm [13]. At 90° where the distance between the gate contact and the drain contact is smallest the fringing capacitance is at its highest value. Fig. 4c and d demonstrate that the extrinsic capacitance is the main factor that contributes to the change of the total capacitance. In order to reduce the fringing capacitance a 60° overgrowth angle is recommended because it has less effect on the drain current in the Id–Vg characteristic as shown in the Fig. 5. 6. Conclusions The IF-QW p-channel Ge device studied here possesses excellent electrostatic integrity and is promising for high performance design. The use of a small EOT makes the device resistant to the interface trap densities within the bandgap and the extrinsic capacitances can be minimised by the tapered overgrowth of the epitaxial source and drain regions. Acknowledgements The authors acknowledge the financial support of EPSRC Grant EP/F032633/1 and the FP7 project DUALLOGIC. References
Fig. 4. (a) The design of spacer with angle 30°, 60° and 90°, results of (b) total capacitance, (c) extrinsic capacitance and (d) intrinsic capacitance from simulations based on 3 different spacer angles.
[1] G. Eneman et al., Thin Solid Films 518 (6) (2010) S88–S91. [2] G. Eneman et al., IEEE Transactions on Electron Devices 55 (9) (2008) 2287– 2296. [3] D.P. Brunco et al., Journal of the Electrochemical Society 155 (2008) H552. [4] H. Zhu, H. Zhong, T. Kawamura, Q. Liang, E. Leobandung, S. Huang, Electron Device Letters IEEE 28 (2) (2007) 168–170. [5] B. Benbakhti, J. Ayubi-Moak, K. Karol, A. Asenov, Journal of Physics: Conference Series 193 (2009) 012122.
K.H. Chan et al. / Microelectronic Engineering 88 (2011) 362–365 [6] C. Riddet, J.R. Watling, K.H. Chan, A. Asenov, II Workshop on Theory, Modelling and Computational Methods for Semiconductor Materials and Nanostructures (2010) 17. [7] Sentaurus device, A-2008.09, Sypnosys Inc. [8] Lixin Ge, J. Fossum, Bin Liu, IEEE Transactions on Electron Devices 48 (9) (2001) 2074–2080. [9] G.C. Crow, R.A. Abram, Semiconductor Science and Technology 15 (2000) 7–14. [10] D. Caughey, R. Thomas, Proceedings of the IEEE 55 (12) (1967) 2192–2193.
365
[11] K. Martens et al., Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs, in: Solid-State Device Research Conference, 2008, ESSDERC, 38th European, 2008, pp. 138–141. [12] P. Zimmerman et al., High performance Ge pMOS devices using a Sicompatible process flow, in: Electron Devices Meeting, IEDM’06, International, 2006, pp. 1–4. [13] X. Wang, Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs, Ph.D. Thesis, Glasgow Uni, 2010.