Simultaneous switching noise reduction by resonant clock distribution networks

INTEGRATION, the VLSI journal 47 (2014) 242–249

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INTEGRATION, the VLSI journal journal homepage: www.elsevier.com/locate/vlsi

Simultaneous switching noise reduction by resonant clock distribution networks Behzad Mesgarzadeh n Linköping University, 58183 Linköping, Sweden

art ic l e i nf o

a b s t r a c t

Article history: Received 14 January 2013 Received in revised form 7 October 2013 Accepted 8 October 2013 Available online 17 October 2013

Resonant clock distribution networks are known as low-power alternatives for conventional powerhungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically. & 2013 Elsevier B.V. All rights reserved.

Keywords: EMI Resonant clock distribution Simultaneous switching noise (SSN) Sine-wave clock

1. Introduction The trend of increasing complexity, speed and density in today's very large scale integrated (VLSI) circuits, due to aggressive technology scaling, introduces new challenges in design and fabrication process. As an example, in today's microprocessors with millions of transistors, a conventional buffer-driven clock tree is typically utilized to synchronize all the elements connected to the leaves. Due to employing high clock frequencies, fast and sharp clock edges are applied to the clocked devices. In such a synchronization scheme, these sharp clock edges occur at the same time creating large current pulses in the power distribution network (PDN). These large and fast current variations flow through on-chip parasitic inductance inherent to the power rails and also off-chip bonding wires resulting in unwanted voltage fluctuations (L Udi=dt) which is known as simultaneous switching noise (SSN). The generated SSN can create serious problems in signal/power integrity [1]. Furthermore, it is considered as one of the important sources of on-chip electromagnetic interference (EMI) [2–5]. Nowadays, since in many applications electronic circuits are playing a crucial role, electromagnetic compatibility (EMC) issue becomes a serious liming factor. Many techniques have been proposed to suppress SSN in a clocking network. Using multiple bonding wires in order to reduce the total inductance to decrease the value of L U di=dt is one way to reduce the SSN. In this technique, we need to consider the relative

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placement of pins carefully, as the absolute value of the inductance is not the only important factor [6]. In [7], a method to determine the optimum number of pins is presented. Furthermore, advance packaging methods can be used to reduce the inductance value [8,9]. However, these methods increase the total packaging costs. In order to suppress SSN, another method is to distribute clock edges within a specific timeslot, as long as it is allowed by timing constraints [10]. This helps to prevent simultaneous occurrence of clock edges. However, this technique is not directly supported by CAD tools and also proper clock drivers need to be utilized in order to employ this method. Another effective technique to suppress SSN is to insert on-chip and off-chip decoupling capacitors (i.e., decaps) [11]. Effectiveness of this technique has been studied and analyzed in [12]. Although decoupling capacitors exhibit capability of SSN suppression, they are not area efficient. Due to this fact, careful optimization is required to choose the proper capacitance size to avoid extreme area penalties. As mentioned earlier, fast clock edges increase the switching noise by increasing di=dt. Hence, one low-cost solution to reduce SSN is to employ a signal with relaxed rise and fall time (i.e., slower edges) [13–15]. Obviously, this technique creates some difficulties in management of timing budget for high-speed applications. However, in [14] and [15], about 40–60% noise reduction has been reported by accepting some speed penalty. In this paper, we investigate a new SSN reduction technique based on resonant clock distribution, which has been previously proposed as a low-power alternative for the conventional bufferdriven clocking [16–19]. In this clocking strategy, since a sinusoidal clock is generated for the clock distribution purpose, the peak

B. Mesgarzadeh / INTEGRATION, the VLSI journal 47 (2014) 242–249

energy of higher harmonic components is suppressed significantly, resulting in smoother transitions. An analysis is presented in this work in order to show the great capability of resonant clocking in SSN reduction. Furthermore, other issues associated with resonant clocking such as effect of harmonic distortion on SSN and shortcircuit power dissipation problem are investigated. The organization of this paper is as follows. In Section 2, the basics of resonant clocking are presented. Section 3 is dedicated to comparison of SSN in resonant clock distribution and conventional buffer-driven clocking. In Section 4, effect of harmonic distortion in resonant clocking on SSN is discussed. Then, the short-circuit power dissipation issue is investigated in Section 5 followed by results and comparison in Section 6 and conclusions in Section 7.

2. Basics of resonant clocking The clock distribution network in a VLSI circuit (e.g., a microprocessor) can be divided into global and local clock distributions [16]. The global network consists of the clock source and buffer stages which connect the clock source to the logic gates by wires and interconnects, while the local network consists of the final load and associated wires which connect them to the final buffer stage. Fig. 1(a) shows a simplified model of a conventional bufferdriven clock distribution network. The main idea behind a resonant clock distribution network is to use the clock capacitance to render oscillation using LC-based oscillators [16–19]. A simplified model of this clocking strategy is shown in Fig. 1(b). A resonant clock can be delivered globally to the leaf node clock buffers using

C

C

243

distributed oscillators [19], or alternatively, to gain the maximum power savings, it can even be distributed completely bufferless directly to the clocked elements [16–18]. In either of these methods, a sinusoidal clock is generated and delivered to devices, which are connected to clock network directly or through local buffers. In terms of clock power dissipation, it can be proven that P res 3πðn  1Þ ¼ 4nQ tank P conv

ð1Þ

where Pres and Pconv are the clock power dissipation in the resonant clocking and the conventional clocking, respectively, n is the tapering factor in the conventional clocking, and Qtank is the quality factor of the LC tank utilized for the clock generation in the resonant clock distribution network [16]. As a numerical example, for n ¼3, a tank quality factor higher than π would result in more than 50% clock power saving by using resonant clocking scheme. In the previous studies on the resonant clock distribution networks, the main focus were on clock power saving capability of this clocking strategy [16–19]. Hence, the application of a resonant clocking network has always been limited to highspeed processors in which the clock power dissipation is a considerable fraction of the total power dissipation. It has barely been considered for other potential applications where the power consumption is not the primary concern. Due to this reason, there have not been sufficient studies about other possible applications of resonant clocking networks. In [20], it has been shown that the total radiated EMI can be reduced significantly by utilizing this clocking strategy. In this paper, we move further to reconsider and demonstrate this technique for other new applications. We investigate the switching noise performance of a resonant clock distribution network and discuss different design issues and considerations. Furthermore, we present a comparison of shortcircuit power dissipation in resonant and conventional clocking, in order to get more insight about the trade-offs involved in employing this clocking strategy in the future applications.

3. SSN in resonant clocking Clock

3.1. Basic considerations

Clock

In power supply rails, the parasitics contributed by wires, interconnects, transistors, etc. form RLC circuits which are the source of undesired voltage fluctuations. To have a basic understanding about the phenomenon, let us consider the simple circuit shown in Fig. 2. In this figure, an AC current is injected through a current source into an ideal inductor. We investigate two different cases. For the first case, we assume that the injected current has a trapezoidal shape varying between 0 and A with identical rise and fall times (i.e., tr). The maximum di=dt occurs during the rising and falling edges creating a voltage change across the inductor which equals to

C

C

n

nm-1

nm

CL

CL

CL

nm

n2

n

CL

V L; max ¼ L

di AL j ¼ : dt max tr

ð2Þ

Sinusoidal Clock

+

Iin Iosc

RP

LP

CL

Iin

L

Iin Fig. 1. A simplified model of (a) a buffer-driven clock network, and (b) a resonant clock distribution network.

Fig. 2. An ideal inductor is fed by a current source.

VL _

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Now for the second case, we assume that the injected current into the inductor is a sinusoidal current with the same amplitude and frequency as those of the trapezoidal one. To get an amplitude between 0 and A, the sinusoidal current should be in the form of A=2 þ ðA=2Þ sin ðωtÞ. Then the maximum voltage drop across the inductor is V L; max ¼ L

di ALω ALπ j ¼ : ¼ dt max 2 T

ð3Þ

Comparing Eq. (2) and (3), we conclude that if tr is less than 32% of the clock period, then the maximum VL for a sinusoidal current is smaller than that of a trapezoidal one. This fact is the starting point to consider the sinusoidal clocking as a low SSN alternative for conventional buffer-driven clock distribution in which typically, very sharp clock edges are fed into the clocked elements and the rise and fall times are less than 10% of the clock period. However, in the clocked elements such as logic gates, flipflops, etc. the shape of the current waveform not necessarily follows the clock signal variations. Due to this fact, more accurate modeling is necessary to prove the concept, as it will be discussed in the coming subsections.

3.2. Single-inductor model Now, we consider a more generalized form in which an inverter is connected to supply rails by a single inductor, as it is shown in Fig. 3(a). This inductor models the on-chip parasitic inductance inherent to the power supply rails and the selfinductance of the off-chip bonding wires. The clock signal is applied as input to the inverter (Vin). Neglecting the effect of short-circuit currents, we can assume that PMOS is off during a low-to-high transition and we calculate the SSN on the ground rail by just considering the NMOS transistor as it is shown in Fig. 3(b). If we assume that the driving transistor is saturated when the peak noise occurs, the current through the transistor (M1) and the inductor is I M1 ¼ I L ¼ Kðvin  V tn  vn Þn

ð4Þ

where K is a process and size dependent constant, Vtn is the threshold voltage of the NMOS transistor, and 1 o n o 2 for short-channel devices and it approaches 1 with scaling. Neglecting the body effect, the derivative of Eq. (4) can be written as
 dI L dvin dvn ¼ Knðvin  V tn  vn Þn  1  : dt dt dt

ð5Þ

VDD

As mentioned earlier, n approaches 1 by scaling, thus we can rewrite (5) as
 dI L dvin dvn ¼ KF  ð6Þ dt dt dt where F can be considered as a constant close to 1. In Eq. (6), considering the fact that dI L =dt ¼ vn =LSS , we get dvn dv þ Bvn  in ¼ 0 dt dt

where B ¼ 1=KFLSS is a constant. Eq. (7) is a first order differential equation with respect to vn and it can be solved for different input signals. To do so, let us first consider a ramp input at t ¼ 0, (i.e., vin ¼ ðV DD =t r Þt). Since transistor is off for vin o V tn , we apply vn ðt 0 Þ ¼ 0 as an initial condition to solve Eq. (7) where t 0 ¼ t r V tn =V DD . Thus vn ðtÞ ¼

ð8Þ

vn ðtÞ ¼

V DD ðe  ðt  t 0 Þ=τ  e  Bðt  t 0 Þ Þ Bτ 1

ð9Þ

where t0 is the time in which vin passes the threshold voltage and transistor turns on. Similarly, based on Eq. (9) increasing the rise time (i.e., relaxed clock edges) results in lower noise voltage. We can plot Eq. (9) for different rise time values, as it is shown in Fig. 4. In this figure, the curves are shifted by t0 towards the origin. It is important to note that this plot shows the noise voltage for a rising edge. Assuming identical rise and fall time values, the peakto-peak SSN voltage is twice the peak values shown in this figure (considering the negative peaks as well). Here, we use a minimum size transistor which is connected to a 1-nH inductor and we employ the process parameters of a standard 65-nm CMOS technology which result in B ¼ 23  1012. With these assumptions, a notable point is that in Eq. (9), two different time constants are involved (i.e., τ and 1/B). Since for today's clock frequency ranges, the rise time is in the order of a few hundreds of picoseconds, then τ441/B. Hence, when transistor turns on (i.e., tooτ) the first exponential term in Eq. (9) is roughly 1 and the exponential 4

vin

M1

IM1

CL

vn

CL

IL

LSS

LSS

SSN Voltage (mV)

vout

VSSN,VSS

V DD ð1  e  Bðt  t 0 Þ Þ: Bt r

Eq. (8) gives the noise voltage for a rising edge of a ramp clock and it is valid for t 0 r t r t r . It is obvious from Eq. (8) that the noise voltage increases for sharp clock edges (i.e., when tr decreases). However, the assumption of a ramp clock signal is not in fact practical, since the clock buffers which distribute the clock signal (dis)charge a capacitive load with an exponential characteristic. Then it could be instructive to solve Eq. (7) for an exponential input signal by employing a similar initial condition. Consequently, we replace vin ¼ V DD ð1  e  t=τ Þ into Eq. (7) to calculate the noise voltage for a rising edge. To avoid uncertainties in start and end of the clock transition, we define the rise time as the time interval between 10% and 90% points of the clock waveform. Based on this definition, the rise time of abovementioned exponential clock is calculated to be 2.2τ. By utilizing a similar initial condition to solve Eq. (7), we get

LDD VSSN,VDD

vin

ð7Þ

tr=25 ps 3

tr=50 ps

2

tr =100 ps tr=200 ps

1

0 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Time (ps) Fig. 3. (a) SSN in a single inverter, and (b) SSN on the ground rail.

Fig. 4. SSN voltage for different clock edges.

0.9

1

B. Mesgarzadeh / INTEGRATION, the VLSI journal 47 (2014) 242–249

behavior is manifested by the second term. When time approaches τ, the second term approaches zero and the first term starts to pull the SSN voltage to zero. For this reason, the peak of SSN voltage occurs in less than 1 ps after the transistor turns on, as it is shown in Fig. 4. Obviously, increasing the size of the transistor (and also the inductor) increases 1/B, however, it could be instructive to reconsider Eq. (9) for τ441/B. In this case, the maximum of Eq. (9) can be approximated by
 V DD 1 vn; max ðtÞ  ð10Þ 1 Bτ Bτ

245

Vin

M1

IM1

CL

vn IL

LSS

CSS RSS

which occurs at time instance of t max 

Fig. 6. SSN model with lumped RLC network.

InBτ : B

ð11Þ

In order to compare the effect of resonant clocking on SSN with that of conventional clocking, now let us employ a rail-to-rail sinusoidal clock signal to solve Eq. (7). Considering vin ¼ 0:5V DD ð1  cos ωtÞ where ω is the clock frequency, and using a similar initial condition result in vn ðtÞ ¼

ωV DD 2ðB2 þ ω2 Þ

½B sin ðωðt  t 0 ÞÞ þωðe

 Bðt  t 0 Þ

In this case, using the previously mentioned definition, the rise time of the sinusoidal clock is calculated to be 0.3T, where T is the clock period. Employing identical process parameters as before for a minimum size transistor and a similar inductor value, we can plot Eq. (12) for different rise times, as shown in Fig. 5. Since for a sinusoidal clock the rise time depends on the clock frequency, different clock frequencies are applied in order to plot Fig. 5. In this figure, the noise contributions of both rising and falling edges are shown. As expected, increasing the clock frequency increases the SSN voltage, since the clock edges become sharper. By comparing Figs. 4 and 5, we can draw an important conclusion. The peak and peak-to-peak SSN voltage in a circuit clocked by a conventional buffer driven clock is higher than that in a circuit clocked by a sinusoidal clock for identical rise times. This fact becomes even more highlighted if we compare the clocks in the frequency domain. As an example, for a 3-GHz clock signal in a resonant clocking network the rise time is about 100 ps generating a peak SSN voltage of 0.4 mV. In a conventional network, the same clock is typically generated by smaller rise time, say 10% of clock period E33 ps, which results in 2.5 mV peak SSN voltage (i.e., about 6 times higher than that of resonant network). Due to this fact, we can expect to get far better switching noise performance by employing resonant clock distribution networks. 3.3. Lumped RLC model The model shown in Fig. 3(b) is a simplified model to derive the analytical expressions presented so far. However in practice, the resistive loss of inductor should be included in the model as well

SSN Voltage (mV)

tr=50 ps

t r=25 ps

I L ¼ I M1  C SS

 cos ðωðt  t 0 ÞÞÞ: ð12Þ

2

as the capacitance which is contributed by wires, interconnects, I/O pads, etc. Due to this fact, we consider the model shown in Fig. 6. Thus, the current through the inductor does not follow Eq. (4) anymore. Instead we rewrite it as

1

0

-1

dvn : dt

ð13Þ

In addition, the SSN voltage can be calculated by vn ¼ RSS I L þLSS

dI L : dt

ð14Þ

Combining Eqs. (4), (13), and (14) results in a second-order differential equation with respect to vn. Utilizing a similar method to that presented in [21], a first-order differential equation can be reached as a1

dvn dv þ a2 vn ffia3 ðvin V tn Þn þ a4 in dt dt

ð15Þ

where a1 ¼ RSS C SS þ FKLSS

ð16Þ

a2 ¼ FKRSS þ 1

ð17Þ

a3 ¼ KRSS

ð18Þ

a4 ¼ FKLSS :

ð19Þ

In these equations, F is considered as a constant close to 1 as it was discussed in deriving Eq. (6). If we set RSS ¼ CSS ¼0, we get a1 ¼ FKLSS ¼ 1=B, a2 ¼ 1, a3 ¼ 0, and a4 ¼ 1=B, so Eq. (15) reduces to Eq. (7) as it is expected. Since n is not an integer number, Eq. (15) has no straight-forward closed-form solution, however, we can solve it numerically using tools like Maple or Matlab. To do so, we apply both exponential and sinusoidal inputs with different rise (fall) times as we did to plot Figs. 4 and 5. The resulted peak-topeak SSN voltage is plotted in Fig. 7. Here, we have used a minimum size transistor which is connected to ground rail (as it is shown in Fig. 6) by LSS ¼ 1 nH, CSS ¼0.5 pF, and RSS ¼5 Ω. As it is expected, the noise voltage reduces by increasing the rise time of the clock signal. Furthermore, it reconfirms our previous results showing that the SSN voltage is lower in a network clocked by a sinusoidal clock compared to that in a traditionally clocked network. Obviously, one might argue that the clock which is generated by a resonant clocking network is not an ideal sine wave and it might suffer from harmonic distortion. In Section 4, we investigate the effect of the distortion on the SSN voltage in a resonant clocking network. 3.4. Resonance effect

tr=200 ps

t r=100 ps

-2 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Time (ns) Fig. 5. SSN voltage for a sinusoidal clock signal for different frequencies.

One of the most important issues in any PDN is the resonance effect associated with parasitics contributed by devices and power rails. In order to have better understanding about the phenomenon, let us consider an RLC network (similar to that shown in

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B. Mesgarzadeh / INTEGRATION, the VLSI journal 47 (2014) 242–249

0.95

SSN Peak (mV)

SSN Voltage p-p (mV)

4 3.5 3 2.5 2

Exponential Clock

1.5

0.9

+12%

0.85

0.8

1 0.5

0.75 -60

Sinusoidal Clock

-55

-50

0 25

50

75

100

125

150

175

-45

-40

-35

-30

-25

-20

2nd Harmonic (dBc)

200

Rise Time (ps)

Fig. 9. SSN variation due to the 2nd harmonic (A3 ¼ 0).

Fig. 7. Peak-to-peak SSN voltage using RLC lumped model. 1.05

SSN Peak (mV)

210

Impedance (Ω)

180 150 120 90 60

1

+11%

0.95

0.9

0.85 -60

30

-55

-50

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

2.5

-40

-35

-30

-25

-20

Fig. 10. SSN variation due to the 3rd harmonic (A2 ¼0.1A1).

Frequency (GHz) Fig. 8. Resonance effect in PDN.

Fig. 6). The frequency-dependent impedance can be written as Z RLC ðsÞ ¼

-45

3rd Harmonic (dBc)

0

Ls þ R LCs2 þ RCs þ 1

which has a resonant frequency at sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 1 R  ω0 ¼ : LC L

ð20Þ vn;k ðtÞ ¼

ð21Þ

Fig. 8 plots Eq. (20) in the frequency domain for L ¼3 nH, C ¼3 pF, and R¼5 Ω, which gives us a resonant peak at 1.6 GHz. As it is shown in this figure, the impedance in power rails increases significantly around the resonance frequency resulting in significant voltage drop. Due to this fact, depending on the clock frequency, this issue might contribute to the SSN considerably. An interesting observation in resonant clocking is that in the PDN which is connected to the LC oscillator, this impedance is absorbed by the LC tank (because of the capacitance couplings) and it resonates away at the tank oscillation frequency. This fact, which is another advantage of resonant clocking over conventional clocking, is shown by circuit simulations in Section 6.

4. Effect of distortion on SSN The clock signal in a resonant clock distribution network is generated by an LC oscillator. The output of an LC tank is considered to be a sine wave due to selectivity of the tank. However, since the quality factor of an LC tank is limited, the output clock suffers from distortion and its spectrum contains higher harmonics. In such a sine wave, the magnitude of higher harmonics reduces sharply and due to this fact, we only focus on the effect of the 2nd and 3rd harmonics. Thus, the generated sinusoidal clock by a resonant clocking network can be written as V CLK  A0 þ A1 cos ðωtÞ þA2 cos ð2ωtÞ þ A3 cos ð3ωtÞ

3rd harmonic, respectively. To calculate the SSN voltage, we apply this signal as the input signal (vin) in Eq. (7) and solve it. Employing the superposition concept, the effect of kth harmonic on SSN voltage is

ð22Þ

where A0 is the DC component, and A1, A2, and A3 are the magnitudes of the fundamental tone, the 2nd harmonic, and the

Ak

½k ω2 cos ðkωtÞ  Bkω sin ðkωtÞ þ B2 e  Bt  2

2

B 2 þ k ω2

ð23Þ

where Ak is the magnitude of the kth harmonic. We assume that the magnitudes of the 2nd and 3rd harmonics are between 20 dB and 60 dB lower than that of the fundamental tone (i.e., 0.001 oA2/A1 o0.1). This covers an acceptable range for the output of an LC oscillator. Fig. 9 plots the peak noise voltage for the case of 50-ps rise time. In this figure, the effect of the 2nd harmonic on SSN is shown when we neglect the effect of the 3rd harmonic (A3 ¼0). As it is shown in Fig. 9, for magnitudes lower than  50 dBc, SSN voltage remains almost constant. Increasing the magnitude of the 2nd harmonic increases the SSN peak voltage and at  20 dBc, SSN voltage increases by about 12% compared to an ideal sine wave case. Now, let us consider the effect of the 3rd harmonic as well. We set the magnitude of the 2nd harmonic to  20 dBc (the worstcase), and sweep the magnitude of the 3rd harmonic at the same range as we did for the 2nd harmonic. Fig. 10 shows the resulted SSN. The SSN peak voltage increases by about 11% across this range. In conclusion, adding harmonic distortion to a pure sine-wave clock increases the SSN voltage in the power rails depending on the magnitude of the added harmonic tones. However, comparing Fig. 4 and Fig. 10 and considering the discussion in the previous section shows that still a sinusoidal clock exhibits better noise performance compared to a traditional clock generated by clock buffers.

5. Short-circuit power dissipation One of the disadvantages of utilizing relaxed clock edges is to increase the short-circuit power dissipation in the clocked elements. Increasing the rise/fall time gives the chance for both

NMOS and PMOS transistors to be on at the same time burning needless extra power. Due to this fact, we should investigate this problem carefully in a resonant clocking network which utilizes a sinusoidal clock signal. For modeling of short-circuit power there are several works which have tried to approach an accurate estimation. A straight-forward model and formulation has been presented in [22]. However, in this formulation, long-channel devices have been targeted. We need to modify the formulation in order to get an acceptable result in a short-channel CMOS process. To do so, let us consider an inverter stage and its current waveform (when it is not loaded), as it is shown in Fig. 11. We need to integrate the transistor current in one cycle to calculate the average short-circuit power dissipation. For simplicity of the integration, we can neglect the SSN voltage variations. It is reasonable since as it is shown in Fig. 4, the voltage drop due to SSN is less than 5 mV, while the threshold voltage of the utilized NMOS transistor is about 300 mV. Specially, the worst-case short-circuit power dissipation occurs for relaxed clock edges where the SSN voltage is even less than 1 mV. Then accuracy of our comparison is not affected by neglecting the SSN voltage fluctuations. For a short-channel transistor in saturation region, neglecting the channel length modulation effect and considering Fig. 11, we write I mean ¼ 2 

2 T

Z

t2 t1

Kðvin  V t Þn dt:

ð24Þ

where Vt is the threshold voltage of the transistor. Multiplying the result by the power supply voltage value gives the short-circuit power dissipation. Since n is not an integer number, the simplest way to calculate Eq. (24) for different input waveforms (vin) is to use the numerical integration. We are again interested in two different input signals. First,we apply an exponential clock signal. Hence, we assume vin ¼ V DD 1  e  t=τ . According to Fig. 11, t1 and t2 can be determined as
 V tn ; t 1 ¼  τ ln 1  V DD

t 2 ¼ τ ln 2

ð25Þ

where Vtn is the threshold voltage of the NMOS transistor. By using these values and the parameters of 65-nm CMOS technology, the short-circuit power dissipation can be plotted for different rise times as it is shown in Fig. 12 for a 1-GHz clock signal. As it is shown, the short-circuit power dissipation increases when the rise time increases. Now, let us apply a sinusoidal input to calculate the shortcircuit power dissipation. As before, we assume vin ¼ 0:5V DD ð1  cos ωtÞ. Using a similar method, we determine the values of

Vin tr Vdd

T

Vdd Vdd - |Vtp| Vtn

Vin

Vout

t I

t 1 t2 Fig. 11. An inverter stage and its short-circuit current.

t

Short-Circuit Power (nW)

B. Mesgarzadeh / INTEGRATION, the VLSI journal 47 (2014) 242–249

247

200 160 120 80 40 0 50

70

90

110

130

150

170

190

210

230

250

Rise time (ps) Fig. 12. Short-circuit power dissipation in an inverter stage.

t1 and t2 as t1 ¼


 1 2V tn cos  1 1  ; 2πf V DD

t2 ¼

1 4f

ð26Þ

where f is the clock frequency (i.e., f ¼ ω=2π). Using these values and numerical solution of Eq. (24), the short-circuit power dissipation of an inverter with a 1-GHz sinusoidal clock is calculated to be 447 nW. Considering Fig. 12, this value is 6 times larger than that of a traditional buffer-driven clock signal at 1-GHz with a 100-ps rise time. Repeating this procedure for other clock frequencies gives a similar result. In conclusion, by employing resonant clock distribution instead of traditional clocking, the short-circuit power dissipation in the clocked elements increases significantly. The results presented in [17] also confirm that about 34% higher power is dissipated in the clocked elements in the resonant network compared to the conventional clocking which is due to short circuit power dissipation. However, the total power in the clock network is still about 14–29% lower in a resonant clock distribution network [17,18].

6. Results and comparison In order to verify our analysis in circuit level, we have designed both resonant and conventional clock networks in 65-nm CMOS process. To do so, two identical clock loads consisting of 250 flipflops each, are clocked by the output of an LC oscillator and also by output of a 6-stage tapered buffer chain. A block level description of our setup is depicted in Fig. 13. To model the SSN voltage a lumped RLC network is utilized which connects the clocked elements (i.e., the flip-flops) to supply rails. Fig. 14 shows a comparison between the supply noise voltage in the conventional buffer-driven network to that in the resonant network. Here, we have used 1 nH for the inductors, 0.5 pF for the capacitors, and 5 Ω for the resistors. With these values, the selfresonance frequency of the RLC network is high enough (i.e., about 7 GHz in this case) to just focus on di/dt noise. As it is shown in this figure, for the frequencies up to 2 GHz, in the worst case the resonant clock network generates 45% lower supply noise. As expected, the noise reduction in lower frequencies is more significant as the edges of the sinusoidal clock become more relax. The resonance effect which has been discussed in Section 3.4, is shown in Fig. 15. Here, we use 3 nH for the inductors, 3 pF for the capacitors, and 5 Ω for the resistors to set the self-resonance frequency of RLC network at about 1.6 GHz. Around the resonance frequency, the SSN noise voltage is dominated by the impedance variation. However, as it is mentioned earlier, due to capacitive coupling between the RLC network and the LC tank, we cannot see this effect in the resonant clocking network. Due to this fact, a significant noise reduction is achieved at frequencies close to resonant frequency of the RLC network (i.e., 69% in this case).

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increasing short-circuit currents in lower frequencies; the ratio increases significantly, as it is expected. At 660-MHz clock frequency, the flip-flops clocked by the LC oscillator dissipate 3.55 times higher power compared to those clocked by tapered buffer chain. This ratio decreases in higher frequencies as the rise time of the sinusoidal clock decreases. However, considering the total power dissipation, this increased power in the clocked elements is compensated by the total clock power savings, as it has been discussed thoroughly in the literature [16–19].

VDD

LDD

CDD

D

RDD

Digital Block

Out D Out D Out Clk Clk Clk

VSSN RSS CSS

7. Conclusions

Conventional Clocking

Resonant Clocking

LSS

In the previous works, it has already been shown that a resonant clock distribution network has great capability in reducing the clock power. In this paper, we focused on the noise performance of such a network. Using an analytical method, it has been shown that resonant clocking reduces also the SSN on the power supply rails in comparison with that of a conventional buffer-driven clocking scheme. On the other hand, the main drawback of using such a clocking network is that short-circuit power dissipation in clocked elements increases due to employing relaxed clock edges. However, this is fortunately compensated by the overall clock power savings according to the previous studies.

Fig. 13. Modeling of SSN voltage on the power rails.

420

SSN Voltage (mV)

370

Conventional

320 270

- 45% - 61%

220

Resonant

170

References

120 70 0.66

0.8

1

1.2

1.5

1.75

2

Frequency (GHz) Fig. 14. Supply noise comparison.

370

SSN Voltage (mV)

320 270

Conventional - 69%

220 170

Resonant

120 70 1

1.2

1.5

1.75

2

2.5

Frequency (GHz) Fig. 15. Resonance effect in PDN.

4

Ratio (Res/Conv)

3.55X 3

2

1

0 0.66

0.8

1

1.2

1.5

1.75

2

Frequency (GHz) Fig. 16. Power dissipation ratio in the clocked elements (resonant to conventional).

A comparison of power dissipation in flip-flops is shown in Fig. 16. This figure plots the ratio of power dissipation in clocked elements in resonant clocking to conventional clocking. Due to

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Behzad Mesgarzadeh received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2000, and the M.Sc. and Ph.D. degrees in electrical engineering from Linköping University, Linköping, Sweden, in 2004 and 2008, respectively. He is currently an Assistant Professor at the Department of Electrical Engineering, Linköping University. His research interests include low-power low-jitter clock generation and distribution, high-performance frequency synthesizers, and high-data-rate communication systems. Dr. Mesgarzadeh was the recipient of the 50th IEEE Midwest Symposium on Circuits and Systems Best Student Paper Award in 2007.