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Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip
MR-12295; No of Pages 6 Microelectronics Reliability xxx (2017) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip Xuecheng Du a, Shuhuan Liu a,⁎, Dongyang Luo c, Yao Zhang a, Xiaozhi Du c, Chaohui He a, Xiaotang Ren b, Weitao Yang a, Yuan Yuan a a b c
School of Nuclear Science and Technology, Xi'an Jiaotong University, Xi'an City 710049, China Peking University, Beijing 100000,China School of Software Engineering, Xi'an Jiaotong University, Xi'an City 710049, China
a r t i c l e
i n f o
Article history: Received 26 May 2016 Received in revised form 15 February 2017 Accepted 20 February 2017 Available online xxxx Keywords: System on chip Single event effects Proton irradiation
a b s t r a c t In this paper, experimental methods are emphatically described for measuring the proton single event effects (SEE) in Xilinx Zynq-7010 system-on chip. Experimental data are presented showing that low energy (3 MeV ≤ Energy ≤ 10 MeV) proton irradiation can cause single event effects in different hardware blocks of Xilinx Zynq-7010 SoC, including D-Cache, programmable logic (PL), arithmetic logical unit (ALU), float point unit (FPU) and direct memory access (DMA). Moreover, the sensitivities of different hardware blocks to single event effects are different. Finally, the Stopping and Range of Ions in Matter (SRIM) software calculations show the possible reasons for this difference. © 2017 Published by Elsevier Ltd.
1. Introduction Because of its small size, great functionality, low power consumption and other useful features, system-on chip (SoC) is widely used in many fields, including mobile communication, control system and aerospace. In particular, SoC is very attractive to the aerospace sector, because it helps the system integration, and miniaturization. However, as feature size and operating voltage decrease, SoC is becoming more susceptible to single event effects (SEE) [1].Single event effects are induced by the interaction of an ionizing particle with the sensitive regions of microelectronic device. Ionizing particles can be protons, heavy ions, and neutrons [2]. Protons are very important part in the space environment and arise from Van Allen radiation belts, solar events (solar flares and Coronal Mass Ejections) and galactic cosmic rays [3]. The Van Allen radiation belts have two radiation belts, which predominantly consist of electrons and protons. The energy ranges commonly encountered go from some keV up to some tens or even hundreds of MeV. The Galactic Cosmic Rays comprise 85% protons, 14% alpha particles, and 1% heavy ions [4, 5]. Therefore, the SEE induced by proton has caused a serious impact on the electronic systems in space, especially for the low-energy protons at radiation belts in nanometer-scale integrated circuits. A lot of SEE experiments induced by protons have been performed, including static random access memory (SRAM) [6–9]. However, a few experiments and researches about proton SEE in SoC have been done, ⁎ Corresponding author. E-mail address: [email protected] (S. Liu).
particularly when the microelectronics enters the nanometer technology node. For example, Boeing Maestro ITC [10] and Freescale P2020 & P5020 [11] have been performed through high energy protons. For Xilinx Zynq-7000 SoC, a single event upset experiment by high-energy protons was carried out and it mainly concentrated on the SEU in the memory elements, such as on-chip memory and L2 Cache [12]. However, the response of the other blocks to protons is also important in 28 nm technology node. In this work, low energy proton experiments (3 MeV ≤ E ≤ 10 MeV) using the dynamic testing methods were performed to characterize the SEE sensitivity of D-Cache, programmable logic (PL), arithmetic logical unit (ALU), float point unit (FPU) and direct memory access (DMA) in the Xilinx Zynq-7010 SoC. Moreover, the SEE cross sections of different blocks under test were obtained. 2. Experimental detail 2.1. Device under test The Xilinx Zynq-7010 All Programmable SoC was used to perform this proton experiment. The SoC system integrates processing system (PS) and Xilinx programmable logic (PL) in a single chip, which is fabricated with 28 nm technology node. The Fig.1 shows the structure of Xilinx Zynq-7010 all programmable SoC. The PS includes ARM CortexA9 CPUs, 252 KB on-chip memory, 512 KB L2 Cache, 32 KB L1 D-Cache and I-Cache, DMA controller, Timers, watchdog, and various peripheral interfaces. The PL is derived from Xilinx 7 series SRAM-based FPGA (Artix-7 for 7Z010), including configuration storage based on SRAM-
http://dx.doi.org/10.1016/j.microrel.2017.02.014 0026-2714/© 2017 Published by Elsevier Ltd.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
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X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 1. The structure block of Xilinx Zynq-7010 SoC [13].
type, programmable logic blocks (CLB), block ram (BRAM), DSP blocks, programmable I/O Blocks, and other resources. The PL stores their customized configuration in configuration storage. The PS is attached to the PL through multiple ARM AMBA AXI ports, creating extremely efficient coupling between these two key components of the Zynq-7000 architecture [13,14]. The various components to be tested include ALU, FPU, DMA, L1D-Cache and PL. The cores (PS and PL) operate with an internal supply voltage of 1.0 V and an auxiliary supply voltage of 1.8 V in the testing process.
diameter [15]. The test system (Fig.2) is composed mainly of host computer, current monitor and test board. The host computer is in charge of the testing flow and recording experimental results. The operating current of test board is monitored with the current monitor section by measure the current of sense resistor. The MicroZed development board was chosen as the test board. It contains SoC chip under test, 1GB of DDR3 SDRAM, 128 Mb of QSPI Flash, Micro Secure Digital (SD) card interface, USB-UART and some extension interfaces [16]. 2.3. Test methods
2.2. Test system The radiation experiment and measurement were carried out on Zynq-7010 SoC Chip using low energy proton provided by EN Tandem Accelerator of Peking University. Its installation and commissioning has been completed quickly in 1989. Various ions, such as 1H, 12C, 16O, 19 35 F, Cl, 79Br, are accelerated. The beam spot at the target is b3 mm in
The different blocks of SoC were checked during irradiation. These test methods are described in details as follows: ALU test: ALU performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, an algorithm was designed, which involved integer mathematical operations, logical operations,
Fig. 2. The structure chart of testing system.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx Table 1 Resource utilization of the circuit design in PL. Resource
Utilization
Available
Utilization rate (%)
Flip-Flop LUT Memory LUT DSP48 BUFG
1177 1259 62 2 1
35,200 17,600 6000 80 32
3.34 7.15 1.03 2.50 3.12
3
a specific circuit design [18]. In this test, the circuit was designed to solve a simple DSP operation (ax2 + bx + c). The design used the LUTs, Flip-Flop, DSP, Clocking and other programmable resources. The resource utilization is shown in Table 1. These methods were coded in C language and hardware description language (VHDL) for different blocks. Moreover, test programs were stored in micro SD card and loaded into the SoC system when the system was started. 2.4. Test process The main part of the testing flow is shown in Fig.3 [19]. The proton SEE tests were performed in different blocks of SoC under test, including ALU, FPU, D-Cache, DMA and PL. The energies of proton beam were chosen at 3 MeV, 5 MeV and 10 MeV. Firstly, the block under test was chosen and tested for correct operations by loading the test program, such as D-Cache. Secondly, the proton beam was only targeted the SoC chip and the fluence and irradiation time were recorded. Thirdly, the block status under test was checked consistently during irradiation. Once an error occurred, the host computer recorded number and error types in a log file and reloaded the test program. Each test run was performed to a total fluence of at least 1 × 1011 p/cm2. 3. Experimental result In this section, the experiment results for different blocks of SoC have been summarized. The number of SEE events for tested blocks and the cross sections are given. The SEE cross section is calculated by summing SEE events and fluence at each energy for the specific block [20]. The cross section σ is calculated as shown in Eq. (1). σ¼
Fig. 3. The flow chart of testing process.
N F
ð1Þ
where N is the number of events, F is the fluence in particles/cm2. The proton beam fluxes were 2.496 × 108 p/cm2 s at 3 MeV, 2.08 × 108 p/cm2 s at 5 MeV, and 2.76 × 10 p/cm2 s at 10 MeV. Table 2 summarize the experimental results of different blocks. The SEE cross sections vs proton energy curves for different blocks were depicted in Figs. 4–7 and all error bars are 1σ based on Poisson statistics. The major sources of uncertainty in cross section are the fluence of protons and the number of SEE events. Due to the number of SEE events is small and limited, it is the dominate contribution to the uncertainty. Therefore, the standard deviation in the cross section is calculated using Eq. (2) [21,22].
and shift operations. By comparing the calculated results with the expected results, the host computer records the errors. D-Cache test: There are 32 kb L1 D-cache and 32 kb L1 I-Cache in individual CPU core of PS. A write/read test was developed to explore potential SEE sensitivity in D-Cache with the Cache Flush instruction and the Cache Invalidate instruction. The D-cache was written the initial value (0xFF) in the entire data cache, flushed the range, written a new value, and invalidated the corresponding range. Moreover, the error correction code (ECC) was not applied in L1 D-Cache during the testing process. FPU test: The main function of FPU is to carryout addition, subtractions, multiplication, division, and square boot operations on floating point numbers. Therefore, the Fast Flourier Transform was executed by FPU. If any result was not as expected the function producing the result, the FPU was abnormal. PL test: The programmable logic is based on artix-7 FPGA, a static sensitive cross section has been characterized by the device manufacture [17]. Therefore, the dynamic cross section of PL is tested to
Error ¼
pffiffiffiffi N F
ð2Þ
As can be seen in the cross section curves, a quite different SEE sensitivity could be observed between D-Cache and others. Obviously, the proton cross section curves of D-Cache decreases with an increase in the proton energy increased. However, if error bars are not shown, others increase with an increase in the proton energy increased. The experimental results have also demonstrated the PL and Cache are more
Table 2 The protons experimental results for Zynq-7010 SoC. Blocks
PL D-Cache ALU FPU
3 MeV
5 MeV
Error events
Fluence (cm−2 s−1)
10 28 3 5
9 9 9 9
× × × ×
1011 1011 1011 1011
Cross section (cm2/device) 1.11 3.10 0.33 0.56
× × × ×
10−11 10−11 10−11 10−11
10 MeV
Error events
Fluence (cm2 s−1)
16 10 6 7
7.5 7.5 7.5 7.5
× × × ×
1011 1011 1011 1011
Cross section (cm2/device) 2.13 1.33 0.80 0.93
× × × ×
10−11 10−11 10−11 10−11
Error events
Fluence (cm−2 s−1)
8 5 3 7
3.7 3.7 3.7 3.7
× 1011 × 1011 ×1 011 × 1011
Cross section (cm2/device) 2.16 1.35 0.81 1.89
× × × ×
10−11 10−11 10−11 10−11
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
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Fig. 4. SEE cross sections vs proton energy for D-Cache.
sensitive than other tested blocks during protons irradiation. In addition, the working current has not obvious change and no single event latch-up (SEL) event is observed during irradiation. 4. Discussion 4.1. Single event sensitivity for the D-Cache The critical charge (Qcrit) is defined as the minimum charge which is needed to upset the state of latch or memory cell. Moreover, the critical charges of the sequential nodes approximately scale according to. Q crit ≈ Vcc C
ð3Þ
where Vcc equals the power supply voltage, and C denotes the node capacitance [23,25]. Hence, Qcrit is also expected to decrease with the decreasing of technology scaling. Moreover, if the collected charge is equal or larger than Qcrit, an upset is occurred. According to the recent research results, the Qcrit for 32 nm SRAM technology is about 0.2 fC
[24]. Due to the Xilinx Zynq-7010 SoC based on 28 nm CMOS technologies, the Qcrit should be smaller than 0.2 fC. The LET value of 10 MeV protons is 0.355 fC/μm by using SRIM (Stopping Range of Ion in Matter) software, as shown in Table 3. The SRIM includes quick calculations which produce tables of stopping powers, range and straggling distributions for any ion at any energy in any elemental target [27]. It is assumed that charge collection depth equals 1 μm. The sufficient charges caused by low-energy proton direct ionizing could result in single event upsets in D-Cache from 3 to 10 MeV. The stopping power for proton into silicon can be determined with SRIM software, and the known decrease in LET value for low energy protons can be observed from 3 to 10 MeV, as shown in Fig. 8. The decrease trend from 3 to 10 MeV is in accordance with D-Cache curve. It is a possible reason that the D-Cache cross section decreases as the proton energies increases. 4.2. Single event effect sensitivities for the tested blocks except the D-Cache Due to the number of SEE events for the PL, ALU, and FPU are relatively smaller, the statistical error have a great effect on the
Fig. 5. SEE cross sections vs proton energy for PL.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx
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Table 3 The proton beam LET value caused by direct ionizing mechanism.
Fig. 6. SEE cross sections vs proton energy for ALU.
experimental results. It would be difficult to give a precise mechanism analysis for the other blocks except the D-Cache. Single event effects may have been caused by two factors for the tested blocks, including indirect ionization and direct ionization. On the one hand, because these components are mainly composed of combination logic and sequential logic circuits, such as latch, Flip-Flop circuits. The research results have shown that the Qcrit for logic circuits is dramatically larger than memory bit cell [23–26]. The SEE events may be caused by the indirect ionization in ALU, PL, and FPU blocks. The indirect ionization creates secondary particles (recoils) by the interactions of incident protons with the atomic nuclei of semiconductor devices initiate processes. In general, the nuclear interactions produce some secondary particles or recoils and fragments, including Mg, Al, Na nuclei [28,29]. The main nuclear reactions include the following: Pþ
28
Si→ 4 He þ
25
Pþ
28
Si→ 4 He þ P þ
Pþ
28
Si→ 12 C þ
Pþ
28
Si→214 N þ P:
Mg; 25
Energy (MeV)
LET (fC/μm)
3 5 10
0.866 0.599 0.355
energies below 10 MeV, the nuclear reactions cross section (P + 28Si) increases as the proton energy increases [30]. The trend is in agreement with the testing result curves for blocks under test except D-Cache. On the other hand, the protons reach silicon surface with a range of energies because of the multi-layer metallization and other materials above the active silicon layer. The protons lost a different value of energy through a variety of paths, due to the complex topologies of the metal wires and BEOL materials [31]. Therefore, the protons energy will be decreased to below 3 MeV. The lower energy protons have higher LET values through direct ionization mechanism. Therefore, single event effects in combination logic and sequential logic circuits would be produced by low-energy protons that lost energy in transporting process. The single event effects in PL, FPU, and ALU could be the results of direct and indirect ionization interactions. In addition, single event function interrupt event (SEFI) was detected during irradiation. Table 4 shows the number of SEFI events and distributions in different blocks. The SEFI has a serious impact on the reliability of electronic system and it is hard to determine the underlying cause of these malfunctions. The fault injection experiments performed in software-based fault injection technique. Some reasons for SEFI are listed: the SEU happened in the shift registers that control the address of the control logic; some errors arose in the address register that stores the memory address; some errors caused by SEU in the special register, such as current program status register or program counter; instruction registers were modified by SEU resulting in unknown instruction code or undefined instruction code. The above errors can result in test program being halted, destruction of normal program control flow, and some unknown, unrecognizable state.
Na; 5. Conclusion
16
O þ P; The SEE experiments of Xilinx Zynq-7010 SoC were performed to investigate the SEE susceptibility of different blocks using low-energy protons based on dynamic testing methods. The dynamic cross sections
These recoils may ionize enough charges to cause an upsets depending on their linear energy transfer (LET) values. The LET values of different secondary particles versus energy are shown in Fig. 9. According to the Fig. 6, the LET value is increasing with the energy. In addition, for
Fig. 7. SEE cross sections vs proton energy for FPU.
Fig. 8. SRIM output with proton range and LET value in silicon.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
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X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 9. The LET value vs proton energy in different recoils.
Table 4 The SEFI results for different blocks of the SoC under test. Blocks
Proton energy (3 MeV) Number of SEFI events
Proton energy (5 MeV) Number of SEFI events
Proton energy (10 MeV) Number of SEFI events
PL D-Cache ALU FPU
7 21 3 5
9 7 6 7
4 5 3 7
of different blocks in different energies protons were calculated. The experimental results have revealed the PL and D-Cache were more sensitive than the other blocks and easily susceptible to SEE. Moreover, the charge curve of cross sections versus proton energy for D-Cache is different from the other tested blocks. Acknowledgements This work was supported by National Natural Science Foundation of China (grant no. 11175139), the National Natural Science Foundation of China (grant no. 11575138), and the Key Program of the National Natural Science Foundation of China (grant no. 11235008). References [1] S.M. Tony, H. Mohammed, J. Mathew, D.K. Pradhan, Soft-error Induced Systemfailure Rate Analysis in an SoC, Norchip19–20 Nov 2013 (Aalborg, Denmark). [2] P.E. Dodd, L.W. Massengil, Basic mechanisms and modeling of single-event upset in digital microelectronics, IEEE Nucl. Plasma Sci. Soc. 50 (3) (2003) 583. [3] C.S. Dyer, S.N. Clucas, C. Sanderson, A.D. Frydland, R.T. Green, An experimental study of single event effects induced in commercial SRAMs by neutrons and protons from thermal energies to 500 MeV, IEEE Trans. Nucl. Sci. 51 (4) (2004) 2817. [4] C. Claeys, E. Simoen, Radiation Effects in Advanced Semiconductor Materials and Devices, Radiation Environments and Component Selection Strategy, Springer, 2002 1–5.
[5] I.A. Daglis, Space storms and space weather hazards, in: M.I. Panasyuk (Ed.) Cosmic Ray and Radiation Belt Hazards for Space Missions, Springer 2001, pp. 251–256. [6] R.K. Lawrence, J.F. Ross, N.F. Haddad, et al., Proton induced soft error sensitivities in 90 nm bulk CMOS, IEEE Radiation Effects Data Workshop, 2009 20–24 July. (La Jolla, CA). [7] D.F. Heidel, P.W. Marshall, K.A. LaBel, et al., Low energy proton single–event-upset test results on 65 nm SOI SRAM, IEEE Trans. Nucl. Sci. 55 (6) (2008). [8] E.H. Canon, M. Cabanas-Holmen, J. Wert, T. Amort, et al., Heavy ion, high-energy, and low-energy proton SEE sensitivity of 90-nm RHBD SRAMs, IEEE Trans. Nucl. Sci. 57 (6) (2010). [9] S.T. Liu, H.Y. Liu, D. Anthony, et al., Proton-induced upset in SoI CMOS SRAM, IEEE Nucl. Plasma Sci. Soc. 51 (6) (2004). [10] B. Wie, M.K. Plante, A. Berkley, S.M. Guertin, R.J. Nejad, Static, Dynamic, and Application-level SEE Results for a 49-core RHBD Processor, IEEE Radiation Effects Data Workshop (REDW)8–12 July 2013 (San Franciso, CA, USA). [11] S.M. Guertin, Mehran Amrbar, SEE Test Results for P2020 and P5020 Freescale Processors, IEEE Radiation Effects Data Workshop (REDW)14–18 July 2014 (Paris, France). [12] Lucas Antunes Tambara, Alexey Akhmetov, Dmitriy Y. Bobrovsky, Fernanda Lima Kastensmidt, On the characterization of Embedded Memories of Zynq-7000 Programmable SoC under Single Event Upsets Induced by Heavy Ions and Protons, IEEE RADECS14–18 Sept. 2015 (Boston, MA). [13] Xilinx, Inc., Zynq-7010 All Programmable SoC Overview, DS190 (v1.8), 2015. [14] Xilinx, Inc., Zynq-7000 All Programmable SoC Technical Reference Manual, UG585 (v1.10), 2015. [15] C. Chen, Z. Guo, S. Yan, et al., Status of the tandem accelerator mass spectrometry facility at Peking University, Nucl. Instrum. Methods Phys. Res., Sect. B 52 (1990) 306–309. [16] Available: http://zedboard.org/product/microzedN 2015. [17] Xilinx, Inc., Device Reliability Report, UG116 (v10.3.1), 2015 (Available: bhttp:// www.xilinx.com/support/documentation/user_guides/ug116.pdfN). [18] K. Morgan, M. Caffrey, P. Graham, E. Johnson, B. Pratt, M. Wirthlin, SEU-induced persistent error propagation in FPGAs, IEEE Trans. Nucl. Sci. 52 (6) (2005) 2438. [19] Farokh Irom, Guide for Ground Radiation Testing of Microprocessors in the Space Radiation Environment, Jet Propulsion Laboratory, Pasadena, California, 2008 14. [20] J.R. Kimbrough, N.J. Colella, S.M. Denton, D.L. Shaeffer, D. Shih, J.W. Wilburn, P.G. Coakley, C. Caseneda, R. Koga, D.A. Clark, J.L. Ullmann, Single event effects and performance predication for space application of RISC processor, IEEE Trans. Nucl. Sci. 41 (6) (1994) 2708. [21] E.L. Petersen, Single-event data analysis, IEEE Trans. Nucl. Sci. 55 (6) (2008) 2820–2821. [22] J.R. Kimbrough, N.J. Colella, S.M. Denton, D.L. Shaeffer, et al., Single event effects and performance prediction for space applications of RISC processors, IEEE Trans. Nucl. Sci. 41 (6) (1994) 2708. [23] P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, L. Alvisi, Modeling the effect of technology trends on the soft error rate of combinational logic, Proceedings International Conference on Dependable System and Networks, 390, 2002. [24] Eishi Ibe, Hitoshi Taniguchi, Yasuo Yahagi, Ken-ichi Shimbo, Tadanobu Tonba, Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule, IEEE Trans. Electron Devices 57 (7) (2010) 1531. [25] N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, B. Gill, J. Maiz, Radiation-induced soft error rates of advanced CMOS bulk devices, IEEE 44th Annual International Reliability Physics Symposium, 2006 (San Jose, CA, USA). [26] Taiki Uemura, Takashi Kato, Hideya Matsuyama, Impact of parasitic bipolar action and Sodt-error trend in bulk CMOS at terrestrial environment, IEEE International Reliability Physics Symposium, 2013 14–18 April. (Anaheim, CA). [27] Available: http://www.srim.org/N 2016. [28] K.P. Rodbell, D.F. Heidel, Henry H.K. Tang, M.S. Gordon, Phil Oldiges, Conal E. Murray, Low-energy proton-induced single-event-upset in 65 nm node, silicon-on-insulator latches and memory cells, IEEE Trans. Nucl. Sci. 54 (6) (2007) 2474–2479. [29] R. Koga, P. Yu, K. Crawford, S. Crain, V. Tran, Comparison of heavy ion and protoninduced single event effects (SEE) sensitivities, IEEE Trans. Nucl. Sci. 49 (6) (2002) 3135–3141. [30] J. Baggio, V. Ferlet-Cavrois, H. Duarte, O. Flament, Analysis of proton/neutron SEU sensitivity of commercial SRAMs-application to the terrestrial environment test method, IEEE Trans. Nucl. Sci. 51 (6) (2005). [31] David F. Heidel, Kenneth P. Rodbell, Phil Oldiges, Michael S. Gordon, et al., Single– event upset critical charge measurements and modeling of 65 nm silicon-oninsulator latches and memory cell, IEEE Trans. Nucl. Sci. 53 (6) (2006) 3515.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip Xuecheng Du a, Shuhuan Liu a,⁎, Dongyang Luo c, Yao Zhang a, Xiaozhi Du c, Chaohui He a, Xiaotang Ren b, Weitao Yang a, Yuan Yuan a a b c
School of Nuclear Science and Technology, Xi'an Jiaotong University, Xi'an City 710049, China Peking University, Beijing 100000,China School of Software Engineering, Xi'an Jiaotong University, Xi'an City 710049, China
a r t i c l e
i n f o
Article history: Received 26 May 2016 Received in revised form 15 February 2017 Accepted 20 February 2017 Available online xxxx Keywords: System on chip Single event effects Proton irradiation
a b s t r a c t In this paper, experimental methods are emphatically described for measuring the proton single event effects (SEE) in Xilinx Zynq-7010 system-on chip. Experimental data are presented showing that low energy (3 MeV ≤ Energy ≤ 10 MeV) proton irradiation can cause single event effects in different hardware blocks of Xilinx Zynq-7010 SoC, including D-Cache, programmable logic (PL), arithmetic logical unit (ALU), float point unit (FPU) and direct memory access (DMA). Moreover, the sensitivities of different hardware blocks to single event effects are different. Finally, the Stopping and Range of Ions in Matter (SRIM) software calculations show the possible reasons for this difference. © 2017 Published by Elsevier Ltd.
1. Introduction Because of its small size, great functionality, low power consumption and other useful features, system-on chip (SoC) is widely used in many fields, including mobile communication, control system and aerospace. In particular, SoC is very attractive to the aerospace sector, because it helps the system integration, and miniaturization. However, as feature size and operating voltage decrease, SoC is becoming more susceptible to single event effects (SEE) [1].Single event effects are induced by the interaction of an ionizing particle with the sensitive regions of microelectronic device. Ionizing particles can be protons, heavy ions, and neutrons [2]. Protons are very important part in the space environment and arise from Van Allen radiation belts, solar events (solar flares and Coronal Mass Ejections) and galactic cosmic rays [3]. The Van Allen radiation belts have two radiation belts, which predominantly consist of electrons and protons. The energy ranges commonly encountered go from some keV up to some tens or even hundreds of MeV. The Galactic Cosmic Rays comprise 85% protons, 14% alpha particles, and 1% heavy ions [4, 5]. Therefore, the SEE induced by proton has caused a serious impact on the electronic systems in space, especially for the low-energy protons at radiation belts in nanometer-scale integrated circuits. A lot of SEE experiments induced by protons have been performed, including static random access memory (SRAM) [6–9]. However, a few experiments and researches about proton SEE in SoC have been done, ⁎ Corresponding author. E-mail address: [email protected] (S. Liu).
particularly when the microelectronics enters the nanometer technology node. For example, Boeing Maestro ITC [10] and Freescale P2020 & P5020 [11] have been performed through high energy protons. For Xilinx Zynq-7000 SoC, a single event upset experiment by high-energy protons was carried out and it mainly concentrated on the SEU in the memory elements, such as on-chip memory and L2 Cache [12]. However, the response of the other blocks to protons is also important in 28 nm technology node. In this work, low energy proton experiments (3 MeV ≤ E ≤ 10 MeV) using the dynamic testing methods were performed to characterize the SEE sensitivity of D-Cache, programmable logic (PL), arithmetic logical unit (ALU), float point unit (FPU) and direct memory access (DMA) in the Xilinx Zynq-7010 SoC. Moreover, the SEE cross sections of different blocks under test were obtained. 2. Experimental detail 2.1. Device under test The Xilinx Zynq-7010 All Programmable SoC was used to perform this proton experiment. The SoC system integrates processing system (PS) and Xilinx programmable logic (PL) in a single chip, which is fabricated with 28 nm technology node. The Fig.1 shows the structure of Xilinx Zynq-7010 all programmable SoC. The PS includes ARM CortexA9 CPUs, 252 KB on-chip memory, 512 KB L2 Cache, 32 KB L1 D-Cache and I-Cache, DMA controller, Timers, watchdog, and various peripheral interfaces. The PL is derived from Xilinx 7 series SRAM-based FPGA (Artix-7 for 7Z010), including configuration storage based on SRAM-
http://dx.doi.org/10.1016/j.microrel.2017.02.014 0026-2714/© 2017 Published by Elsevier Ltd.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
2
X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 1. The structure block of Xilinx Zynq-7010 SoC [13].
type, programmable logic blocks (CLB), block ram (BRAM), DSP blocks, programmable I/O Blocks, and other resources. The PL stores their customized configuration in configuration storage. The PS is attached to the PL through multiple ARM AMBA AXI ports, creating extremely efficient coupling between these two key components of the Zynq-7000 architecture [13,14]. The various components to be tested include ALU, FPU, DMA, L1D-Cache and PL. The cores (PS and PL) operate with an internal supply voltage of 1.0 V and an auxiliary supply voltage of 1.8 V in the testing process.
diameter [15]. The test system (Fig.2) is composed mainly of host computer, current monitor and test board. The host computer is in charge of the testing flow and recording experimental results. The operating current of test board is monitored with the current monitor section by measure the current of sense resistor. The MicroZed development board was chosen as the test board. It contains SoC chip under test, 1GB of DDR3 SDRAM, 128 Mb of QSPI Flash, Micro Secure Digital (SD) card interface, USB-UART and some extension interfaces [16]. 2.3. Test methods
2.2. Test system The radiation experiment and measurement were carried out on Zynq-7010 SoC Chip using low energy proton provided by EN Tandem Accelerator of Peking University. Its installation and commissioning has been completed quickly in 1989. Various ions, such as 1H, 12C, 16O, 19 35 F, Cl, 79Br, are accelerated. The beam spot at the target is b3 mm in
The different blocks of SoC were checked during irradiation. These test methods are described in details as follows: ALU test: ALU performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, an algorithm was designed, which involved integer mathematical operations, logical operations,
Fig. 2. The structure chart of testing system.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx Table 1 Resource utilization of the circuit design in PL. Resource
Utilization
Available
Utilization rate (%)
Flip-Flop LUT Memory LUT DSP48 BUFG
1177 1259 62 2 1
35,200 17,600 6000 80 32
3.34 7.15 1.03 2.50 3.12
3
a specific circuit design [18]. In this test, the circuit was designed to solve a simple DSP operation (ax2 + bx + c). The design used the LUTs, Flip-Flop, DSP, Clocking and other programmable resources. The resource utilization is shown in Table 1. These methods were coded in C language and hardware description language (VHDL) for different blocks. Moreover, test programs were stored in micro SD card and loaded into the SoC system when the system was started. 2.4. Test process The main part of the testing flow is shown in Fig.3 [19]. The proton SEE tests were performed in different blocks of SoC under test, including ALU, FPU, D-Cache, DMA and PL. The energies of proton beam were chosen at 3 MeV, 5 MeV and 10 MeV. Firstly, the block under test was chosen and tested for correct operations by loading the test program, such as D-Cache. Secondly, the proton beam was only targeted the SoC chip and the fluence and irradiation time were recorded. Thirdly, the block status under test was checked consistently during irradiation. Once an error occurred, the host computer recorded number and error types in a log file and reloaded the test program. Each test run was performed to a total fluence of at least 1 × 1011 p/cm2. 3. Experimental result In this section, the experiment results for different blocks of SoC have been summarized. The number of SEE events for tested blocks and the cross sections are given. The SEE cross section is calculated by summing SEE events and fluence at each energy for the specific block [20]. The cross section σ is calculated as shown in Eq. (1). σ¼
Fig. 3. The flow chart of testing process.
N F
ð1Þ
where N is the number of events, F is the fluence in particles/cm2. The proton beam fluxes were 2.496 × 108 p/cm2 s at 3 MeV, 2.08 × 108 p/cm2 s at 5 MeV, and 2.76 × 10 p/cm2 s at 10 MeV. Table 2 summarize the experimental results of different blocks. The SEE cross sections vs proton energy curves for different blocks were depicted in Figs. 4–7 and all error bars are 1σ based on Poisson statistics. The major sources of uncertainty in cross section are the fluence of protons and the number of SEE events. Due to the number of SEE events is small and limited, it is the dominate contribution to the uncertainty. Therefore, the standard deviation in the cross section is calculated using Eq. (2) [21,22].
and shift operations. By comparing the calculated results with the expected results, the host computer records the errors. D-Cache test: There are 32 kb L1 D-cache and 32 kb L1 I-Cache in individual CPU core of PS. A write/read test was developed to explore potential SEE sensitivity in D-Cache with the Cache Flush instruction and the Cache Invalidate instruction. The D-cache was written the initial value (0xFF) in the entire data cache, flushed the range, written a new value, and invalidated the corresponding range. Moreover, the error correction code (ECC) was not applied in L1 D-Cache during the testing process. FPU test: The main function of FPU is to carryout addition, subtractions, multiplication, division, and square boot operations on floating point numbers. Therefore, the Fast Flourier Transform was executed by FPU. If any result was not as expected the function producing the result, the FPU was abnormal. PL test: The programmable logic is based on artix-7 FPGA, a static sensitive cross section has been characterized by the device manufacture [17]. Therefore, the dynamic cross section of PL is tested to
Error ¼
pffiffiffiffi N F
ð2Þ
As can be seen in the cross section curves, a quite different SEE sensitivity could be observed between D-Cache and others. Obviously, the proton cross section curves of D-Cache decreases with an increase in the proton energy increased. However, if error bars are not shown, others increase with an increase in the proton energy increased. The experimental results have also demonstrated the PL and Cache are more
Table 2 The protons experimental results for Zynq-7010 SoC. Blocks
PL D-Cache ALU FPU
3 MeV
5 MeV
Error events
Fluence (cm−2 s−1)
10 28 3 5
9 9 9 9
× × × ×
1011 1011 1011 1011
Cross section (cm2/device) 1.11 3.10 0.33 0.56
× × × ×
10−11 10−11 10−11 10−11
10 MeV
Error events
Fluence (cm2 s−1)
16 10 6 7
7.5 7.5 7.5 7.5
× × × ×
1011 1011 1011 1011
Cross section (cm2/device) 2.13 1.33 0.80 0.93
× × × ×
10−11 10−11 10−11 10−11
Error events
Fluence (cm−2 s−1)
8 5 3 7
3.7 3.7 3.7 3.7
× 1011 × 1011 ×1 011 × 1011
Cross section (cm2/device) 2.16 1.35 0.81 1.89
× × × ×
10−11 10−11 10−11 10−11
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
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X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 4. SEE cross sections vs proton energy for D-Cache.
sensitive than other tested blocks during protons irradiation. In addition, the working current has not obvious change and no single event latch-up (SEL) event is observed during irradiation. 4. Discussion 4.1. Single event sensitivity for the D-Cache The critical charge (Qcrit) is defined as the minimum charge which is needed to upset the state of latch or memory cell. Moreover, the critical charges of the sequential nodes approximately scale according to. Q crit ≈ Vcc C
ð3Þ
where Vcc equals the power supply voltage, and C denotes the node capacitance [23,25]. Hence, Qcrit is also expected to decrease with the decreasing of technology scaling. Moreover, if the collected charge is equal or larger than Qcrit, an upset is occurred. According to the recent research results, the Qcrit for 32 nm SRAM technology is about 0.2 fC
[24]. Due to the Xilinx Zynq-7010 SoC based on 28 nm CMOS technologies, the Qcrit should be smaller than 0.2 fC. The LET value of 10 MeV protons is 0.355 fC/μm by using SRIM (Stopping Range of Ion in Matter) software, as shown in Table 3. The SRIM includes quick calculations which produce tables of stopping powers, range and straggling distributions for any ion at any energy in any elemental target [27]. It is assumed that charge collection depth equals 1 μm. The sufficient charges caused by low-energy proton direct ionizing could result in single event upsets in D-Cache from 3 to 10 MeV. The stopping power for proton into silicon can be determined with SRIM software, and the known decrease in LET value for low energy protons can be observed from 3 to 10 MeV, as shown in Fig. 8. The decrease trend from 3 to 10 MeV is in accordance with D-Cache curve. It is a possible reason that the D-Cache cross section decreases as the proton energies increases. 4.2. Single event effect sensitivities for the tested blocks except the D-Cache Due to the number of SEE events for the PL, ALU, and FPU are relatively smaller, the statistical error have a great effect on the
Fig. 5. SEE cross sections vs proton energy for PL.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx
5
Table 3 The proton beam LET value caused by direct ionizing mechanism.
Fig. 6. SEE cross sections vs proton energy for ALU.
experimental results. It would be difficult to give a precise mechanism analysis for the other blocks except the D-Cache. Single event effects may have been caused by two factors for the tested blocks, including indirect ionization and direct ionization. On the one hand, because these components are mainly composed of combination logic and sequential logic circuits, such as latch, Flip-Flop circuits. The research results have shown that the Qcrit for logic circuits is dramatically larger than memory bit cell [23–26]. The SEE events may be caused by the indirect ionization in ALU, PL, and FPU blocks. The indirect ionization creates secondary particles (recoils) by the interactions of incident protons with the atomic nuclei of semiconductor devices initiate processes. In general, the nuclear interactions produce some secondary particles or recoils and fragments, including Mg, Al, Na nuclei [28,29]. The main nuclear reactions include the following: Pþ
28
Si→ 4 He þ
25
Pþ
28
Si→ 4 He þ P þ
Pþ
28
Si→ 12 C þ
Pþ
28
Si→214 N þ P:
Mg; 25
Energy (MeV)
LET (fC/μm)
3 5 10
0.866 0.599 0.355
energies below 10 MeV, the nuclear reactions cross section (P + 28Si) increases as the proton energy increases [30]. The trend is in agreement with the testing result curves for blocks under test except D-Cache. On the other hand, the protons reach silicon surface with a range of energies because of the multi-layer metallization and other materials above the active silicon layer. The protons lost a different value of energy through a variety of paths, due to the complex topologies of the metal wires and BEOL materials [31]. Therefore, the protons energy will be decreased to below 3 MeV. The lower energy protons have higher LET values through direct ionization mechanism. Therefore, single event effects in combination logic and sequential logic circuits would be produced by low-energy protons that lost energy in transporting process. The single event effects in PL, FPU, and ALU could be the results of direct and indirect ionization interactions. In addition, single event function interrupt event (SEFI) was detected during irradiation. Table 4 shows the number of SEFI events and distributions in different blocks. The SEFI has a serious impact on the reliability of electronic system and it is hard to determine the underlying cause of these malfunctions. The fault injection experiments performed in software-based fault injection technique. Some reasons for SEFI are listed: the SEU happened in the shift registers that control the address of the control logic; some errors arose in the address register that stores the memory address; some errors caused by SEU in the special register, such as current program status register or program counter; instruction registers were modified by SEU resulting in unknown instruction code or undefined instruction code. The above errors can result in test program being halted, destruction of normal program control flow, and some unknown, unrecognizable state.
Na; 5. Conclusion
16
O þ P; The SEE experiments of Xilinx Zynq-7010 SoC were performed to investigate the SEE susceptibility of different blocks using low-energy protons based on dynamic testing methods. The dynamic cross sections
These recoils may ionize enough charges to cause an upsets depending on their linear energy transfer (LET) values. The LET values of different secondary particles versus energy are shown in Fig. 9. According to the Fig. 6, the LET value is increasing with the energy. In addition, for
Fig. 7. SEE cross sections vs proton energy for FPU.
Fig. 8. SRIM output with proton range and LET value in silicon.
Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014
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X. Du et al. / Microelectronics Reliability xxx (2017) xxx–xxx
Fig. 9. The LET value vs proton energy in different recoils.
Table 4 The SEFI results for different blocks of the SoC under test. Blocks
Proton energy (3 MeV) Number of SEFI events
Proton energy (5 MeV) Number of SEFI events
Proton energy (10 MeV) Number of SEFI events
PL D-Cache ALU FPU
7 21 3 5
9 7 6 7
4 5 3 7
of different blocks in different energies protons were calculated. The experimental results have revealed the PL and D-Cache were more sensitive than the other blocks and easily susceptible to SEE. Moreover, the charge curve of cross sections versus proton energy for D-Cache is different from the other tested blocks. Acknowledgements This work was supported by National Natural Science Foundation of China (grant no. 11175139), the National Natural Science Foundation of China (grant no. 11575138), and the Key Program of the National Natural Science Foundation of China (grant no. 11235008). References [1] S.M. Tony, H. Mohammed, J. Mathew, D.K. Pradhan, Soft-error Induced Systemfailure Rate Analysis in an SoC, Norchip19–20 Nov 2013 (Aalborg, Denmark). [2] P.E. Dodd, L.W. Massengil, Basic mechanisms and modeling of single-event upset in digital microelectronics, IEEE Nucl. Plasma Sci. Soc. 50 (3) (2003) 583. [3] C.S. Dyer, S.N. Clucas, C. Sanderson, A.D. Frydland, R.T. Green, An experimental study of single event effects induced in commercial SRAMs by neutrons and protons from thermal energies to 500 MeV, IEEE Trans. Nucl. Sci. 51 (4) (2004) 2817. [4] C. Claeys, E. Simoen, Radiation Effects in Advanced Semiconductor Materials and Devices, Radiation Environments and Component Selection Strategy, Springer, 2002 1–5.
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Please cite this article as: X. Du, et al., Single event effects sensitivity of low energy proton in Xilinx Zynq-7010 system-on chip, Microelectronics Reliability (2017), http://dx.doi.org/10.1016/j.microrel.2017.02.014