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Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors
Solid-State Electronics 54 (2010) 957–964
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Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors F. Carrara a,*, C.D. Presti b, A. Scuderi c, G. Palmisano a a
Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Università di Catania, Viale A. Doria 6, 95125 Catania, Italy Department of Electrical and Computer Engineering, University of California at San Diego, 9500 Gilman Drive, La Jolla, CA 92093-0407, USA c STMicroelectronics s.r.l., Stradale Primosole 50, 95121 Catania, Italy b
a r t i c l e
i n f o
Article history: Available online 23 May 2010 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Silicon-on-insulator (SOI) CMOS Single-transistor latch-up Large-signal reliability Gate finger length Power amplifier (PA) Power-added efficiency (PAE) RF stress Impact ionization
a b s t r a c t RF power transistors are typically operated at extreme drain voltage and current peaks, which cause severe impact ionization conditions at the channel pinch-off region. On a SOI CMOS technology platform, the resulting large body currents may eventually lead to single transistor latch-up, unless the length of the gate/body finger is properly chosen. In this work, the effect of single-transistor latch-up on the large-signal performance of SOI CMOS RF power transistors is investigated for the first time. Extensive multi-harmonic load–pull measurements have been performed to characterize the resulting current runaway phenomenon and its detrimental effect on the device efficiency. Useful guidelines have been derived to avoid such limitations and a prototype power transistor has been designed accordingly. Thanks to the proposed design criteria, the device achieves latch-up-free operation at the nominal 2-V supply voltage, while exhibiting an excellent 72% power-added efficiency at a 19.5-dBm output power level under 1.9-GHz continuous-wave excitation. Moreover, an experimental study on the gate oxide degradation kinetics under RF stress has been carried out to characterize the long-term device reliability of the adopted SOI CMOS process. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction If compared to a standard bulk CMOS process, SOI CMOS features higher speed and reduced power consumption, because the drain and source capacitances to the body of the transistors are substantially reduced. Since past yield issues have been largely solved by wafer suppliers, SOI CMOS technologies have experienced a remarkable growth, mainly driven by the digital electronics segment. Despite the inherently higher wafer cost is still a limiting factor for the industrial diffusion of SOI, the net impact of the substrate cost on a fully packaged IC is quite small, and it is believed to further decrease in the near future, eventually reaching parity with standard bulk CMOS [1,2]. Recently, SOI CMOS has also drawn the attention of circuit designers as a promising candidate for the implementation of complex RF systems for the increasingly demanding market of mobile communications. In particular, the adoption of a SOI technology platform enables the integration of both complex digital/analogue baseband functions and high-performance RF power blocks onto the same die [3]. Indeed, besides the excellent frequency response of active devices, the use of a high-resistivity substrate beneath the buried oxide (BOX) layer guarantees high-Q integrated inductors * Corresponding author. Tel.: +39 095 7382305; fax: +39 095 330793. E-mail address: [email protected] (F. Carrara). 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.04.036
and transformers as well as excellent cross-talk isolation. Moreover, SOI switches can be designed to handle arbitrarily high offstate voltages by exploiting transistor stacking [4]. All these are crucial features for the implementation of next-generation highpower mixed-signal reconfigurable system architectures. According to these motivations, we decided to investigate the performance of SOI CMOS for RF power applications. While pursuing such goal, we faced a peculiar device limitation which can compromise the SOI transistors’ efficiency during large-signal operation. This gave us the opportunity to perform an in-deep experimental characterization of the phenomenon and to suggest an explaining model, which are the focal topics of this work [5]. The observations reported herein provide relevant physical insight into the high-frequency high-power regime of SOI devices, and the resulting analysis offers useful hints for the RF PA designer. The paper is organized as follows. Section 2 gives an overview of the fabrication process adopted for the present work. In Section 3 extensive experimental results are provided to describe the limitations affecting the transistor large-signal operation and a physical interpretation is proposed to explain the observed behaviour. According to this model, in Section 4 some design guidelines are introduced to achieve safe RF operation. Based on such criteria, a prototype test device is designed and its load–pull power performance is reported. Finally, for the sake of an exhaustive device characterization, the results of an additional study on the
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long-term gate oxide degradation kinetics under RF stress are discussed in Section 5. 2. SOI CMOS technology This work is based on a 0.13-lm partially depleted SOI CMOS technology provided by STMicroelectronics [4–6]. A cross section of the process is schematically depicted in Fig. 1. Transistors are built on a thin 150-nm silicon film on top of a 400-nm BOX layer. Active areas are separated by shallow trench isolation (STI). In order to improve the RF performance, a high-resistivity substrate (>1 kX cm) is used as a carrier. The process features two different oxide thickness options, namely 2 nm and 5 nm, exploited for 1.2V and 2.5-V devices, respectively. Both floating-body (FB) and body-contacted (BC) NMOS and PMOS devices are available. A fmax of 149 GHz and 76 GHz is achieved by FB and BC NMOS transistors, respectively, whereas a fmax of 94 GHz and 71 GHz is attained by FB and BC PMOS transistors, respectively. The process back-end features one poly layer (with cobalt silicide), six damascene-copper metal layers, and an additional top aluminium layer (ALUCAP) to be used on bonding pads. Topmost copper layers and ALUCAP can be shunted to implement high-Q inductors and transformers on the high-resistivity substrate (no patterned ground shield is needed). Poly resistors, metal–insulator–metal (MIM) capacitors, and lateral diodes are also available. 3. Experimental observations and interpretation The large-signal high-frequency performance of the SOI process was characterized by on-wafer load–pull measurements. The adopted test setup is schematically represented in Fig. 2. By means of the load–pull bench, both the source and load impedances can be independently tuned to optimize the RF performance of the device under test, with the aim of exploring its potentials in terms of delivered output power and power-added efficiency (PAE) [7]. Moreover, multi-harmonic tuning capability is available at the de-
Fig. 1. SOI CMOS process schematic cross section.
vice output, i.e., the load impedance at the fundamental, second, and third harmonic frequencies can be optimized for maximum efficiency [8]. Multi-harmonic load tuning is performed by using a triplexer, which allows a parallel connection of three tuners at the output. A 1-mm-perimeter test device was adopted for the load–pull characterization. The thick-gate and BC process options were selected for improved robustness at high power levels. In this technology, the use of a 5-nm gate oxide mandates for a 0.28-lm minimum drawn channel length. The device was excited by a 1.9-GHz single-tone continuous-wave (CW) input signal with a 2-dBm available power. The resulting output power and PAE load–pull contours are reported in Fig. 3a–d at different supply voltage levels. The plots show how the device performance varies as the load impedance at the fundamental frequency covers the Smith chart, while the second and third harmonic load impedances are kept close to the open circuit condition for improved efficiency (Class-E-like operation [9]). Load–pull contours at 1.4 V and 1.7 V (Fig. 3a and b, respectively) demonstrate ordinary device operation with well-behaved power characteristics. As usual for large-signal operation, two different optimal impedances can be detected for a specific supply voltage, one for maximum output power and the other for maximum PAE [7], and a fair trade-off can be chosen by the designer. Nevertheless, load–pull performance begins exhibiting some unexpected problem as the supply voltage is further increased to 2 V, as apparent from Fig. 3c. In particular, the PAE contours are considerably deteriorated, as a sharp efficiency decrease can be detected in the upper left portion of the Smith chart (i.e., at lower load resistances). The PAE collapse is even more evident as the supply voltage is pushed to a 2.3-V level (Fig. 3d). Conversely, it should be noted that the output power contours are less seriously affected. Further insight into the peculiar characteristics of such behaviour can be gained by monitoring the device performance versus input power for a given load impedance. To this aim, the device output power, average collector current, and PAE with a 50-X broadband load are reported in Figs. 4–6 at different supply voltage levels. Once more, the output power curves do not reveal significant misbehaviour, not even at the highest supply voltage of 2.6 V. Nevertheless, Fig. 5 clearly demonstrates that a current runaway occurs as the device is driven beyond a specific input power level. Moreover, such threshold power level gets progressively lower as the supply voltage is increased. For instance, a 8-dBm available input power is needed to cause the current runaway at 2.3 V, while a 2-dBm input is enough to trigger the unwanted phenomenon at 2.6 V. As a consequence of the current runaway, the corresponding PAE plots reveal a dramatic efficiency drop as the device is operated in the high-voltage high-power regime. Such collapse agrees with the observed PAE fall in the load–pull contours of Fig. 3c and d.
Fig. 2. Schematic representation of the on-wafer multi-harmonic load–pull test setup.
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Fig. 3. Output power and PAE load–pull contours at different supply voltage levels (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, Pin(av) = 2 dBm, single-tone CW input). (a) VDD = 1.4 V. (b) VDD = 1.7 V. (c) VDD = 2 V. (d) VDD = 2.3 V.
The large-signal current runaway is a self-sustaining phenomenon, i.e., high average drain current values are still detected even after switching off the RF input. Once current runaway is triggered, the only way to reset the device is pulling the supply (drain) voltage to zero. However, after being reset the device is still able to work properly with substantially unchanged power performance.
Therefore, the observed current runaway is a non-destructive phenomenon. For this reason, its origin cannot be related to gate oxide failure. The frequency spectrum of the output signal was also monitored after inducing the current runaway phenomenon, in order to search for possible device oscillations due to inappropriate
Fig. 4. Output power versus input power with broadband 50-X load (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = –0.23 + j0.57).
Fig. 5. Average drain current versus input power with broadband 50-X load (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57).
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Fig. 6. PAE versus input power with broadband 50-X load (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57).
choice of the output load impedance (i.e., beyond the limit of the load stability circles [10]). Nevertheless, the device exhibits a clean output spectrum even after triggering the current runaway. Therefore, the phenomenon is not caused by any RF instability. According to the reported experimental evidence, the observed current runaway apparently results from the single-transistor latch-up phenomenon, which has been widely described in the past [11,12] with reference to the dc transistor characteristics. Single-transistor latch-up in SOI devices can be illustrated by referring to Fig. 7, which represents a simplified layout and cross section of a SOI BC NMOS transistor. Due to the narrow, thin shape of the body finger, a large parasitic body resistance RBB is formed between the intrinsic body and the body contact (much larger than in bulk CMOS transistors). The body contact should short-out the base-emitter junction of the parasitic npn BJT (see Fig. 8), thus keeping it off. However, if a substantial channel current iCH flows through the MOSFET and a large drain voltage is present at the same time, direct carrier generation (impact ionization) occurs close to the channel pinch-off region due to the high electric field:
iH ¼ ðM 1Þ ðiCH þ iBJT Þ
ð1Þ
where iH is the resulting hole current and M is the drain current multiplication factor. Hole current iH should be collected by the body contact. However, if RBB is large, a substantial fraction of iH will flow through the body-source (base-emitter) junction, thus effectively turning the parasitic BJT on. The resulting collector current
Fig. 8. Single-transistor latch-up in SOI BC NMOS transistors. (a) Parasitic npn bipolar transistor. (b) Equivalent electrical model.
iBJT will eventually increase the drain current, hence triggering a positive feedback which leads to latch-up. 4. Power transistor design and large-signal characterization As well known [12], drain current runaway can be avoided by ensuring that the overall gain of the positive feedback loop is lower than unity:
ðM 1Þ
iBASE b <1 iH F
ð2Þ
where iBASE is the fraction of iH which is drawn by the base of the parasitic BJT and bF is its current gain. Though analytically correct, Eq. (2) is not a friendly tool for the designer. Indeed, in order to be exploited for a latch-up-free transistor design, it requires a complete characterization of the current multiplication factor and the parasitic BJT. As an alternative, a more empirical (though conservative) methodology can be adopted by ensuring that the base-emitter voltage of the BJT is lower than the value needed to turn it on:
v BS < v BSðONÞ ¼ 0:7 V
ð3Þ
Maximum vBS is attained at the transistor region which is farthest from the body contact. Integral calculations [13] give
v BS;max ¼
Fig. 7. Simplified layout and cross section of a SOI BC NMOS transistor.
1 j r BB W 2f 2 H
ð4Þ
where jH is the hole current per unit length, rBB is the specific body resistance (9 kX/lm for the adopted technology), and Wf is the length of the gate/body finger. Hence, device latch-up is effectively avoided through the use of short gate fingers. To determine the maximum allowed value of Wf to comply with (3), jH is to be
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estimated. This can be done by recourse to RF circuit simulations, as explained in the following. As a first step, the device waveforms are to be simulated in the required operating conditions, i.e., with the same source/load impedances and supply voltage as in the specific device application. As an example, the simulated voltage and current waveforms are displayed in Fig. 9a for a 1-mm device operating at a saturated output power level under a 2-V supply voltage with 1.9-GHz input and optimized source/load impedances (simulated load–pull experiment). After that, the capacitive components of the drain current have to be de-embedded, since those parasitic currents are not relevant as far as the stress of the intrinsic device is concerned. Thus, the drain current is re-calculated, knowing the gate and drain voltage waveforms, as it was a static current (quasi-static extrapolation in Fig. 9b). By analyzing the quasi-static waveforms, maximum impact ionization can be estimated by assuming that the worst case corresponds to the peak of the instantaneous power dissipation (Fig. 9c), where both the highvoltage and high-current conditions simultaneously occur. For the reported design example, a drain current of 60 mA at vDS = 2 V must be safely sustained. Finally, from (1) we get
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Fig. 10. Micrograph of the designed power transistor.
Fig. 11. Output power versus input power for the designed power transistor at different supply voltage levels (VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17).
jH ¼ ðM 1Þ
iCH þ iBJT W
ð5Þ
where W is the overall device width. According to (5), a hole current density of 18 lA/lm is estimated,1 having assumed a typical impact ionization factor (M 1) of 0.3 [11,12]. By substituting (5) into (4), we obtain the following condition:
W f < 2:9 lm
ð6Þ
Therefore, a prototype power device with 2.5-lm-long gate fingers was designed and integrated (384 gate fingers for a total channel width of 960 lm). Even shorter gate fingers, although beneficial for latch-up considerations, would substantially clutter interconnections. For easy use in multi-cell modular layouts, gate fingers were arranged orthogonally with respect to main source/drain routing lines, as shown in Fig. 10. Higher metal layers and multiple stacked vias were exploited to reduce extrinsic parasitic series resistances. The large-signal performance of the designed power transistor was characterized by the multi-harmonic load–pull test bench under single-tone 1.9-GHz CW excitation. Load impedance at the fundamental frequency was set for a fair trade-off between output power and efficiency, whereas load impedances at the second and third harmonics were tuned close to the open circuit condition for improved efficiency, as already explained. The corresponding Fig. 9. Simulated voltage and current waveforms at saturated output power level (W = 1 mm, L = 0.28 lm, VDD = 2 V, VGG = 0.45 V, f = 1.9 GHz, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17). (a) Simulated load–pull experiment. (b) Quasi-static extrapolation. (c) Instantaneous power dissipation (vDS iD).
1 Current iBJT has been assumed still negligible at the onset of the phenomenon. Moreover, current iCH has been assumed equal to the simulated drain current (i.e., 60 mA), since the device electrical model adopted for circuit simulations does not account for the current runaway phenomenon.
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output power and PAE characteristics versus input power at different supply voltage levels are reported in Figs. 11 and 12, respectively. At 2 V, the designed power transistor achieved an excellent peak efficiency as high as 72%, while delivering a 19.5dBm output power. The onset of single-transistor latch-up under large-signal operation was also explored by testing the device with increasing supply voltage and unchanged input signal and source/load impedances, as summarized in Fig. 13. Experimental results confirm safe operation at the nominal 2-V supply voltage level, which agrees with the reported design criteria.
5. Device degradation under RF stress As demonstrated in the previous section, proper device design can guarantee efficient and latch-up-safe operation at the nominal 2-V supply voltage. Nevertheless, further investigation is needed to characterize possible gate oxide stress phenomena due to the highvoltage high-current waveforms typical of RF operation (see Fig. 9). This is essential to understand whether the device is experiencing any serious degradation that could lead to failure in the long term. For this reason, a study of the transistor degradation kinetics under RF stress has been performed as well. Using experimental techniques similar to those described in [14], the designed power transistor has been repeatedly stressed at RF, while monitoring the sub-threshold current characteristics between each stress phase, to get useful indicators of device degradation. Indeed, the threshold voltage variation is related to the amount of trapped charge in the oxide [15], whereas the subthreshold slope factor is an indicator of the damage, as traps are created at the Si–Si oxide interface. During the RF stress phase, the transistor was operated under the same load–pull conditions described in Section 4. As regards the dc sampling phase, a semiconductor parameter analyzer was used to measure the VGS–ID characteristics on the fresh device and after each RF stress phase. A best fit algorithm was used to match the exponential region of drain current ID (between 0.1 lA and 100 lA) to the following equation:
ID ¼ ID0 exp Fig. 12. PAE versus input power for the designed power transistor at different supply voltage levels (VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17).
Fig. 13. Onset of device latch-up under large-signal operation at supply voltages higher than the nominal 2-V level (VGG = 0.45 V, f = 1.9 GHz, Pin(av) = 2 dBm, singletone CW input, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17).
V GS V th nV T
ð7Þ
where n is the sub-threshold slope factor (ideality factor), Vth is the threshold voltage, VT is the thermal voltage, and ID0 is a process- and geometry-dependent parameter [16], estimated to be equal to 120 lA in the present case. A small 50-mV drain voltage was purposely employed during the dc sampling phase. Indeed, if a higher VDS were used (higher than a few VT), the sub-threshold current would not have been influenced by the quality of the oxide and/ or interface close to the drain terminal (where damage actually occurs), simply because electrons are confined near the source terminal due to channel pinch-off [14]. Fig. 14 shows the VGS–ID sub-threshold characteristic of one device sample, before and after being stressed at RF for 2000 s, at a 2V power supply. Analysis of the data shows that n shifted from 1.396 to 1.435 (2.3% relative variation), and the threshold voltage decreased by 6.8 mV. Interestingly, the reduction of Vth indicates the generation of positive charge in the oxide, possibly hole injection [15]. On the contrary, similar experiments on bulk CMOS
Fig. 14. Sub-threshold drain current before and after RF stress.
F. Carrara et al. / Solid-State Electronics 54 (2010) 957–964
transistors [14] previously evidenced a Vth increase after RF stress, which was attributed to the trapping of hot electrons. This significant difference between bulk and SOI can be attributed to the fact that efficient hole collection is lacking in SOI transistors, and it is an indirect confirmation of what has been observed in the previous Sections. To investigate the kinetics of transistor degradation, several devices were tested while applying a different supply voltage during the RF stress phase, from 1.4 V through 2.3 V, to control the stress severity (note that a 2.3-V supply actually triggers single-transistor latch-up). A new device was used for each supply voltage value. Each device underwent cumulative RF stress, whose duration started from 0.25 s up to 2000 s. The results of these experiments are shown in Figs. 15–17. The threshold voltage variation DVth = Vth – Vth(0) is plotted against total RF stress time in Fig. 15 on a linear scale, whereas the threshold voltage reduction (i.e., DVth) is shown in Fig. 16 on a logarithmic scale. It is evident that, for a given stress time, the accumulated Vth variation increases with the supply voltage. A closer scrutiny of the data (Fig. 15b) reveals that, during the initial stress steps, the threshold voltage actually increases by a fraction of a mV. However, on the long term, the threshold voltage always decreases. This could be interpreted as an initial trapping of hot electrons, which are compensated and overcome by a more intense trapping of holes. Fig. 16 reveals that the threshold voltage variation (and hence the amount of trapped positive charge) increases with the square root of time [14]. Similar conclusions can be drawn if the sub-threshold slope-factor variation Dn = n n(0) is analyzed. As shown in Fig. 17, the same square-root dependence on time was found in the long term, in all cases except VDD = 2.3 V. When single-transistor latch-up is actually triggered (VDD = 2.3 V), a much larger 5.5-mV Vth reduction is observed in Fig. 15 after just 0.25 s of RF stress. Indeed, in this case the
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Fig. 16. Threshold voltage reduction DVth = Vth(0) Vth versus total RF stress time at different supply voltage levels.
Fig. 17. Sub-threshold slope variation Dn = n n(0) versus total RF stress time at different supply voltage levels.
Fig. 15. Threshold voltage variation DVth = Vth Vth(0) versus total RF stress time at different supply voltage levels. Y-axis expansion of (a) is shown in (b).
observed current runaway phenomenon produces a much larger drain current. Then, the threshold voltage keeps decreasing, up to a 13.47-mV variation after 1024 s, but with a much smaller slope, which indicates a saturation of the hole trapping rate, possibly due to a large amount of positive charge already in the oxide. Signs of saturation can be also observed in the data at VDD = 2.0 V. An estimation of the device operating lifetime can be carried out by exploiting the data reported in Fig. 16. To this purpose, a 200-mV threshold voltage shift can be assumed as a maximum tolerable limit, since RF performance of power amplifiers under saturated operation is relatively insensitive to the Vth shift [18]. Under such assumption, an excellent CW lifetime of around 2500 h is found at 2 V by extrapolating the threshold shift curve as the 0.4-th power of time (according to the above mentioned slope saturation). The operating lifetime can be even longer when realworld operating conditions are considered. Indeed, a parasitic inductance is usually present at the source of integrated power devices (due to bonding wires), which may result in a smaller peak drain voltage compared to on-wafer test conditions. Moreover, wireless communication standards often call for burst transmission with specific duty cycles (e.g., 12.5% for GSM or 50% for Class-12 GPRS) rather than CW operation, which extend the power device lifetime accordingly.
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6. Conclusions In this work, the implications of single-transistor latch-up on the large-signal high-frequency performance of SOI CMOS RF power transistor have been reported for the first time. The phenomenon has been characterized by means of on-wafer multi-harmonic load–pull measurements at 1.9 GHz and proper design criteria have been derived to achieve efficient and latch-up-safe operation at the nominal supply voltage. Additionally, an experimental study on the gate oxide degradation kinetics under RF stress has been performed to characterize the long-term device reliability of the adopted SOI CMOS technology. Besides providing useful design guidelines for the implementation of SOI transistors, the disclosed results also set a new benchmark for the state-of-the-art of SOI RF power amplifiers. Indeed, previously reported works [3,17] make use of high-voltage LDMOS devices for the implementation of power modules, whereas in the present work a record power performance (19.5-dBm output power and 72% PAE at 2 V and 1.9 GHz) is drawn from standard NMOS transistors. Acknowledgments The authors would like to thank B. Rauber, STMicroelectronics, Crolles, France, for device processing, and A. Castorina, STMicroelectronics, Catania, Italy, for valuable help during measurements. References [1] DeJule R. SOI technology goes mainstream. Semiconductor International; March 2009.. [2] SOI Industry Consortium. .
[3] Tombak A, Baeten RJ, Jorgenson JD, Dening DC. Integration of a cellular handset power amplifier and a DC/DC converter in a silicon-on-insulator (SOI) technology. In: IEEE RFIC Symp Dig; 2008. p. 413–6. [4] Scuderi A, Presti CD, Carrara F, Rauber B, Palmisano G. A stage-bypass SOICMOS switch for multi-mode multi-band applications. In: IEEE RFIC Symp. Dig.; 2008. p. 325–8. [5] Carrara F, Presti CD, Scuderi A, Palmisano G. Power transistor design guidelines and RF load–pull characterization of a 0.13-lm SOI CMOS technology. In: Proc. IEEE European Solid-State Device Research Conf. (ESSDERC 2009), Athens, Greece; September 2009. p. 444–7. [6] Gianesello F, Gloria D, Boret S, Bon O, Touret P, Pastore C, et al. High resistivity SOI CMOS technology for multi-standard RF frontends. In: Proc IEEE International SOI Conf, Octomber 2008. p. 77–8. [7] Cripps SC. RF power amplifiers for wireless communications. 2nd ed. Boston (MA), USA: Arthech House Inc.; 2006. [8] Berini P, Desgagné M, Ghannouchi FM, Bosisio RG. An experimental study of the effects of harmonic loading on microwave MESFET oscillators and amplifiers. IEEE Trans Microwave Theory Technol 1994;42(6):943–50. [9] Sokal NO, Sokal AD. Class E – a new class of high-efficiency tuned single-ended switching power amplifiers. IEEE J Solid State Circ 1975;SC-10:168–76. [10] Gonzalez G. Microwave transistor amplifiers: analysis and design. 2nd ed. Upper Saddle River (NJ), USA: Prentice Hall Inc.; 1997. [11] Young KK, Barnes JA. Avalanche-induced drain-source breakdown in siliconon-insulator n-MOSFET’s. IEEE Trans Electron Dev 1988;35(4):426–31. [12] Suh D, Fossum JG. The effect of body resistance on the breakdown characteristics of SOI MOSFET’s. IEEE Trans Electron Dev 1994;41(6):1063–6. [13] Kuehne SC, Chan ABY, Nguyen CT, Wong SS. SOI MOSFET with buried body strap by wafer bonding. IEEE Trans Electron Dev 1998;45(5):1084–91. [14] Presti CD, Carrara F, Scuderi A, Lombardo S, Palmisano G. Degradation mechanisms in CMOS power amplifiers subject to radio-frequency stress and comparison to the dc case. In: Proc IEEE Int Reliability Physics Symp (IRPS 2007), Phoenix AZ, USA; April 2007. p. 86–92. [15] Lombardo S, Stathis JH, Linder BP, Pey KL, Palumbo F, Tung CH. Dielectric breakdown mechanisms in gate oxides. J Appl Phys 2005;98(121,301). [16] Muller RS, Kamins TI, Ko PK. Device electronics for integrated circuits. 3rd ed. New York, USA: John Wiley & Sons Inc.; 2003. [17] Tan Y, Kumar M, Sin JKO, Shi L, Lau J. A 900-MHz fully integrated SOI power amplifier for single-chip wireless transceiver applications. IEEE J Solid State Circ 2000;35(10):1481–6. [18] Carrara F, Presti CD, Scuderi A, Santagati C, Palmisano G. A methodology for fast VSWR protection implemented in a monolithic 3-W 55%-PAE RF CMOS power amplifier. IEEE J Solid State Circ 2008;43:2057–66.
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Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors F. Carrara a,*, C.D. Presti b, A. Scuderi c, G. Palmisano a a
Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Università di Catania, Viale A. Doria 6, 95125 Catania, Italy Department of Electrical and Computer Engineering, University of California at San Diego, 9500 Gilman Drive, La Jolla, CA 92093-0407, USA c STMicroelectronics s.r.l., Stradale Primosole 50, 95121 Catania, Italy b
a r t i c l e
i n f o
Article history: Available online 23 May 2010 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Silicon-on-insulator (SOI) CMOS Single-transistor latch-up Large-signal reliability Gate finger length Power amplifier (PA) Power-added efficiency (PAE) RF stress Impact ionization
a b s t r a c t RF power transistors are typically operated at extreme drain voltage and current peaks, which cause severe impact ionization conditions at the channel pinch-off region. On a SOI CMOS technology platform, the resulting large body currents may eventually lead to single transistor latch-up, unless the length of the gate/body finger is properly chosen. In this work, the effect of single-transistor latch-up on the large-signal performance of SOI CMOS RF power transistors is investigated for the first time. Extensive multi-harmonic load–pull measurements have been performed to characterize the resulting current runaway phenomenon and its detrimental effect on the device efficiency. Useful guidelines have been derived to avoid such limitations and a prototype power transistor has been designed accordingly. Thanks to the proposed design criteria, the device achieves latch-up-free operation at the nominal 2-V supply voltage, while exhibiting an excellent 72% power-added efficiency at a 19.5-dBm output power level under 1.9-GHz continuous-wave excitation. Moreover, an experimental study on the gate oxide degradation kinetics under RF stress has been carried out to characterize the long-term device reliability of the adopted SOI CMOS process. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction If compared to a standard bulk CMOS process, SOI CMOS features higher speed and reduced power consumption, because the drain and source capacitances to the body of the transistors are substantially reduced. Since past yield issues have been largely solved by wafer suppliers, SOI CMOS technologies have experienced a remarkable growth, mainly driven by the digital electronics segment. Despite the inherently higher wafer cost is still a limiting factor for the industrial diffusion of SOI, the net impact of the substrate cost on a fully packaged IC is quite small, and it is believed to further decrease in the near future, eventually reaching parity with standard bulk CMOS [1,2]. Recently, SOI CMOS has also drawn the attention of circuit designers as a promising candidate for the implementation of complex RF systems for the increasingly demanding market of mobile communications. In particular, the adoption of a SOI technology platform enables the integration of both complex digital/analogue baseband functions and high-performance RF power blocks onto the same die [3]. Indeed, besides the excellent frequency response of active devices, the use of a high-resistivity substrate beneath the buried oxide (BOX) layer guarantees high-Q integrated inductors * Corresponding author. Tel.: +39 095 7382305; fax: +39 095 330793. E-mail address: [email protected] (F. Carrara). 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.04.036
and transformers as well as excellent cross-talk isolation. Moreover, SOI switches can be designed to handle arbitrarily high offstate voltages by exploiting transistor stacking [4]. All these are crucial features for the implementation of next-generation highpower mixed-signal reconfigurable system architectures. According to these motivations, we decided to investigate the performance of SOI CMOS for RF power applications. While pursuing such goal, we faced a peculiar device limitation which can compromise the SOI transistors’ efficiency during large-signal operation. This gave us the opportunity to perform an in-deep experimental characterization of the phenomenon and to suggest an explaining model, which are the focal topics of this work [5]. The observations reported herein provide relevant physical insight into the high-frequency high-power regime of SOI devices, and the resulting analysis offers useful hints for the RF PA designer. The paper is organized as follows. Section 2 gives an overview of the fabrication process adopted for the present work. In Section 3 extensive experimental results are provided to describe the limitations affecting the transistor large-signal operation and a physical interpretation is proposed to explain the observed behaviour. According to this model, in Section 4 some design guidelines are introduced to achieve safe RF operation. Based on such criteria, a prototype test device is designed and its load–pull power performance is reported. Finally, for the sake of an exhaustive device characterization, the results of an additional study on the
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long-term gate oxide degradation kinetics under RF stress are discussed in Section 5. 2. SOI CMOS technology This work is based on a 0.13-lm partially depleted SOI CMOS technology provided by STMicroelectronics [4–6]. A cross section of the process is schematically depicted in Fig. 1. Transistors are built on a thin 150-nm silicon film on top of a 400-nm BOX layer. Active areas are separated by shallow trench isolation (STI). In order to improve the RF performance, a high-resistivity substrate (>1 kX cm) is used as a carrier. The process features two different oxide thickness options, namely 2 nm and 5 nm, exploited for 1.2V and 2.5-V devices, respectively. Both floating-body (FB) and body-contacted (BC) NMOS and PMOS devices are available. A fmax of 149 GHz and 76 GHz is achieved by FB and BC NMOS transistors, respectively, whereas a fmax of 94 GHz and 71 GHz is attained by FB and BC PMOS transistors, respectively. The process back-end features one poly layer (with cobalt silicide), six damascene-copper metal layers, and an additional top aluminium layer (ALUCAP) to be used on bonding pads. Topmost copper layers and ALUCAP can be shunted to implement high-Q inductors and transformers on the high-resistivity substrate (no patterned ground shield is needed). Poly resistors, metal–insulator–metal (MIM) capacitors, and lateral diodes are also available. 3. Experimental observations and interpretation The large-signal high-frequency performance of the SOI process was characterized by on-wafer load–pull measurements. The adopted test setup is schematically represented in Fig. 2. By means of the load–pull bench, both the source and load impedances can be independently tuned to optimize the RF performance of the device under test, with the aim of exploring its potentials in terms of delivered output power and power-added efficiency (PAE) [7]. Moreover, multi-harmonic tuning capability is available at the de-
Fig. 1. SOI CMOS process schematic cross section.
vice output, i.e., the load impedance at the fundamental, second, and third harmonic frequencies can be optimized for maximum efficiency [8]. Multi-harmonic load tuning is performed by using a triplexer, which allows a parallel connection of three tuners at the output. A 1-mm-perimeter test device was adopted for the load–pull characterization. The thick-gate and BC process options were selected for improved robustness at high power levels. In this technology, the use of a 5-nm gate oxide mandates for a 0.28-lm minimum drawn channel length. The device was excited by a 1.9-GHz single-tone continuous-wave (CW) input signal with a 2-dBm available power. The resulting output power and PAE load–pull contours are reported in Fig. 3a–d at different supply voltage levels. The plots show how the device performance varies as the load impedance at the fundamental frequency covers the Smith chart, while the second and third harmonic load impedances are kept close to the open circuit condition for improved efficiency (Class-E-like operation [9]). Load–pull contours at 1.4 V and 1.7 V (Fig. 3a and b, respectively) demonstrate ordinary device operation with well-behaved power characteristics. As usual for large-signal operation, two different optimal impedances can be detected for a specific supply voltage, one for maximum output power and the other for maximum PAE [7], and a fair trade-off can be chosen by the designer. Nevertheless, load–pull performance begins exhibiting some unexpected problem as the supply voltage is further increased to 2 V, as apparent from Fig. 3c. In particular, the PAE contours are considerably deteriorated, as a sharp efficiency decrease can be detected in the upper left portion of the Smith chart (i.e., at lower load resistances). The PAE collapse is even more evident as the supply voltage is pushed to a 2.3-V level (Fig. 3d). Conversely, it should be noted that the output power contours are less seriously affected. Further insight into the peculiar characteristics of such behaviour can be gained by monitoring the device performance versus input power for a given load impedance. To this aim, the device output power, average collector current, and PAE with a 50-X broadband load are reported in Figs. 4–6 at different supply voltage levels. Once more, the output power curves do not reveal significant misbehaviour, not even at the highest supply voltage of 2.6 V. Nevertheless, Fig. 5 clearly demonstrates that a current runaway occurs as the device is driven beyond a specific input power level. Moreover, such threshold power level gets progressively lower as the supply voltage is increased. For instance, a 8-dBm available input power is needed to cause the current runaway at 2.3 V, while a 2-dBm input is enough to trigger the unwanted phenomenon at 2.6 V. As a consequence of the current runaway, the corresponding PAE plots reveal a dramatic efficiency drop as the device is operated in the high-voltage high-power regime. Such collapse agrees with the observed PAE fall in the load–pull contours of Fig. 3c and d.
Fig. 2. Schematic representation of the on-wafer multi-harmonic load–pull test setup.
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Fig. 3. Output power and PAE load–pull contours at different supply voltage levels (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, Pin(av) = 2 dBm, single-tone CW input). (a) VDD = 1.4 V. (b) VDD = 1.7 V. (c) VDD = 2 V. (d) VDD = 2.3 V.
The large-signal current runaway is a self-sustaining phenomenon, i.e., high average drain current values are still detected even after switching off the RF input. Once current runaway is triggered, the only way to reset the device is pulling the supply (drain) voltage to zero. However, after being reset the device is still able to work properly with substantially unchanged power performance.
Therefore, the observed current runaway is a non-destructive phenomenon. For this reason, its origin cannot be related to gate oxide failure. The frequency spectrum of the output signal was also monitored after inducing the current runaway phenomenon, in order to search for possible device oscillations due to inappropriate
Fig. 4. Output power versus input power with broadband 50-X load (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = –0.23 + j0.57).
Fig. 5. Average drain current versus input power with broadband 50-X load (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57).
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Fig. 6. PAE versus input power with broadband 50-X load (W = 1 mm, L = 0.28 lm, VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57).
choice of the output load impedance (i.e., beyond the limit of the load stability circles [10]). Nevertheless, the device exhibits a clean output spectrum even after triggering the current runaway. Therefore, the phenomenon is not caused by any RF instability. According to the reported experimental evidence, the observed current runaway apparently results from the single-transistor latch-up phenomenon, which has been widely described in the past [11,12] with reference to the dc transistor characteristics. Single-transistor latch-up in SOI devices can be illustrated by referring to Fig. 7, which represents a simplified layout and cross section of a SOI BC NMOS transistor. Due to the narrow, thin shape of the body finger, a large parasitic body resistance RBB is formed between the intrinsic body and the body contact (much larger than in bulk CMOS transistors). The body contact should short-out the base-emitter junction of the parasitic npn BJT (see Fig. 8), thus keeping it off. However, if a substantial channel current iCH flows through the MOSFET and a large drain voltage is present at the same time, direct carrier generation (impact ionization) occurs close to the channel pinch-off region due to the high electric field:
iH ¼ ðM 1Þ ðiCH þ iBJT Þ
ð1Þ
where iH is the resulting hole current and M is the drain current multiplication factor. Hole current iH should be collected by the body contact. However, if RBB is large, a substantial fraction of iH will flow through the body-source (base-emitter) junction, thus effectively turning the parasitic BJT on. The resulting collector current
Fig. 8. Single-transistor latch-up in SOI BC NMOS transistors. (a) Parasitic npn bipolar transistor. (b) Equivalent electrical model.
iBJT will eventually increase the drain current, hence triggering a positive feedback which leads to latch-up. 4. Power transistor design and large-signal characterization As well known [12], drain current runaway can be avoided by ensuring that the overall gain of the positive feedback loop is lower than unity:
ðM 1Þ
iBASE b <1 iH F
ð2Þ
where iBASE is the fraction of iH which is drawn by the base of the parasitic BJT and bF is its current gain. Though analytically correct, Eq. (2) is not a friendly tool for the designer. Indeed, in order to be exploited for a latch-up-free transistor design, it requires a complete characterization of the current multiplication factor and the parasitic BJT. As an alternative, a more empirical (though conservative) methodology can be adopted by ensuring that the base-emitter voltage of the BJT is lower than the value needed to turn it on:
v BS < v BSðONÞ ¼ 0:7 V
ð3Þ
Maximum vBS is attained at the transistor region which is farthest from the body contact. Integral calculations [13] give
v BS;max ¼
Fig. 7. Simplified layout and cross section of a SOI BC NMOS transistor.
1 j r BB W 2f 2 H
ð4Þ
where jH is the hole current per unit length, rBB is the specific body resistance (9 kX/lm for the adopted technology), and Wf is the length of the gate/body finger. Hence, device latch-up is effectively avoided through the use of short gate fingers. To determine the maximum allowed value of Wf to comply with (3), jH is to be
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estimated. This can be done by recourse to RF circuit simulations, as explained in the following. As a first step, the device waveforms are to be simulated in the required operating conditions, i.e., with the same source/load impedances and supply voltage as in the specific device application. As an example, the simulated voltage and current waveforms are displayed in Fig. 9a for a 1-mm device operating at a saturated output power level under a 2-V supply voltage with 1.9-GHz input and optimized source/load impedances (simulated load–pull experiment). After that, the capacitive components of the drain current have to be de-embedded, since those parasitic currents are not relevant as far as the stress of the intrinsic device is concerned. Thus, the drain current is re-calculated, knowing the gate and drain voltage waveforms, as it was a static current (quasi-static extrapolation in Fig. 9b). By analyzing the quasi-static waveforms, maximum impact ionization can be estimated by assuming that the worst case corresponds to the peak of the instantaneous power dissipation (Fig. 9c), where both the highvoltage and high-current conditions simultaneously occur. For the reported design example, a drain current of 60 mA at vDS = 2 V must be safely sustained. Finally, from (1) we get
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Fig. 10. Micrograph of the designed power transistor.
Fig. 11. Output power versus input power for the designed power transistor at different supply voltage levels (VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17).
jH ¼ ðM 1Þ
iCH þ iBJT W
ð5Þ
where W is the overall device width. According to (5), a hole current density of 18 lA/lm is estimated,1 having assumed a typical impact ionization factor (M 1) of 0.3 [11,12]. By substituting (5) into (4), we obtain the following condition:
W f < 2:9 lm
ð6Þ
Therefore, a prototype power device with 2.5-lm-long gate fingers was designed and integrated (384 gate fingers for a total channel width of 960 lm). Even shorter gate fingers, although beneficial for latch-up considerations, would substantially clutter interconnections. For easy use in multi-cell modular layouts, gate fingers were arranged orthogonally with respect to main source/drain routing lines, as shown in Fig. 10. Higher metal layers and multiple stacked vias were exploited to reduce extrinsic parasitic series resistances. The large-signal performance of the designed power transistor was characterized by the multi-harmonic load–pull test bench under single-tone 1.9-GHz CW excitation. Load impedance at the fundamental frequency was set for a fair trade-off between output power and efficiency, whereas load impedances at the second and third harmonics were tuned close to the open circuit condition for improved efficiency, as already explained. The corresponding Fig. 9. Simulated voltage and current waveforms at saturated output power level (W = 1 mm, L = 0.28 lm, VDD = 2 V, VGG = 0.45 V, f = 1.9 GHz, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17). (a) Simulated load–pull experiment. (b) Quasi-static extrapolation. (c) Instantaneous power dissipation (vDS iD).
1 Current iBJT has been assumed still negligible at the onset of the phenomenon. Moreover, current iCH has been assumed equal to the simulated drain current (i.e., 60 mA), since the device electrical model adopted for circuit simulations does not account for the current runaway phenomenon.
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output power and PAE characteristics versus input power at different supply voltage levels are reported in Figs. 11 and 12, respectively. At 2 V, the designed power transistor achieved an excellent peak efficiency as high as 72%, while delivering a 19.5dBm output power. The onset of single-transistor latch-up under large-signal operation was also explored by testing the device with increasing supply voltage and unchanged input signal and source/load impedances, as summarized in Fig. 13. Experimental results confirm safe operation at the nominal 2-V supply voltage level, which agrees with the reported design criteria.
5. Device degradation under RF stress As demonstrated in the previous section, proper device design can guarantee efficient and latch-up-safe operation at the nominal 2-V supply voltage. Nevertheless, further investigation is needed to characterize possible gate oxide stress phenomena due to the highvoltage high-current waveforms typical of RF operation (see Fig. 9). This is essential to understand whether the device is experiencing any serious degradation that could lead to failure in the long term. For this reason, a study of the transistor degradation kinetics under RF stress has been performed as well. Using experimental techniques similar to those described in [14], the designed power transistor has been repeatedly stressed at RF, while monitoring the sub-threshold current characteristics between each stress phase, to get useful indicators of device degradation. Indeed, the threshold voltage variation is related to the amount of trapped charge in the oxide [15], whereas the subthreshold slope factor is an indicator of the damage, as traps are created at the Si–Si oxide interface. During the RF stress phase, the transistor was operated under the same load–pull conditions described in Section 4. As regards the dc sampling phase, a semiconductor parameter analyzer was used to measure the VGS–ID characteristics on the fresh device and after each RF stress phase. A best fit algorithm was used to match the exponential region of drain current ID (between 0.1 lA and 100 lA) to the following equation:
ID ¼ ID0 exp Fig. 12. PAE versus input power for the designed power transistor at different supply voltage levels (VGG = 0.45 V, f = 1.9 GHz, single-tone CW input, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17).
Fig. 13. Onset of device latch-up under large-signal operation at supply voltages higher than the nominal 2-V level (VGG = 0.45 V, f = 1.9 GHz, Pin(av) = 2 dBm, singletone CW input, CS = 0.23 + j0.57, CL1 = 0.38 + j0.42, CL2 = 0.72 j0.36, CL3 = 0.81 j0.17).
V GS V th nV T
ð7Þ
where n is the sub-threshold slope factor (ideality factor), Vth is the threshold voltage, VT is the thermal voltage, and ID0 is a process- and geometry-dependent parameter [16], estimated to be equal to 120 lA in the present case. A small 50-mV drain voltage was purposely employed during the dc sampling phase. Indeed, if a higher VDS were used (higher than a few VT), the sub-threshold current would not have been influenced by the quality of the oxide and/ or interface close to the drain terminal (where damage actually occurs), simply because electrons are confined near the source terminal due to channel pinch-off [14]. Fig. 14 shows the VGS–ID sub-threshold characteristic of one device sample, before and after being stressed at RF for 2000 s, at a 2V power supply. Analysis of the data shows that n shifted from 1.396 to 1.435 (2.3% relative variation), and the threshold voltage decreased by 6.8 mV. Interestingly, the reduction of Vth indicates the generation of positive charge in the oxide, possibly hole injection [15]. On the contrary, similar experiments on bulk CMOS
Fig. 14. Sub-threshold drain current before and after RF stress.
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transistors [14] previously evidenced a Vth increase after RF stress, which was attributed to the trapping of hot electrons. This significant difference between bulk and SOI can be attributed to the fact that efficient hole collection is lacking in SOI transistors, and it is an indirect confirmation of what has been observed in the previous Sections. To investigate the kinetics of transistor degradation, several devices were tested while applying a different supply voltage during the RF stress phase, from 1.4 V through 2.3 V, to control the stress severity (note that a 2.3-V supply actually triggers single-transistor latch-up). A new device was used for each supply voltage value. Each device underwent cumulative RF stress, whose duration started from 0.25 s up to 2000 s. The results of these experiments are shown in Figs. 15–17. The threshold voltage variation DVth = Vth – Vth(0) is plotted against total RF stress time in Fig. 15 on a linear scale, whereas the threshold voltage reduction (i.e., DVth) is shown in Fig. 16 on a logarithmic scale. It is evident that, for a given stress time, the accumulated Vth variation increases with the supply voltage. A closer scrutiny of the data (Fig. 15b) reveals that, during the initial stress steps, the threshold voltage actually increases by a fraction of a mV. However, on the long term, the threshold voltage always decreases. This could be interpreted as an initial trapping of hot electrons, which are compensated and overcome by a more intense trapping of holes. Fig. 16 reveals that the threshold voltage variation (and hence the amount of trapped positive charge) increases with the square root of time [14]. Similar conclusions can be drawn if the sub-threshold slope-factor variation Dn = n n(0) is analyzed. As shown in Fig. 17, the same square-root dependence on time was found in the long term, in all cases except VDD = 2.3 V. When single-transistor latch-up is actually triggered (VDD = 2.3 V), a much larger 5.5-mV Vth reduction is observed in Fig. 15 after just 0.25 s of RF stress. Indeed, in this case the
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Fig. 16. Threshold voltage reduction DVth = Vth(0) Vth versus total RF stress time at different supply voltage levels.
Fig. 17. Sub-threshold slope variation Dn = n n(0) versus total RF stress time at different supply voltage levels.
Fig. 15. Threshold voltage variation DVth = Vth Vth(0) versus total RF stress time at different supply voltage levels. Y-axis expansion of (a) is shown in (b).
observed current runaway phenomenon produces a much larger drain current. Then, the threshold voltage keeps decreasing, up to a 13.47-mV variation after 1024 s, but with a much smaller slope, which indicates a saturation of the hole trapping rate, possibly due to a large amount of positive charge already in the oxide. Signs of saturation can be also observed in the data at VDD = 2.0 V. An estimation of the device operating lifetime can be carried out by exploiting the data reported in Fig. 16. To this purpose, a 200-mV threshold voltage shift can be assumed as a maximum tolerable limit, since RF performance of power amplifiers under saturated operation is relatively insensitive to the Vth shift [18]. Under such assumption, an excellent CW lifetime of around 2500 h is found at 2 V by extrapolating the threshold shift curve as the 0.4-th power of time (according to the above mentioned slope saturation). The operating lifetime can be even longer when realworld operating conditions are considered. Indeed, a parasitic inductance is usually present at the source of integrated power devices (due to bonding wires), which may result in a smaller peak drain voltage compared to on-wafer test conditions. Moreover, wireless communication standards often call for burst transmission with specific duty cycles (e.g., 12.5% for GSM or 50% for Class-12 GPRS) rather than CW operation, which extend the power device lifetime accordingly.
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6. Conclusions In this work, the implications of single-transistor latch-up on the large-signal high-frequency performance of SOI CMOS RF power transistor have been reported for the first time. The phenomenon has been characterized by means of on-wafer multi-harmonic load–pull measurements at 1.9 GHz and proper design criteria have been derived to achieve efficient and latch-up-safe operation at the nominal supply voltage. Additionally, an experimental study on the gate oxide degradation kinetics under RF stress has been performed to characterize the long-term device reliability of the adopted SOI CMOS technology. Besides providing useful design guidelines for the implementation of SOI transistors, the disclosed results also set a new benchmark for the state-of-the-art of SOI RF power amplifiers. Indeed, previously reported works [3,17] make use of high-voltage LDMOS devices for the implementation of power modules, whereas in the present work a record power performance (19.5-dBm output power and 72% PAE at 2 V and 1.9 GHz) is drawn from standard NMOS transistors. Acknowledgments The authors would like to thank B. Rauber, STMicroelectronics, Crolles, France, for device processing, and A. Castorina, STMicroelectronics, Catania, Italy, for valuable help during measurements. References [1] DeJule R. SOI technology goes mainstream. Semiconductor International; March 2009.
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