series-output bridge-based buck dc–dc converters

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Journal of the Franklin Institute 349 (2012) 260–283 www.elsevier.com/locate/jfranklin

Small-signal modelling of current-programmed N-connected parallel-input/series-output bridge-based buck dc–dc converters$ M.R.D. Al-Mothafarn Electrical Engineering Department, Jordan University of Science and Technology, P.O. Box 3030, Irbid 22110, Jordan Received 7 May 2009; received in revised form 26 October 2011; accepted 27 October 2011 Available online 7 November 2011

Abstract A procedure is established for the small-signal modelling of n-connected current-programmed parallelinput/series-output pulse-width modulated bridge-based buck dc–dc converters operating in the continuous-current conduction mode. State-space averaging is used to represent the power stage while current-mode control is modelled using a modified new continuous-time technique. Approximate analytical expressions of the major small-signal transfer functions that include the number of modules as a variable are proposed. PSpice simulations are carried out to validate the analysis. & 2011 The Franklin Institute. Published by Elsevier Ltd. All rights reserved.

1. Introduction The control of switching dc–dc converters has been a subject of great research interest for many years. Various analogue and digital control techniques with variable degree of complexity have been used to regulate this type of converters. Analogue linear pulse-width modulation (PWM) technique is the traditional switching control method to drive the dc–dc converter power semiconductor devices. PWM converters are usually operated under voltage-mode control (VMC) or current-mode control (CMC). In both schemes, closed-loop control is typically achieved by designing linear compensated controllers; the $

This paper has not been presented at any conference and it is not currently under consideration by another journal. n Tel.: þ962 2 7201000x22645; fax: þ962 2 7201074. E-mail address: [email protected] 0016-0032/$32.00 & 2011 The Franklin Institute. Published by Elsevier Ltd. All rights reserved. doi:10.1016/j.jfranklin.2011.10.019

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control design is dominantly carried out using small-signal models locally linearized around a specific operating point. To improve the dynamic performance of dc–dc converters, several analogue nonlinear and hybrid (linear/nonlinear) controllers have been proposed. These controllers are known to be more robust and react faster to transient conditions than their linear counterparts. Examples of such controllers are: sliding-mode [1], passivity [2], hysteretic [3], fuzzy logic [4], sliding modeþproportional integral (PI) [5], and nonlinear CMC [6], to name just a few. Research efforts have also been extended to the use of digital control techniques for dc–dc converters (for example see the works in [7,8]). Digital control offers many advantages over analogue control such as reprogrammability, better noise immunity, and low susceptibility to environmental factors. Digital control is also well suited for hybrid controllers which possess the fast reaction of nonlinear control during transients and the precision of linear control during steady state [8]. Refs. [1–8] only represent a sample of published articles related to advanced control techniques for dc–dc converters, and would be useful pointers to other publications in the field. Although various analogue and digital controllers based on nonlinear techniques have been employed for the control of dc–dc converters, the conventional small-signal analysis based on linearized models is still needed by many researchers and power supply designers to assess the local stability and to gain sufficient insight into the design of new dc–dc converter topologies. It is also useful for the preliminary investigation of the dynamics of complex systems that is comprised of several interconnected subsystems like the one treated in the following sections of this paper. The continued need for linearized small-signal models is manifested in many recent publications, for example the works in [9–11]. Several methodologies have been employed to model switching dc–dc converters such as bond graph [2,12], switching flow graph [13], and averaging techniques [14–16]. The most popular approach for constructing small-signal models of these converters is based on averaging methods. Whether the dc–dc converter is operated under VMC or CMC, averaging rely on two prevalent approaches for power stage modelling: The first is the state-space algebraic approach which is based on the famous state-space averaging method [14]; and the second is the circuit-oriented approach which depends on either circuit averaging [15], or the PWM switch averaged model [16]. With the circuit-oriented approach, switching elements are replaced by controlled current and voltage sources. It requires less mathematical manipulations than the algebraic one, and is more suitable for implementation using a circuit analysis package [17,18]. In addition to the power-stage model, CMC converters require a CMC-stage law to be included in the development of the small-signal model. This can be done either algebraically, by augmenting the power-stage matrices, or as a current-sensing network interfaced with the power-stage model. A popular CMC scheme for PWM converters is the peak CMC [19,20] due to its fast response, accuracy and overload protection [21]. Since its foundation a considerable number of small-signal models have been proposed to study the dynamics of peak CMC, many of which have been reviewed in [22,23]. The most accurate models are the ones that include the sampling effect of the current loop in their structure, and follow the modelling procedure of either the new continuous-time (NCT) technique [24] or the unified modelling (UM) approach [25]. Comparisons of the NCT and the UM techniques were reported in [26–29,22] with slight modification proposed in [28] to the NCT model prediction of the CMC converter audiosusceptibility.

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Although previous research has been focused on the single-module dc–dc converters, averaged and small-signal modelling techniques have also been employed to study the dynamics of VMC and CMC multimodule PWM dc–dc converters [30–40,27]. However because of the complexity of these converters obtaining analytical expressions of the smallsignal transfer functions that include the number of modules as a variable was limited to control schemes where a reduced-order (RO) or equivalent circuit model of the modular converter is feasible. An exception is a recent work in [40] where full-order models, based on the state-space algebraic approach, have been proposed to derive the control-toinductor current transfer functions of VMC parallel-input/parallel-output buck/boost dc–dc converters. The authors of [40] proved that their proposed models are more accurate than RO models in predicting the damping effect on each power stage from the other stages of the modular converter. With the growing interest in the more complex CMC modular dc–dc converters, there is a need to establish a systematic approach for the small-signal modelling of these converters capable of producing full-order models that give the designer more insight into the system behaviour. The work presented in the following sections is a step towards achieving this objective. The procedure we propose is based on the state-space algebraic approach for modelling the converter power stage [14], and uses a modified NCT technique [24,28] to model the CMC stage of each module. The converter that will be considered has the parallel-input series-output (PISO) architecture of Fig. 1, where the inputs of (n) identical full-bridge-based buck modules are connected in parallel and outputs in series to share the load requirements. Each module has its own current and voltage feedback loops for increased system reliability. A PISO converter is chosen because most of the published

Fig. 1. Schematic diagram of the PISO modular dc–dc converter.

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work on modular converters has been geared to the parallel-output architecture [31–34,37,38,40]. PISO converters are very desirable for applications that require the conversion of a low input dc voltage into a higher one such as photovoltaic systems, fuel-cell systems, and highvoltage dc power supplies [30,41]. As with other modular converters, the PISO architecture offers several advantages over the single-unit converter; these include the reduction of voltage and current stresses on the semiconductor devices, ease of expandability of output power, and the possibility of reducing the load voltage ripple by introducing a suitable phase shift between the constituent modules. Few articles have been published on the small-signal modelling of PISO systems [30,27,35,39]. The work presented in [30] studied the stability of a CMC buck-derived PISO converter with a control scheme that consists of an independent current feedback loop for each module, and a common output-voltage feedback circuit. An equivalent-circuit approach was used to obtain a RO small-signal model for the converter, thus allowing the analysis of a multimodule converter to be similar to that of a single module. However, the sampling effect of the current loop was not included in the derivation of the model and issues like the role of external compensating ramp, the effect of varying the number of modules on the current-loop gain, the audiosusceptibility and the output impedance of a converter module were not addressed. The work in [27] has concentrated on comparing two widely used small-signal modelling techniques for CMC [24,25] taking a two-module buck-derived PISO converter as an example. The effect of varying the number of converter modules was not addressed. In [35,39] state-space-based small-signal models are developed for modular CMC boost and buck-boost derived PISO systems that have the control scheme of Fig. 1. The effect of varying the number of modules on the small-signal transfer functions is studied numerically using Matlab. There was, however, no attempt to obtain explicit analytical expressions for these functions or to verify the small-signal characteristics resulted from Matlab simulations. The objectives of this work are: (1) to establish a systematic procedure for constructing state-space-based small-signal models of the PISO PWM CMC bridge-based buck dc–dc converters operating in the continuous-conduction mode and have the architecture of Fig. 1, where RO models cannot be used; (2) to obtain approximate analytical expressions of the major small-signal transfer functions of these converters which include the sampling effect of the current loop and show n as a variable, thus giving the designer more insight into system performance; and (3) to verify the analysis using PSpice.

2. Small-signal modelling Each module has three parts: the power stage, the CMC stage, and the compensator stage. This work will be focused on the first two stages, as the design of the voltage loop proceeds in the same way as for a voltage-mode (duty-ratio) controlled power stage. The small-signal model is derived with the following assumptions: (a) identical converter modules; (b) ideal switching devices; (c) module isolation transformer has a negligible leakage inductance and inter-winding capacitance; (d) ideal output capacitors; (e) the sensed current of each module is noise-free; and (f) the input voltage is ripple-free.

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2.1. Power-stage modelling The following steps briefly explain how the power stage is modelled: Step 1: Starting with a two-module (n ¼ 2) arrangement, the power stage of each module is substituted by a single-buck stage. Step 2: State-space equations representing the resultant two series-connected buck cells are derived as usual using circuit equations. A controlled current source is added across the load to study the effect of changes in the load current. Step 3: Time averaging of the state-space equations and small-signal linearization are performed [18].

Repeating the above procedure for n¼ 3, a general power-stage small-signal model can be deduced. The state-space equations following time averaging and linearization can be generally expressed as 2 3 2 3 ^iL1 ^iL1 2 3 d^ 1 6 7 6 7 6 v^ o1 7 6 v^ o1 7 7 6 6 7 6 7 6 d^ 2 7 6 ^i 7 6 ^i 7 7 6 6 L2 7 6 L2 7 6 ^ 7 6 7   d6 7 7 _x^ ¼ 6 v^ o2 7 ¼ AOL 6 v^ o2 7 þ BOL 6 ð1Þ 6^ 7 7 6 7 7 6 dt 6 d n 6 ^ 7 6 ^ 7 7 6 6 7 6 7 6 v^ 7 6 7 6 7 4 g5 6 ^iLn 7 6 ^iLn 7 4 5 4 5 ^io v^ on v^ on Matrices AOL and BOL are given in Appendix A. 2.2. Module CMC-stage modelling 2.2.1. Module pulse-width modulator gain The steady-state waveforms of Fig. 2 illustrate how the duty ratio D of a converter module (say module 1) is generated. A constant-frequency clock initiates the switching cycle T and the ON time of the converter transistors. D is determined when the sensed

Fig. 2. General idealized steady-state waveforms of one module of the PISO converter of Fig. 1.

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current (usually inductor current) which has a rising slope Sn1 reaches a peak value Vc1 set by the outer voltage loop. An external ramp with a slope Se1 is added to stabilize the current feedback loop [24]. In general, the PWM modulator gain of a converter module can be written as FM ¼

1 ðSn þ Se ÞT

ð2Þ

The rising slope of the current-sensed waveform Sn is given by Sn ¼ D0 Vg Ri =L

ð3Þ

where Ri represents the gain of the current-sensing network and D0 ¼ 1D. Substituting for Sn in (2) and rearranging terms yields the following modulator gain: FM ¼

L D0 Mc Ri Vg T

Fig. 3. General complete small-signal model of power stage and current loops of the PISO converter.

ð4Þ

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where Mc ¼ 1 þ Se =Sn

ð5Þ

2.2.2. Sampling gain of the module current loop The CMC converter can be considered a sample-and-hold system [24]. The current loop is approximated by the sampling gain He(s), a double right-hand plane (RHP) zero at fs/2 He ðsÞ ffi 1 þ

s s2 þ 2 on Qz on

ð6Þ

where Qz ¼ 2=p and on ¼ p=T. 2.2.3. Feedforward gains of a converter module Feedforward gains Kf, and Kr are created when the current feedback path of each module is closed. They provide feedforward of voltages across the module inductor during the ON and OFF times of the converter, respectively. Kf ¼ DTRi ð10:5DÞ=L

ð7Þ

Kr ¼ D02 TRi =ð2LÞ

ð8Þ

A modification to the feedforward gain of (7) is found necessary to predict the module source-to-output transfer function at high frequencies. The modified expression is based on the analysis presented in [28] and adds a high-frequency zero to that given by (7). Gain Kf becomes Kf ðsÞ ¼ 

DTRi ð10:5DÞ D2 T 2 Ri ð32DÞ þ s L 12L

ð9Þ

Fig. 3 shows the complete small-signal model for the converter of Fig. 1 with the voltage loops open. Duty-ratio law of a converter module can be expressed as d^ ¼ FM ½^iL Ri He þ v^ c þ Kf v^ on þ Kr v^ off 

ð10Þ

where v^ on and v^ off are small-signal variations in the voltage across the module inductor during the ON and OFF times, respectively. 2.2.4. CMC transfer function expressions To eliminate d^ from (1), we first apply Laplace transforms to the set of equations given by (1) and then substitute, for each module, its respective duty ratio law given by (10). Assuming identical components, we get 3 2 G1 ðsÞ s^iL1 ðsÞ 7 6 6 s^vo1 ðsÞ 7 6 7 6 K1 6 6 s^i ðsÞ 7 6 0 6 L2 7 6 7 6 6 6 s^vo2 ðsÞ 7 ¼ 6 0 7 6 6 6 ^ 7 6 ^ 7 6 6 7 6 6 ^ 6 siLn ðsÞ 7 6 0 4 5 4 0 s^von ðsÞ 2

G2 ðsÞ K2 0 K2

0 0 G1 ðsÞ K1

0 K2 G2 ðsÞ K2

^ 0 K2

^ 0 0

^ 0 K2

   

0 0 0 0

& ^    G1 ðsÞ  K1

3 32 ^ iL1 ðsÞ 7 76 v^ o1 ðsÞ 7 76 7 76 ^iL2 ðsÞ 7 76 7 76 7 76 6 ^ v ðsÞ 76 o 2 7 7 76 7 ^ 7 ^ 7 6 76 7 7 ^ 7 G2 ðsÞ 56 i ðsÞ L 4 n 5 K2 v^ on ðsÞ 0 K2 0 K2

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þ

6 6 6 6 6 6 6 6 6 6 6 4

K3 0 0

0 0 K3

0 ^ 0 0

0 ^ 0 0

0 0 0

G3 ðsÞ 0 G3 ðsÞ

 0 & ^    K3  0

0 ^ G3 ðsÞ 0

  

3 0 K1 7 7 7 0 7 7 K1 7 7 7 ^ 7 7 0 7 5 K1

3 v^ c1 ðsÞ 6 v^ ðsÞ 7 6 c2 7 7 6 6 ^ 7 7 6 7 6^ 6 vcn ðsÞ 7 7 6 6 v^ g ðsÞ 7 5 4 ^io ðsÞ

267

2

ð11Þ

Expressions of G1 to G3 and K1 to K3 are listed in Table 1. The set of equations given by (11) represents the converter of Fig. 1 when all current loops are closed. Exact transfer function relations between small changes in any of the system states and small changes in the control input, source voltage or load current can be derived for a given number of modules, n. Three CMC transfer functions of interest are generated, namely, the module control-tooutput voltageð^vo =^vc Þ, the source-to-output voltage or audiosusceptibilityð^vo =^vg Þ, and the output impedanceð^vo =^io Þ K1 K3 s2 sðG1 þ K2 ðn1ÞÞ þ ðn1ÞK2 G1 K1 G2 v^ o ðsÞ ¼ 2  s sG1 K1 G2 s2 sðG1 þ nK2 Þ þ nK2 G1 K1 G2 v^ c

ð12Þ

K1 G3 v^ o ðsÞ ¼ 2 s sðG1 þ nK2 Þ þ nK2 G1 K1 G2 v^ g

ð13Þ

K1 ðsG1 Þ v^ o ðsÞ ¼ 2 ^io s sðG1 þ nK2 Þ þ nK2 G1 K1 G2

ð14Þ

The significance of (12)–(14) is that they include n as a variable. The n-dependent terms have been arrived at by deriving the transfer function of interest for n ¼ 1, then for n ¼ 2, followed by n ¼ 3. Resultant expressions are then compared with each other, thus giving the effect of changing n on that particular transfer. Deriving an expression for the module current-loop gain, however, requires a different procedure. Current-loop gain of a certain module (say module 1) is obtained by breaking the loop at point (A) in Fig. 3, leaving the current loops of other modules closed. Transfer Table 1 Summary of the parameters of Eq. (11). Parameter

Expression

G1(s)

He ðsÞ TD0 Mc ðKr Kf ðsÞÞ 1 L þ TD0 Ri Mc Kf ðsÞ D L þ TD0 Ri Mc 1 C 1 RC 1 TD0 Ri Mc

G2(s) G3(s) K1 K2 K3

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function ð^iL1 =d^ 1 Þ is then derived, and the current-loop gain ðTi1 Þ is found using Ti1 ðsÞ ¼

^iL1 ðsÞRi FM He ðsÞ d^ 1

ð15Þ

where FM and He are as given by (4) and (6) above. 3. Small-signal characteristics of CMC These characteristics are investigated using the proposed model. The derived exact expressions of the major transfer functions are coded into a Matlab programme. The circuit parameters are Vo ¼ 120 V,ðVo Þmodule ¼ 120=n, ðDVo =Vo Þ ¼ 1%, Io ¼ 4A, R ¼ 30 O, Vg ¼ 200=n, D ¼ 0:6,

T ¼ 10ms,ðLÞmodule ¼ 480 mH, ðCÞmodule ¼ 1:042mF, Ri ¼ 0:1 O, Mc ¼ 1:3to2:9 Despite the complexity of the PISO system, it is found possible to derive a set of approximate expressions describing the small-signal behaviour at both low and high frequencies. These expressions (discussed in the following subsections) were coded into the same Matlab programme. The Bode plots produced were found to be in good agreement with those generated using the exact expressions. A sample of the approximation procedure can be found in Appendix B. 3.1. Module control-to-output voltage ð^vo =^vc Þ The module control-to-output voltage transfer function is defined as the ratio of the corresponding module output voltage and its control voltage with all current loops closed. ð^vo =^vc Þ can be approximated as ð1 þ s=ozvc Þ v^ o  Fh ðsÞ ðsÞ ffi Kvc  ^vc ð1 þ s=opvc1 Þð1 þ s=opvc2 Þ Expressions for Kvc, ozvc, opvc1, opvc2, and Fh(s) are given in Table 2. Table 2 Summary of control-to-output voltage expressions. Parameter

Expression

Kvc

LR Ri

xzvc

sþðn1ÞL L½CRþTðn1ÞðD0 Mc 0:5Þ sþnL L½CRþnTðD0 Mc 0:5Þ s LCR 1 1þðs=on QÞþðs2 =o2n Þ 0

xpvc1 xpvc2 Fh(s)

 ½sþðn1ÞL s½sþnL where s ¼ RTðD0 Mc 0:5Þ

where Q ¼ 1=ðpðD Mc 0:5ÞÞ and on ¼ p=T

ð16Þ

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gain, dB

80 60 40 20 0 10-2

10-1

100 101 frequency, krad/sec

102

103

10-1

100 101 frequency, krad/sec

102

103

phase, deg

0

-100

-200

-300 10-2

Fig. 4. v^ o =^vc with Mc as a running parameter and n ¼3 UUMc ¼ 1:3,

_____

Mc ¼ 2, Mc ¼ 2:9.

gain, dB

60 40 20 0 10-2

10-1

100 101 frequency, krad/sec

102

103

10-1

100 101 frequency, krad/sec

102

103

phase, deg

0

-100

-200

-300 10-2

Fig. 5. v^ o =^vc with n as a running parameter and Mc ¼ 2.9. UUn ¼ 1,

_____

n ¼ 2, n ¼ 3.

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Fig. 4 depicts the module control-to-output voltage responses with Mc as a running parameter and n¼ 3. The low frequency (LF) region has a real left-hand plane (LHP) zero which locates between two real LHP poles. At high frequencies the response is influenced by a pair of LHP complex poles at fs/2, (also present in single-cell PWM converters) which is responsible for the peaking observed. The Q of this second-order pole is controlled using the compensation ramp; by gradually increasing Mc, it splits into two real ones: One of these poles moves to low frequencies and the other to frequencies beyond fs/2. The following equation Q¼

1 pðD0 M

ð17Þ

c 0:5Þ

80

80

60

60

gain, dB

gain, dB

can be used to decide on the size of ramp required to prevent the peaking at fs/2. The size of ramp (Mc ¼ 2.84) is required for critical damping. Fig. 5 gives the module ð^vo =^vc Þ curves as the number of modules is varied when Mc ¼ 2.9. It can be observed that adding more modules increases the LF gain. Cycle-by-cycle simulations using PSpice are carried out to examine the validity of the analysis. Fig. 6 shows PSpice results superimposed on the small-signal model predictions. A similar approach to that appeared in [42] is employed to examine frequency response. A small sinusoidal perturbation (amplitude o1% of control voltage) that has a certain

40

20

20 100

102

0

0

-50

-50

phase, deg

phase, deg

40

-100 -150 -200

100

102

100

102

-100 -150 -200

100 frequency, krad/sec

102

frequency, krad/sec

Fig. 6. Module control-to-output voltage with PSpice results superimposed on the small-signal model predictions when Mc ¼1.5. Traces (a) and (b) n¼2; Traces (c) and (d) n¼ 3. ——— Small-signal model predictions, x x x x PSpice simulation results.

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frequency (say 1 kHz) is added to the dc control voltage of a converter module after steady state conditions have been reached. PSpice is asked to find and tabulate the harmonic content of the output voltage waveform of that module using Fourier analysis. This is followed by extracting the 1 kHz component (Magnitude and Phase) from the tabulated results. The process is repeated for the set of frequencies that appears as discrete points.

Change in module output voltage, V

6

5

4

3

2

1

n=1 n=2 n=3

0 0

1

0.5

1.5

time, msec 6.0v

6.0v

5.0v

5.0v

4.0v

4.0v

3.0v

3.0v

2.0v

2.0v

1.0v

1.0v 0v

0v

n=3

n=2 -1.0v 0.9ms 1.2ms 1.5ms 1.8ms 2.1ms Time V(C1) -60

2.4ms

-1.0v 0.9ms

1.2ms

1.5ms 1.8ms Time

2.1ms

2.4ms

V(C1) -40

Fig. 7. Module output-voltage small-signal transient responses when Mc ¼2.9: (a) averaged-model predications due to a step change of 0.01 V in control voltage and (b) corresponding cycle-by-cycle simulations.

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For the time domain, small-step changes in the module control voltage are applied to the small-signal derived expressions using Matlab. The generated transient responses are compared with those produced from the more accurate cycle-by-cycle simulations. Fig. 7(a) illustrates the predicted module average output voltage during and following a 0.01-V step change in the control signal when Mc ¼ 2.9. Fig. 7(b) gives the corresponding transients produced by PSpice for n¼ 2 and 3. It is clear that the proposed expressions are valid to predict the well-damped time-domain responses of the converter when small-signal disturbances occur. For large variations in control voltage, however, a large-signal model is also necessary to study the general dynamics of a PISO converter.

Table 3 Summary of current-loop gain expressions. Parameter

Expression

Kti

L D0 RTMc

s  sþðn1ÞL where s ¼ RTðD0 Mc 0:5Þ

xzti xpti

s CRðsþnLÞ 1 pffiffiffiffiffi LC

40

gain, dB

20 0 -20 -40 10-2

10-1

100 101 frequency, krad/sec

102

103

10-1

100 101 frequency, krad/sec

102

103

phase, deg

100 0 -100 -200 -300 10-2

Fig. 8. Module current-loop gain with Mc as a running parameter and n¼ 3. UUMc ¼ 1:3, Mc ¼ 2:9.

_____

Mc ¼ 2,

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3.2. Module current-loop gain ðTi Þ This transfer function provides stability information for CMC. The module current-loop gain can be expressed as Ti ðsÞ ffi Kti 

ð1 þ s=ozti Þ  He ðsÞ ð1 þ s2 =o2pti Þ

ð18Þ

Expressions for Kti, ozti, and opti are given in Table 3. With Mc as a running parameter and n ¼ 3, Fig. 8 depicts the module current-loop gain characteristics. The LF region is dominated by the effect of the zeropat ffiffiffiffiffiffiffiozti. There is a significant peaking at the module power-stage resonant frequency ð1= LC Þ. It can be observed that the dc gain of the current loop is below unity; but increases as more ramp is added. The current-loop gain curve has two zero crossovers; the first occurs at a frequency below the power-stage resonant frequency and the second at a frequency given by ðTD0 Mc Þ1 . Sampling action of the current loop produces a pair of complex RHP zeros at (fs/2). With Mc ¼ 1.3, the magnitude of the current-loop gain touches 0 dB at this frequency with a corresponding phase of 1801. If Mc is reduced below 1.3, instability occurs. Fig. 9 gives (Ti) curves as the number of modules is varied when Mc ¼ 2.9. The dc gain is always below unity when n41, and the addition of more modules reduces this gain. Observations of Fig. 8 still apply and the following can be added: the dc gain of the current loop can be greater than one only when a single module is used, and in this case the loop has a single crossover frequency. 30

gain, dB

20 10 0 -10 -20 10-2

10-1

100 101 frequency, krad/sec

102

103

10-1

100 101 frequency, krad/sec

102

103

phase, deg

100 0 -100 -200 -300 10-2

Fig. 9. Module current-loop gain with n as a running parameter and Mc ¼ 2.9. UUn ¼ 1,

_____

n ¼ 2, n ¼ 3.

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3.3. Audiosusceptibility of a converter module ð^vo =^vg Þ The source-to-output voltage transfer function can be approximated by ð1 þ s=ozvg Þ v^ o  Fh ðsÞ ðsÞ ffi Kvg  ^vg ð1 þ s=opvg Þ

ð19Þ

Expressions for Kvg, ozvg, opvg, and Fh(s) are given in Table 4. The module audiosusceptibility curves with different slope ratios and n ¼ 3 are given in Fig. 10. The transfer function has a single real LHP pole, and a double LHP pole. This double pole is similar to that of the ð^vo =^vc Þ discussed earlier. Sampling effect is also responsible for creating a zero in the module source-to-output response. This zero is single, does not depend on the number of modules, and is strongly affected by the size of external ramp. At low values of ramp, the zero locates in the RHP at high frequencies. It moves to the LHP as more ramp is added, and eventually settles down at frequencies higher than fs/2 when Mc ¼ 2.9. Table 4 Summary of audiosusceptibility expressions. Parameter

Expression

Kvg

sb sþnL 6½D0 ðMc 0:5Þ0:5 TðD02 0:5D0 0:5Þ sþnL L½CRþnTðD0 Mc 0:5Þ RTðD0 Mc 0:5Þ 2 D0 RTðMc 0:5Þ

xzvg xpvg r b

-10 -15 -20

gain, dB

-25 -30 -35 -40 -45 -50 -55 -60 10-2

10-1

100 101 frequency, krad/sec

102

Fig. 10. Module audiosusceptibility with Mc as a running parameter and n¼3. UUMc ¼ 1:3, Mc ¼ 2:9.

103

_____

Mc ¼ 2,

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-10 -15 -20

gain, dB

-25 -30 -35 -40 -45 -50 -55 -60 10-2

10-1

100 101 frequency, krad/sec

102

Fig. 11. Module Audiosusceptibility with n as a running parameter and Mc ¼2.9. UUn ¼ 1, n ¼ 3.

103

_____

n ¼ 2,

Inspection of the Kvg terms of ð^vo =^vg Þ in Table 4 shows that the audiosusceptibility can be nulled at low frequencies with a proper choice of external ramp. For the parameters chosen, the susceptibility of this converter decreases as Mc is increased until Mc ¼ 1.8, where nulling occurs, and starts to increase with Mc41.8. Fig. 11 illustrates ð^vo =^vg Þ as the number of modules is varied when Mc ¼ 2.9. Increasing n reduces the module audiosusceptibility regardless of the size of external ramp used. Fig. 12 shows PSpice results superimposed on the small-signal model predictions. It is worth mentioning here that the audiosusceptibility is very sensitive to variations in the compensating ramp especially at low frequencies and around the null value, which explains the slight discrepancy between the predicted and simulated results in the gain plots of Fig. 12. PSpice simulations, in general, confirm the validity of the small-signal model predictions. 3.4. Output impedance of a converter module ð^vo =^io Þ The module output impedance can be approximated by 1 v^ o ðsÞ ffi Kvi  ^io ð1 þ s=opvi Þ

ð20Þ

Expressions for Kvi, and opvi, are given in Table 5. Fig. 13 gives the module output impedance curves with Mc as a running parameter and n ¼ 3. The response is influenced by a single LF real LHP pole. As it is the case with single-cell PWM converters, current-mode control increases the output impedance at low frequencies but prevents peaking at the power-stage resonant frequency.

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-20

-20

-30

-30

gain, dB

gain, dB

276

-40

-40

-50

-50 102

100

200

200

100

100

phase, deg

phase, deg

100

0 -100

102

0 -100

-200

-200 100 102 frequency, krad/sec

100 102 frequency, krad/sec

Fig. 12. Module audiosusceptibility with PSpice results superimposed on the small-signal model predictions when Mc ¼ 1.4. Traces (a) and (b) n¼ 2 ; Traces (c) and (d) n¼3. ——— Small-signal model predictions, x x x x PSpice simulation results.

Table 5 Summary of output impedance expressions. Parameter

Expression

Kvi xpvi

LR sþnL sþnL L½CRþnTðD0 Mc 0:5Þ

where s ¼ RTðD0 Mc 0:5Þ

The effect of varying the number of modules on the output impedance when Mc ¼ 2.9 is depicted in Fig. 14. One can observe that there is a drop in the module output impedance as the number of modules is increased. 4. Conclusions A small-signal model is developed for bridge-based PISO CMC PWM buck dc–dc converters operating in the continuous-current conduction mode. The model is suitable for

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277

25

20

gain, dB

15

10

5

0

-5 10-2

10-1

100

101

102

103

frequency, krad/sec Fig. 13. Module output impedance with Mc as a running parameter and n¼3. UUMc ¼ 1:3, Mc ¼ 2:9.

_____

Mc ¼ 2,

30 25

gain, dB

20 15 10 5 0 -5 10-2

10-1

100

101

102

103

frequency, krad/sec Fig. 14. Module output impedance with n as a running parameter and Mc ¼2.9. UUn ¼ 1, n ¼ 3.

_____

n ¼ 2,

studying the small-signal behaviour and the effect of varying the number of modules. The sampling effect of the module current-loop is included in the development of the model which makes it valid up to half the switching frequency.

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278

The modelling procedure resulted in a general set of transfer function expressions that include the number of modules as a variable, and are suitable for numerically predicting the major small-signal characteristics of the PISO converter. Despite the complexity of these expressions, we have found that they can be approximated by simpler ones showing the zero-pole locations. With other parameters kept unchanged, the effect of increasing the number of modules on the gain of the major transfer functions can be summarized in the following table Transfer function

Effect of increasing n

Current-loop gain Control-to-output voltage Audiosusceptibility Output impedance

Decreases and is always below unity for n41 Increases Decreases Decreases

The power-stage resonant frequency of the converter is independent of the number of modules used. The peaking observed at half the switching frequency can be damped by a proper choice of external ramp. The equation used to decide on the size of ramp is found to be similar to that used for the single-cell buck converter. A modification to the expression of the feedforward gain of the new continuous time modelling technique is needed to correctly predict the module audiosusceptibility at high frequencies. PSpice simulations showed a good agreement with the results obtained from the smallsignal model.

Appendix A. Power-stage matrices For the bridge-based PISO converter, the matrices AOL and BOL of (1) can be derived as 2

0

6 6 6 1 6 6C 6 1 6 6 6 0 6 6 AOL ¼ 6 6 0 6 6 6 ^ 6 6 6 6 0 6 6 4 0

1 L1 1 C1 R

0

0



0



0



0

0

0

1 C2 R ^

1 C2 ^

1 C1 R 1 L2 1 C2 R ^

0

0

0



0

1 Cn R

0

1 Cn R



1 Cn

0



0

&

^

0

3

7 7 1 7 7 C1 R 7 7 7 7 0 7 7 7 1 7 7 C2 R 7 7 ^ 7 7 1 7 7 7 Ln 7 7 1 5 Cn R

ðA1Þ

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2

Vg 6 L1 6 6 6 0 6 6 6 6 0 6 6 6 BOL ¼ 6 6 0 6 6 6 ^ 6 6 6 0 6 6 6 4 0

0



0

D1 L1

0



0

0

Vg L2



0

D2 L2

0



0

0

^

&

0



^ Vg Ln

^ Dn Ln

0



0

0

0

279

3

7 7 1 7 7 C1 7 7 7 0 7 7 7 7 1 7 7 C2 7 7 ^ 7 7 7 0 7 7 7 7 1 5 Cn

ðA2Þ

Appendix B. Approximation of control-to-output voltage given by Eq. (16) Substituting for G1, and G2 (from Table 1) in the general expression of vo/vc given by (12) we get 1 þ D1 s þ D2 s2 þ D3 s3 v^ o ðsÞ ¼ Kvc  ð1 þ P1 s þ P2 s2 þ P3 s3 Þð1 þ C1 s þ C2 s2 þ C3 s3 Þ v^ c

ðB1Þ

where Kvc ¼

2L½2D0 Mc RT þ 2Lðn1ÞRT Ri Tð2D0 Mc 1Þð2D0 Mc RT þ 2LnRTÞ

ðB2Þ

D1 ¼

2L½CRQz on þ ðn1Þð1 þ D0 Mc Qz Ton Þ Qz on ½2D0 Mc RT þ 2Lðn1ÞRT

ðB3Þ

D2 ¼

2L½CRon ð1 þ D0 Mc Qz Ton Þ þ Qz ðn1Þ Qz o2n ½2D0 Mc RT þ 2Lðn1ÞRT

ðB4Þ

D3 ¼

2CLR o2n ½2D0 Mc RT þ 2Lðn1ÞRT

ðB5Þ

P1 ¼

2L½CRQz on þ nð1 þ D0 Mc Qz Ton Þ Qz on ½2D0 Mc RT þ 2LnRT

ðB6Þ

P2 ¼

2L½CRon ð1 þ D0 Mc Qz Ton Þ þ nQz  Qz o2n ½2D0 Mc RT þ 2LnRT

ðB7Þ

P3 ¼

2CLR o2n ð2D0 Mc RT þ 2LnRTÞ

ðB8Þ

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280

C1 ¼

2LC Tð2D0 Mc 1Þ

C2 ¼

2LCð1 þ D0 Mc Qz Ton Þ Qz Ton ð2D0 Mc 1Þ

ðB10Þ

C3 ¼

2LC To2n ð2D0 Mc 1Þ

ðB11Þ

ðB9Þ

where Qz and on are as appeared in Eq. (6) Qz ¼ 2=p

and

on ¼ p=T

ðB12Þ

Simple calculations show that D1 bD2 and D1 bD3 P1 bP2 and P1 bP3 C1 bC2 and C1 bC3 and therefore, we can invoke the approximation   b c 2 2 3 1 þ as þ bs þ cs ffi ð1 þ asÞ 1 þ s þ s with abb and abc a a Simplifying (B1) we get ð1 þ D1 sÞð1 þ ðD2 =D1 Þs þ ðD3 =D1 Þs2 Þ v^ o ðsÞ ffi Kvc ½ð1 þ P1 sÞð1 þ ðP2 =P1 Þs þ ðP3 =P1 Þs2 Þ½ð1 þ C1 sÞð1 þ ðC2 =C1 Þs þ ðC3 =C1 Þs2 Þ v^ c

ðB13Þ The second-order zero and the two second-order poles locate in the LHP at high frequencies. Numerical calculations using Matlab revealed that the double zero coincides with the double pole ð1 þ ðP2 =P1 Þs þ ðP3 =P1 Þs2 Þ, and thus they cancel each other’s effect. Hence vo/vc can be approximated by ð1 þ D1 sÞ v^ o ðsÞ ffi Kvc ð1 þ P1 sÞð1 þ C1 sÞð1 þ ðC2 =C1 Þs þ ðC3 =C1 Þs2 Þ v^ c

ðB14Þ

Finally, using (B12), the term Kvc given by (B2) can be expressed in a simpler form Kvc ¼

LR ½s þ ðn1ÞL  Ri sðs þ nLÞ

ðB15Þ

where s ¼ RT ðD0 Mc 0:5Þ

ðB16Þ

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281

Similarly, using (B12), the terms D1, P1, C1, C2/C1, and C3/C1 can be, respectively, expressed as D1 ¼

L½CR þ Tðn1ÞðD0 Mc 0:5Þ s þ ðn1ÞL

ðB17Þ

P1 ¼

L½CR þ nTðD0 Mc 0:5Þ s þ nL

ðB18Þ

C1 ¼

LCR s

ðB19Þ

C2 pðD0 Mc 0:5Þ ¼ on C1

ðB20Þ

C3 1 ¼ 2 on C1

ðB21Þ

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