- Email: [email protected]
Sn whisker growth on Sn plating with or without surface treatment during the room temperature exposure
Journal of Alloys and Compounds 558 (2013) 125–130
Contents lists available at SciVerse ScienceDirect
Journal of Alloys and Compounds journal homepage: www.elsevier.com/locate/jalcom
Sn whisker growth on Sn plating with or without surface treatment during the room temperature exposure Keun-Soo Kim a,⇑, Sun-Sik Kim b,1, Yuuhi Yorikado b,2, Katsuaki Suganuma b, Masanobu Tsujimoto c, Isamu Yanada c a b c
Fusion Technology Lab., Hoseo University, Asan 336-795, Republic of Korea Institute of Scientific and Industrial Research, Osaka University, Osaka 567-0047, Japan C. Uyemura & Co., Ltd., Osaka 573-0065, Japan
a r t i c l e
i n f o
Article history: Received 1 November 2012 Received in revised form 14 January 2013 Accepted 15 January 2013 Available online 24 January 2013 Keywords: Sn whisker Plating Flash-coating Lead-free
a b s t r a c t The establishment of lead-free plating technology and countermeasures for whisker formation are some of the critical issues remaining to be solved for lead-free electronics packaging. This study examined a method for mitigating Sn whisker formation by depositing a thin metal layer, such as Au, Pd and Ni, on pure Sn plating. Au, Pd and Ni layers with thicknesses ranging from 50 nm to 200 nm were deposited on matte Sn plating using a flash-coating process. The Sn whisker growth behavior of pure Sn plating and metal layer/Sn plating samples at room ambient over a period of 10,000 h was observed. The metal layer/ Sn plating was considerably more stable against Sn whisker formation in room ambient environment than the pure Sn plating. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction As a result of the global transition to Pb-free electronics, the majority of electronics component manufacturers are currently using pure Sn or Sn-rich alloys for terminal and lead-frame finishes. Sn whiskers are one of the serious causes of the failure of electronics and aerospace equipment. Sn whiskers grow spontaneously from Sn-based, Pb-free finished surfaces, even at room temperature (RT). Many different types of Sn whiskers have been reported, such as RT whiskers, thermal cycle whiskers, corrosion/ oxidation whiskers, contact whiskers and electromigration whiskers, and there are many theories regarding the spontaneous growth of Sn whiskers [1–16]. A primary factor of Sn whisker formation is compressive stress, which enhances the diffusion of Sn or other elements. The sources of compressive stress are the growth of non-uniform large intermetallic compounds (IMCs) along the interface between the Sn grain boundary and Cu substrate under near RT exposure conditions, oxide formation under high humidity conditions, contact condition (external applied stress), such as connectors and mismatch of the thermal expansion coefficients during thermal cycling. Details of the major driving force for Sn whisker growth are reported elsewhere [7,13–16].
⇑ Corresponding author. 1 2
E-mail address: [email protected] (K.-S. Kim). Present address: Samsung Techwin Co., Ltd., Republic of Korea. Present address: Sony Co., Japan.
0925-8388/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.jallcom.2013.01.051
Recent studies revealed the methods for reducing Sn whisker formation and growth [17–23]. A thermal treatment after Sn plating has long been used to mitigate RT whisker formation in the electronics industry. Two types of thermal treatment are used, annealing at temperatures below the Sn melting point, such as 150 °C, and a reflowing treatment at temperatures above the Sn melting point. Both have an effect on growing a uniform IMC at the interface between the Sn grain boundary and Cu substrate [3,5,21]. Although these methods are effective in mitigating Sn whisker growth under RT conditions, thermal treatment methods have little effect on the growth of contact pressure-induced whiskers. Furthermore, they degrade the solder wettability due to the formation of oxide films at the Sn plating surface. A Ni under layer treatment is also typical method of RT whisker mitigation because non-uniform interfacial IMC growth is suppressed [14]. On the other hand, a Ni under layer is unsuitable for a number of parts, and is ineffective under other conditions. Sn alloy plating, such as Sn–Ag and Sn–Bi, have a better effect of mitigating Sn whisker growth under internally and externally applied stress conditions [21,22]. The Sn grain structure of Sn–Ag plating (near-equiaxed structure) is different from that of pure Sn plating (columnar structure). The IMCs at the interface between Sn–Bi plating and Cu substrate form not only Sn grain boundaries but also Sn grains. These differences appear to mitigate Sn whisker growth. Therefore, further research will be needed to understand the mitigation mechanism. A surface treatment of Sn plating samples is one of the many whisker mitigation strategies. Wu and Ding reported that the
126
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
Table 1 Flash-coating condition of each sample. Thickness (nm)
Current density (A/dm2)
Time (s)
Au
50 200
0.2 0.2
25 90
Pd
50 200
1 1
13 45
Ni
50 200
1 1
15 60
spraying of Sn oxide nanoparticles on Sn plating samples reduces the density of hillocks without growing whiskers during near RT exposure for 10 weeks [23]. The authors also reported the mitigation effect of metal surface-treated Sn plating on Sn whisker growth under a range of conditions [24–28]. Nevertheless, the effects of a surface treatment on Sn whisker mitigation are not completely understood. This study examined a metal surface treatment for the mitigation of Sn whisker formation during long term RT storage. 2. Experimental procedure A matte Sn electroplated film (plating bath: Soft alloy GTC-33 (C. Uyemura & Co., Ltd.), thickness: 6 ± 1 lm, cathode current density: 5 A/dm2, plating time: 144 s, plating temperature: 45 °C) was prepared on a Cu substrate (C1020) [24]. Au, Pd and Ni layers with thicknesses ranging from 50 nm to 200 nm were deposited on matte Sn plating using a flash-coating process. Table 1 lists the flash-coating conditions for each sample. The flash-coated samples were called the 50 nm or 200 nm X (X = Au, Pd, Ni)/Sn samples. All samples were stored at RT for up to 10,000 h. Au/Sn and Pd/Sn samples were stored at RT for up to 30,000 h. Surface and cross sectional images of each sample during the RT storage test were obtained by scanning electron microscopy (SEM, JSM-5510S), scanning ion microscopy (SIM, FB-2100) and transmission electron microscopy (TEM, JEM-2100). X-ray diffraction (XRD, Rint-2500) was also carried out to identify the phases formed between the metal layer and Sn plating during the RT storage test. The specimens for cross-section TEM analysis were prepared using a focused ion beam (FIB, Hitachi FB-2100) system and cross section polisher (CP, JEOL SM09010). To observe the three-dimensional morphology of the interfacial IMCs, the Sn layer on the substrates was etched deeply using a 5%HCl–90%C2H5OH solution for 1 h.
3. Results and discussion 3.1. Initial microstructure of the surface treated Sn plating Fig. 1 shows as the surface microstructures of the thin and thick Au, Pd, and Ni/Sn samples. The Sn plating exhibited a typical
Fig. 2. Enlarged image of Fig. 1c.
columnar structure with a mean grain size of approximately 6 lm. The surfaces of the 50 nm and 200 nm Au/Sn samples (Fig. 1a and d) were coated uniformly on the Sn surface, and showed a reticulate structure. Those of the Pd/Sn samples were also smooth and uniform. In the case of the Ni/Sn sample, nano particle islands were dispersed discontinuously over the Sn surface, as shown in Fig. 2. Fig. 3 shows the cross sectional SIM images of the 50 nm and 200 nm Ni/Sn samples. The Ni layer in the 200 nm Ni/Sn sample covers the entire surface of Sn plating. All Au/Sn and Pd/Sn samples showed a similar tendency. On the other hand, the 50 nm Ni/Sn sample showed a discontinuous Ni layer. Some sections of Sn plating were exposed to the air. The surface layers of the flash-coated samples were examined by TEM. Fig. 4a shows a bright-field (BF) TEM image and the selected area diffraction pattern (SADP) obtained from a second layer formed at the Au/Sn interface. The surface layers were composed of various layers with slightly different colors. The first layer from the free surface was Au layer. The second layer was identified as a AuSn2 phase from the corresponding SADP taken with the incident beam parallel to the [1 1 0] direction of AuSn2. The AuSn phases were also scattered between the Au and AuSn2 layer. Tang et al. reported that the AuSn2 and AuSn phases formed at the interface between the Au and Sn thin film couples after 5 days RT exposure
Fig. 1. Surface morphologies of the surface treated samples: (a) 50 nm Au/Sn, (b) 50 nm Pd/Sn, (c) 50 nm Ni/Sn, (d) 200 nm Au/Sn, (e) 200 nm Pd/Sn and (f) 200 nm Ni/Sn. (a– f) are at the same magnification with a scale bar of 5 lm.
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
127
Fig. 3. Cross sectional microstructures of the Ni coated samples: (a) 50 nm thick and (b) 200 nm thick. (a and b) are at the same magnification with a scale bar of 2 lm.
Fig. 4. Interfacial microstructures between coated layer and Sn plating: (a) 200 nm Au/Sn, (b) 200 nm Pd/Sn and (c) 200 nm Ni/Sn.
[29]. Fig. 4b and c shows BF TEM images and the SADPs obtained from the second layer formed at the Pd/Sn and Ni/Sn interface. The interfacial layer was identified as a mixture of PdSn4 and Ni3Sn2 phases by SADP, which was taken with the incident beam par 2] direction of PdSn4 and the [0 1 1 1] direction of allel to the [1 1 Ni3Sn2. Simic and Marinkovic reported that the PdSn4 phase formed at the Pd/Sn thin film couples after RT exposure for 1 day [30]. Therefore, all flash-coated samples can form IMCs at the interface between the metal layer and Sn plating during the plating process or TEM sampling process, even at RT. 3.2. Whisker growth behavior Fig. 5 shows a SEM image of the pure Sn sample after 10,000 h. The needle-like whisker and hillocks formed on the surface of the Sn samples. The kinked types of Sn whisker formed on the surface of the Sn and 50 nm Ni/Sn samples, as shown in Fig. 6. Fig. 7 shows the maximum changes in the length of the Sn whiskers in the plating samples during the RT storage test. The length of the Sn whiskers on the Sn and 50 nm Ni/Sn samples increased with increasing storage time. Sn whiskers were first observed on the pure Sn sample and 50 nm Ni/Sn sample after 168 h and 1200 h, respectively. The length of the Sn whisker in the Sn plating samples increased to 13 lm, whereas the increases in the length of the whiskers in the 50 nm Ni/Sn plating were more than 20 lm after 5200 h
Fig. 5. Surface morphology of pure Sn plating after room temperature storage for 10,000 h.
exposure. The length of the Sn whiskers on the Sn plating reached a maximum after 5200 h whereas the density reached a saturation point of 200/mm2 after 100 h. In contrast, the length of the whiskers on the 50 nm Ni/Sn plating became saturated after 1680 h
128
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
Fig. 6. Surface morphologies after room temperature storage for 10,000 h: (a) pure Sn plating and (b) 50 nm Ni/Sn plating. (a and b) are at the same magnification with a scale bar of 10 lm.
Fig. 7. Changes in whisker maximum length (a) and in whisker density (b) as a function of room temperature storage time.
Fig. 8. XRD patterns of before and after room temperature storage: (a) 200 nm Au/Sn plating and (b) 200 nm Ni/Sn plating.
but the density was quite low (<5/mm2). On the other hand, no whiskers were observed on the Au, Pd and 200 nm Ni/Sn plating samples after more than 10,000 h. Fig. 8 shows XRD patterns of the 200 nm Au and Ni/Sn samples before and after the RT storage test. The XRD profiles before the RT storage test indicated the existence of AuSn2 and Ni3Sn2 phases. The intensities of the peaks for these phases after the long-term storage test were stronger than those before the RT storage test. From the results of Fig. 7, Au and Pd flash plating have a better effect of mitigating Sn whisker growth. In order to examine the long term RT stability of Au and Pd/Sn samples, these samples were stored at RT for up to 30,000 h. Fig. 9 shows cross-sectional SIM images of the 200 nm Au and Pd/Sn samples after the 30,000 h RT storage test. The surface regions clearly changed their aspects. The flash-coated layers with their IMCs extended deeply into the
Sn plating side with increasing storage time. The total thickness of the surface regions in the 200 nm Au/Sn samples increased from 300 to 400 nm (Fig. 4a) to 1.5 lm (Fig. 9a) after the 30,000 h RT storage test, whereas it increased from approximately 200 nm to 1.5 lm in the 200 nm Pd/Sn samples. After the 30,000 h RT storage test, the flash-coated layers with their IMCs in the Au and Pd/Sn samples were still uniform, and no whiskers were observed. Fig. 10 shows the SEM images of the interfacial IMCs on the Cu substrate before and after the RT storage test, viewed from the top after deep etching. In the case of the as-plated pure Sn samples, Cu6Sn5 IMCs between the Sn plating and Cu substrate formed as localized precipitates along the grain boundary of Sn (Fig. 10a). After the RT storage test for 670 h, they grew into large particles (Fig. 10a). The tendency for Cu–Sn compound growth of the metal layer/Sn plating samples was similar to that of the pure Sn plating
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
129
Fig. 9. Cross-sectional SIM images after room temperature storage for 30,000 h: (a) 200 nm Au/Sn plating and (b) 200 nm Pd/Sn plating. (a and b) are at the same magnification with a scale bar of 3.5 lm.
Fig. 10. Interfacial IMCs between Sn and Cu: (a) as-plated sample and (b) after room temperature storage for 670 h sample (Sn layer was deeply etched). (a and b) are at the same magnification with a scale bar of 5 lm.
Fig. 11. Schematic illustration of Sn whisker growth during room temperature storage: (a) Sn plating, (b) inhomogeneous coated layer/Sn plating and (c) homogeneous coated layer/Sn plating.
samples. The formation and growth of interfacial Cu6Sn5 IMCs can be a source of compressive stresses that acts on the Sn grains, as shown in Fig. 11a. Interestingly, Sn whiskers were not observed at the uniform metal layer/Sn plating samples during RT storage, even though Cu6Sn5 IMCs grew up from the interface. The whisker-free tendency observed in the Au, Pd and 200 nm Ni/Sn samples after the RT storage test was attributed to uniform layer formation on the entire surface of the Sn plating samples. Those layers were quite uniform and stable during RT storage, and acted as a protective layer of Sn whisker nucleation on the Sn plating
surface, as shown schematically in Fig. 11c. The compressive stresses caused by the growth of interfacial Cu–Sn IMCs between Sn and Cu rarely affect Sn whisker formation in those cases. In the case of the 50 nm Ni/Sn sample, the Ni layer was not uniform, and some sections of Sn plating were exposed to the air, as shown schematically in Fig. 11b. This can explain why a small number of long Sn whiskers were observed in the 50 nm Ni/Sn sample. Sn whiskers can grow from the Sn surface, where the Ni layer was interrupted locally.
130
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
4. Conclusions This study examined the Sn whisker growth behavior of the pure Sn plating and metal layer/Sn plating samples under internal stress conditions. Sn whiskers formed on the surface of the pure Sn and 50 nm Ni/Sn samples during the RT storage test. The formation of interfacial IMCs along the grain boundaries near the Cu substrate generated compressive stress in/on a Sn grain. As a result, Sn whiskers grew from the surface of the Sn grains to release this compressive stress. Compared to pure Sn plating, no Sn whiskers or hillocks were observed on the 50–200 nm Au/Sn and Pd/Sn samples, even after 30,000 h storage at RT. The uniform metal layers on the Sn plating samples reduced the risk of Sn whisker failure significantly. Overall, Au and Pd flash plating has potential for Sn whisker mitigation under RT exposure conditions. Acknowledgements The authors acknowledge the Materials Analysis Center, ISIR, Osaka University for the use of XRD equipment. This work was partly supported by a Grant-in-Aid for Science Research (A) of the Japan Society for the Promotion of Science (JSPS), Grant No. 21246109. References [1] K.N. Tu, Mater. Chem. Phys. 46 (1996) 217–223. [2] B.-Z. Lee, D.N. Lee, Acta Mater. 46–10 (1998) 3701–3714. [3] W.J. Boettinger, C.E. Johnson, L.A. Bendersky, K.W. Moon, M.E. Williams, G.R. Stafford, Acta Mater. 53 (2005) 5033–5050. [4] W.J. Choi, T.Y. Lee, K.N. Tu, N. Tamura, R.S. Celestre, A.A. MacDowell, Y.Y. Bong, Luu Nguyen, Acta Mater. 51 (2003) 6253–6261. [5] K.N. Tu, J.C.M. Li, Mater. Sci. Eng. A 409 (2005) 131–139. [6] Y. Nakadaira, S. Jeong, J. Shim, J. Seo, S. Min, T. Cho, S. Kang, S. Oh, Microelectron. Reliab. 48 (2008) 83–104. [7] K.S. Kim, T. Matsuura, K. Suganuma, J. Electron. Mater. 35–1 (2006) 41–47.
[8] T. Yamashita, T. Shibutani, Q. Yu, M. Shiratori, IEEE Trans. Electron. Packag. Manuf. 29–4 (2006) 259–264. [9] H. Moriuchi, Y. Tadokoro, M. Sato, T. Furusawa, N. Suzuki, J. Electron. Mater. 36–3 (2007) 220–225. [10] S.H. Liu, C. Chen, P.C. Liu, T. Chou, J. Appl. Phys. 95–12 (2004) 7742–7747. [11] Y. Fukuda, M. Osterman, M. Pecht, Microelectron. Reliab. 47–1 (2007) 88–92. [12] Y.W. Lin, Y.S. Lai, Y.L. Lin, C.T. Tu, C.R. Kao, J. Electron. Mater. 37–1 (2008) 17– 22. [13] K. Suganuma, A. Baated, K.S. Kim, K. Hamasaki, N. Nemoto, T. Nakagawa, T. Yamada, Acta Mater. 59 (2011) 7255–7267. [14] A. Batted, K.S. Kim, K. Suganuma, J. Mater. Sci.: Mater. Electron. 22 (2011) 1685–1693. [15] S.H. Lin, Y. Yorikado, J. Jiang, K.S. Kim, K. Suganuma, S.W. Chen, M. Tsujimoto, I. Yanada, J. Mater. Res. 22–7 (2007) 1975–1986. [16] S.H. Lin, Y. Yorikado, J. Jiang, K.S. Kim, K. Suganuma, S.W. Chen, M. Tsujimoto, I. Yanada, J. Electron. Mater. 36–12 (2007) 1732–1734. [17] T.A. Woodrow, E.A. Ledbury, in: Proc.ICP/JEDEC 8th International Conference on Lead-Free Electronic Components and Assemblies, San Jose, CA, April 18– 20, 2005. [18] M. Takeuchi, K. Kamiyama, K. Suganuma, J. Electron. Mater. 35–11 (2006) 1918–1925. [19] J.P. Winterstein, M.G. Norton, J. Mater. Res. 21–12 (2006) 2971–2974. [20] T. Kato, H. Akahoshi, M. Nakamura, T. Hashimoto, A. Nishima, IEEE Trans. Electron. Packag. Manuf. 30–4 (2007) 258–269. [21] A. Batted, K. Hamasaki, S.S. Kim, K.S. Kim, K. Suganuma, J. Electron. Mater. 40– 11 (2011) 2278–2289. [22] T. Asai, T. Kiga, Y. Taniguchi, H. Morikawa, K. Sumiyama, J. Jpn. Inst. Met. 73–11 (2009) 823–832. [23] A.T. Wu, Y.C. Ding, Microelectron. Reliab. 49–3 (2009) 318–322. [24] M. Tsujimoto, I. Yanada, K. Suganuma, K.S. Kim, JP Patent 2007-100148, 2007. [25] Y. Yorikado, K.S. Kim, K. Suganuma, M. Tsujimoto, I. Yanada, in: Proc. 16th Micro-Electronic Symposium, Osaka, Japan: Japan Institute of Electronics Packaging, 2006, pp. 207–210. [26] K. Suganuma, K.S. Kim, Y. Yorikado, M. Tsujimoto, I. Yanada, in: 136th TMS Annual Meeting & Exhibition, Orlando, FL, USA, February 25–March 16, 2007, pp. 153. [27] K.S. Kim, S.S. Kim, S.J. Kim, K. Suganuma, M. Tsujimoto, I. Yanada, in: 137th TMS Annual Meeting & Exhibition, New Orleans, LA, USA, March 9–March 13, 2008, pp. 187. [28] K.S. Kim, S.S. Kim, S.J. Kim, K. Suganuma, M. Tsujimoto, I. Yanada, in: 138th TMS Annual Meeting & Exhibition, San Francisco, CA, USA, March 9–March 13, 2009, pp. 74. [29] W. Tang, A. He, Q. Liu, D.G. Ivey, Acta Mater. 56–19 (2008) 5818–5827. [30] V. Simic, Z. Marinkovic, Mater. Chem. Phys. 47 (1997) 246–248.
Contents lists available at SciVerse ScienceDirect
Journal of Alloys and Compounds journal homepage: www.elsevier.com/locate/jalcom
Sn whisker growth on Sn plating with or without surface treatment during the room temperature exposure Keun-Soo Kim a,⇑, Sun-Sik Kim b,1, Yuuhi Yorikado b,2, Katsuaki Suganuma b, Masanobu Tsujimoto c, Isamu Yanada c a b c
Fusion Technology Lab., Hoseo University, Asan 336-795, Republic of Korea Institute of Scientific and Industrial Research, Osaka University, Osaka 567-0047, Japan C. Uyemura & Co., Ltd., Osaka 573-0065, Japan
a r t i c l e
i n f o
Article history: Received 1 November 2012 Received in revised form 14 January 2013 Accepted 15 January 2013 Available online 24 January 2013 Keywords: Sn whisker Plating Flash-coating Lead-free
a b s t r a c t The establishment of lead-free plating technology and countermeasures for whisker formation are some of the critical issues remaining to be solved for lead-free electronics packaging. This study examined a method for mitigating Sn whisker formation by depositing a thin metal layer, such as Au, Pd and Ni, on pure Sn plating. Au, Pd and Ni layers with thicknesses ranging from 50 nm to 200 nm were deposited on matte Sn plating using a flash-coating process. The Sn whisker growth behavior of pure Sn plating and metal layer/Sn plating samples at room ambient over a period of 10,000 h was observed. The metal layer/ Sn plating was considerably more stable against Sn whisker formation in room ambient environment than the pure Sn plating. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction As a result of the global transition to Pb-free electronics, the majority of electronics component manufacturers are currently using pure Sn or Sn-rich alloys for terminal and lead-frame finishes. Sn whiskers are one of the serious causes of the failure of electronics and aerospace equipment. Sn whiskers grow spontaneously from Sn-based, Pb-free finished surfaces, even at room temperature (RT). Many different types of Sn whiskers have been reported, such as RT whiskers, thermal cycle whiskers, corrosion/ oxidation whiskers, contact whiskers and electromigration whiskers, and there are many theories regarding the spontaneous growth of Sn whiskers [1–16]. A primary factor of Sn whisker formation is compressive stress, which enhances the diffusion of Sn or other elements. The sources of compressive stress are the growth of non-uniform large intermetallic compounds (IMCs) along the interface between the Sn grain boundary and Cu substrate under near RT exposure conditions, oxide formation under high humidity conditions, contact condition (external applied stress), such as connectors and mismatch of the thermal expansion coefficients during thermal cycling. Details of the major driving force for Sn whisker growth are reported elsewhere [7,13–16].
⇑ Corresponding author. 1 2
E-mail address: [email protected] (K.-S. Kim). Present address: Samsung Techwin Co., Ltd., Republic of Korea. Present address: Sony Co., Japan.
0925-8388/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.jallcom.2013.01.051
Recent studies revealed the methods for reducing Sn whisker formation and growth [17–23]. A thermal treatment after Sn plating has long been used to mitigate RT whisker formation in the electronics industry. Two types of thermal treatment are used, annealing at temperatures below the Sn melting point, such as 150 °C, and a reflowing treatment at temperatures above the Sn melting point. Both have an effect on growing a uniform IMC at the interface between the Sn grain boundary and Cu substrate [3,5,21]. Although these methods are effective in mitigating Sn whisker growth under RT conditions, thermal treatment methods have little effect on the growth of contact pressure-induced whiskers. Furthermore, they degrade the solder wettability due to the formation of oxide films at the Sn plating surface. A Ni under layer treatment is also typical method of RT whisker mitigation because non-uniform interfacial IMC growth is suppressed [14]. On the other hand, a Ni under layer is unsuitable for a number of parts, and is ineffective under other conditions. Sn alloy plating, such as Sn–Ag and Sn–Bi, have a better effect of mitigating Sn whisker growth under internally and externally applied stress conditions [21,22]. The Sn grain structure of Sn–Ag plating (near-equiaxed structure) is different from that of pure Sn plating (columnar structure). The IMCs at the interface between Sn–Bi plating and Cu substrate form not only Sn grain boundaries but also Sn grains. These differences appear to mitigate Sn whisker growth. Therefore, further research will be needed to understand the mitigation mechanism. A surface treatment of Sn plating samples is one of the many whisker mitigation strategies. Wu and Ding reported that the
126
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
Table 1 Flash-coating condition of each sample. Thickness (nm)
Current density (A/dm2)
Time (s)
Au
50 200
0.2 0.2
25 90
Pd
50 200
1 1
13 45
Ni
50 200
1 1
15 60
spraying of Sn oxide nanoparticles on Sn plating samples reduces the density of hillocks without growing whiskers during near RT exposure for 10 weeks [23]. The authors also reported the mitigation effect of metal surface-treated Sn plating on Sn whisker growth under a range of conditions [24–28]. Nevertheless, the effects of a surface treatment on Sn whisker mitigation are not completely understood. This study examined a metal surface treatment for the mitigation of Sn whisker formation during long term RT storage. 2. Experimental procedure A matte Sn electroplated film (plating bath: Soft alloy GTC-33 (C. Uyemura & Co., Ltd.), thickness: 6 ± 1 lm, cathode current density: 5 A/dm2, plating time: 144 s, plating temperature: 45 °C) was prepared on a Cu substrate (C1020) [24]. Au, Pd and Ni layers with thicknesses ranging from 50 nm to 200 nm were deposited on matte Sn plating using a flash-coating process. Table 1 lists the flash-coating conditions for each sample. The flash-coated samples were called the 50 nm or 200 nm X (X = Au, Pd, Ni)/Sn samples. All samples were stored at RT for up to 10,000 h. Au/Sn and Pd/Sn samples were stored at RT for up to 30,000 h. Surface and cross sectional images of each sample during the RT storage test were obtained by scanning electron microscopy (SEM, JSM-5510S), scanning ion microscopy (SIM, FB-2100) and transmission electron microscopy (TEM, JEM-2100). X-ray diffraction (XRD, Rint-2500) was also carried out to identify the phases formed between the metal layer and Sn plating during the RT storage test. The specimens for cross-section TEM analysis were prepared using a focused ion beam (FIB, Hitachi FB-2100) system and cross section polisher (CP, JEOL SM09010). To observe the three-dimensional morphology of the interfacial IMCs, the Sn layer on the substrates was etched deeply using a 5%HCl–90%C2H5OH solution for 1 h.
3. Results and discussion 3.1. Initial microstructure of the surface treated Sn plating Fig. 1 shows as the surface microstructures of the thin and thick Au, Pd, and Ni/Sn samples. The Sn plating exhibited a typical
Fig. 2. Enlarged image of Fig. 1c.
columnar structure with a mean grain size of approximately 6 lm. The surfaces of the 50 nm and 200 nm Au/Sn samples (Fig. 1a and d) were coated uniformly on the Sn surface, and showed a reticulate structure. Those of the Pd/Sn samples were also smooth and uniform. In the case of the Ni/Sn sample, nano particle islands were dispersed discontinuously over the Sn surface, as shown in Fig. 2. Fig. 3 shows the cross sectional SIM images of the 50 nm and 200 nm Ni/Sn samples. The Ni layer in the 200 nm Ni/Sn sample covers the entire surface of Sn plating. All Au/Sn and Pd/Sn samples showed a similar tendency. On the other hand, the 50 nm Ni/Sn sample showed a discontinuous Ni layer. Some sections of Sn plating were exposed to the air. The surface layers of the flash-coated samples were examined by TEM. Fig. 4a shows a bright-field (BF) TEM image and the selected area diffraction pattern (SADP) obtained from a second layer formed at the Au/Sn interface. The surface layers were composed of various layers with slightly different colors. The first layer from the free surface was Au layer. The second layer was identified as a AuSn2 phase from the corresponding SADP taken with the incident beam parallel to the [1 1 0] direction of AuSn2. The AuSn phases were also scattered between the Au and AuSn2 layer. Tang et al. reported that the AuSn2 and AuSn phases formed at the interface between the Au and Sn thin film couples after 5 days RT exposure
Fig. 1. Surface morphologies of the surface treated samples: (a) 50 nm Au/Sn, (b) 50 nm Pd/Sn, (c) 50 nm Ni/Sn, (d) 200 nm Au/Sn, (e) 200 nm Pd/Sn and (f) 200 nm Ni/Sn. (a– f) are at the same magnification with a scale bar of 5 lm.
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
127
Fig. 3. Cross sectional microstructures of the Ni coated samples: (a) 50 nm thick and (b) 200 nm thick. (a and b) are at the same magnification with a scale bar of 2 lm.
Fig. 4. Interfacial microstructures between coated layer and Sn plating: (a) 200 nm Au/Sn, (b) 200 nm Pd/Sn and (c) 200 nm Ni/Sn.
[29]. Fig. 4b and c shows BF TEM images and the SADPs obtained from the second layer formed at the Pd/Sn and Ni/Sn interface. The interfacial layer was identified as a mixture of PdSn4 and Ni3Sn2 phases by SADP, which was taken with the incident beam par 2] direction of PdSn4 and the [0 1 1 1] direction of allel to the [1 1 Ni3Sn2. Simic and Marinkovic reported that the PdSn4 phase formed at the Pd/Sn thin film couples after RT exposure for 1 day [30]. Therefore, all flash-coated samples can form IMCs at the interface between the metal layer and Sn plating during the plating process or TEM sampling process, even at RT. 3.2. Whisker growth behavior Fig. 5 shows a SEM image of the pure Sn sample after 10,000 h. The needle-like whisker and hillocks formed on the surface of the Sn samples. The kinked types of Sn whisker formed on the surface of the Sn and 50 nm Ni/Sn samples, as shown in Fig. 6. Fig. 7 shows the maximum changes in the length of the Sn whiskers in the plating samples during the RT storage test. The length of the Sn whiskers on the Sn and 50 nm Ni/Sn samples increased with increasing storage time. Sn whiskers were first observed on the pure Sn sample and 50 nm Ni/Sn sample after 168 h and 1200 h, respectively. The length of the Sn whisker in the Sn plating samples increased to 13 lm, whereas the increases in the length of the whiskers in the 50 nm Ni/Sn plating were more than 20 lm after 5200 h
Fig. 5. Surface morphology of pure Sn plating after room temperature storage for 10,000 h.
exposure. The length of the Sn whiskers on the Sn plating reached a maximum after 5200 h whereas the density reached a saturation point of 200/mm2 after 100 h. In contrast, the length of the whiskers on the 50 nm Ni/Sn plating became saturated after 1680 h
128
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
Fig. 6. Surface morphologies after room temperature storage for 10,000 h: (a) pure Sn plating and (b) 50 nm Ni/Sn plating. (a and b) are at the same magnification with a scale bar of 10 lm.
Fig. 7. Changes in whisker maximum length (a) and in whisker density (b) as a function of room temperature storage time.
Fig. 8. XRD patterns of before and after room temperature storage: (a) 200 nm Au/Sn plating and (b) 200 nm Ni/Sn plating.
but the density was quite low (<5/mm2). On the other hand, no whiskers were observed on the Au, Pd and 200 nm Ni/Sn plating samples after more than 10,000 h. Fig. 8 shows XRD patterns of the 200 nm Au and Ni/Sn samples before and after the RT storage test. The XRD profiles before the RT storage test indicated the existence of AuSn2 and Ni3Sn2 phases. The intensities of the peaks for these phases after the long-term storage test were stronger than those before the RT storage test. From the results of Fig. 7, Au and Pd flash plating have a better effect of mitigating Sn whisker growth. In order to examine the long term RT stability of Au and Pd/Sn samples, these samples were stored at RT for up to 30,000 h. Fig. 9 shows cross-sectional SIM images of the 200 nm Au and Pd/Sn samples after the 30,000 h RT storage test. The surface regions clearly changed their aspects. The flash-coated layers with their IMCs extended deeply into the
Sn plating side with increasing storage time. The total thickness of the surface regions in the 200 nm Au/Sn samples increased from 300 to 400 nm (Fig. 4a) to 1.5 lm (Fig. 9a) after the 30,000 h RT storage test, whereas it increased from approximately 200 nm to 1.5 lm in the 200 nm Pd/Sn samples. After the 30,000 h RT storage test, the flash-coated layers with their IMCs in the Au and Pd/Sn samples were still uniform, and no whiskers were observed. Fig. 10 shows the SEM images of the interfacial IMCs on the Cu substrate before and after the RT storage test, viewed from the top after deep etching. In the case of the as-plated pure Sn samples, Cu6Sn5 IMCs between the Sn plating and Cu substrate formed as localized precipitates along the grain boundary of Sn (Fig. 10a). After the RT storage test for 670 h, they grew into large particles (Fig. 10a). The tendency for Cu–Sn compound growth of the metal layer/Sn plating samples was similar to that of the pure Sn plating
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
129
Fig. 9. Cross-sectional SIM images after room temperature storage for 30,000 h: (a) 200 nm Au/Sn plating and (b) 200 nm Pd/Sn plating. (a and b) are at the same magnification with a scale bar of 3.5 lm.
Fig. 10. Interfacial IMCs between Sn and Cu: (a) as-plated sample and (b) after room temperature storage for 670 h sample (Sn layer was deeply etched). (a and b) are at the same magnification with a scale bar of 5 lm.
Fig. 11. Schematic illustration of Sn whisker growth during room temperature storage: (a) Sn plating, (b) inhomogeneous coated layer/Sn plating and (c) homogeneous coated layer/Sn plating.
samples. The formation and growth of interfacial Cu6Sn5 IMCs can be a source of compressive stresses that acts on the Sn grains, as shown in Fig. 11a. Interestingly, Sn whiskers were not observed at the uniform metal layer/Sn plating samples during RT storage, even though Cu6Sn5 IMCs grew up from the interface. The whisker-free tendency observed in the Au, Pd and 200 nm Ni/Sn samples after the RT storage test was attributed to uniform layer formation on the entire surface of the Sn plating samples. Those layers were quite uniform and stable during RT storage, and acted as a protective layer of Sn whisker nucleation on the Sn plating
surface, as shown schematically in Fig. 11c. The compressive stresses caused by the growth of interfacial Cu–Sn IMCs between Sn and Cu rarely affect Sn whisker formation in those cases. In the case of the 50 nm Ni/Sn sample, the Ni layer was not uniform, and some sections of Sn plating were exposed to the air, as shown schematically in Fig. 11b. This can explain why a small number of long Sn whiskers were observed in the 50 nm Ni/Sn sample. Sn whiskers can grow from the Sn surface, where the Ni layer was interrupted locally.
130
K.-S. Kim et al. / Journal of Alloys and Compounds 558 (2013) 125–130
4. Conclusions This study examined the Sn whisker growth behavior of the pure Sn plating and metal layer/Sn plating samples under internal stress conditions. Sn whiskers formed on the surface of the pure Sn and 50 nm Ni/Sn samples during the RT storage test. The formation of interfacial IMCs along the grain boundaries near the Cu substrate generated compressive stress in/on a Sn grain. As a result, Sn whiskers grew from the surface of the Sn grains to release this compressive stress. Compared to pure Sn plating, no Sn whiskers or hillocks were observed on the 50–200 nm Au/Sn and Pd/Sn samples, even after 30,000 h storage at RT. The uniform metal layers on the Sn plating samples reduced the risk of Sn whisker failure significantly. Overall, Au and Pd flash plating has potential for Sn whisker mitigation under RT exposure conditions. Acknowledgements The authors acknowledge the Materials Analysis Center, ISIR, Osaka University for the use of XRD equipment. This work was partly supported by a Grant-in-Aid for Science Research (A) of the Japan Society for the Promotion of Science (JSPS), Grant No. 21246109. References [1] K.N. Tu, Mater. Chem. Phys. 46 (1996) 217–223. [2] B.-Z. Lee, D.N. Lee, Acta Mater. 46–10 (1998) 3701–3714. [3] W.J. Boettinger, C.E. Johnson, L.A. Bendersky, K.W. Moon, M.E. Williams, G.R. Stafford, Acta Mater. 53 (2005) 5033–5050. [4] W.J. Choi, T.Y. Lee, K.N. Tu, N. Tamura, R.S. Celestre, A.A. MacDowell, Y.Y. Bong, Luu Nguyen, Acta Mater. 51 (2003) 6253–6261. [5] K.N. Tu, J.C.M. Li, Mater. Sci. Eng. A 409 (2005) 131–139. [6] Y. Nakadaira, S. Jeong, J. Shim, J. Seo, S. Min, T. Cho, S. Kang, S. Oh, Microelectron. Reliab. 48 (2008) 83–104. [7] K.S. Kim, T. Matsuura, K. Suganuma, J. Electron. Mater. 35–1 (2006) 41–47.
[8] T. Yamashita, T. Shibutani, Q. Yu, M. Shiratori, IEEE Trans. Electron. Packag. Manuf. 29–4 (2006) 259–264. [9] H. Moriuchi, Y. Tadokoro, M. Sato, T. Furusawa, N. Suzuki, J. Electron. Mater. 36–3 (2007) 220–225. [10] S.H. Liu, C. Chen, P.C. Liu, T. Chou, J. Appl. Phys. 95–12 (2004) 7742–7747. [11] Y. Fukuda, M. Osterman, M. Pecht, Microelectron. Reliab. 47–1 (2007) 88–92. [12] Y.W. Lin, Y.S. Lai, Y.L. Lin, C.T. Tu, C.R. Kao, J. Electron. Mater. 37–1 (2008) 17– 22. [13] K. Suganuma, A. Baated, K.S. Kim, K. Hamasaki, N. Nemoto, T. Nakagawa, T. Yamada, Acta Mater. 59 (2011) 7255–7267. [14] A. Batted, K.S. Kim, K. Suganuma, J. Mater. Sci.: Mater. Electron. 22 (2011) 1685–1693. [15] S.H. Lin, Y. Yorikado, J. Jiang, K.S. Kim, K. Suganuma, S.W. Chen, M. Tsujimoto, I. Yanada, J. Mater. Res. 22–7 (2007) 1975–1986. [16] S.H. Lin, Y. Yorikado, J. Jiang, K.S. Kim, K. Suganuma, S.W. Chen, M. Tsujimoto, I. Yanada, J. Electron. Mater. 36–12 (2007) 1732–1734. [17] T.A. Woodrow, E.A. Ledbury, in: Proc.ICP/JEDEC 8th International Conference on Lead-Free Electronic Components and Assemblies, San Jose, CA, April 18– 20, 2005. [18] M. Takeuchi, K. Kamiyama, K. Suganuma, J. Electron. Mater. 35–11 (2006) 1918–1925. [19] J.P. Winterstein, M.G. Norton, J. Mater. Res. 21–12 (2006) 2971–2974. [20] T. Kato, H. Akahoshi, M. Nakamura, T. Hashimoto, A. Nishima, IEEE Trans. Electron. Packag. Manuf. 30–4 (2007) 258–269. [21] A. Batted, K. Hamasaki, S.S. Kim, K.S. Kim, K. Suganuma, J. Electron. Mater. 40– 11 (2011) 2278–2289. [22] T. Asai, T. Kiga, Y. Taniguchi, H. Morikawa, K. Sumiyama, J. Jpn. Inst. Met. 73–11 (2009) 823–832. [23] A.T. Wu, Y.C. Ding, Microelectron. Reliab. 49–3 (2009) 318–322. [24] M. Tsujimoto, I. Yanada, K. Suganuma, K.S. Kim, JP Patent 2007-100148, 2007. [25] Y. Yorikado, K.S. Kim, K. Suganuma, M. Tsujimoto, I. Yanada, in: Proc. 16th Micro-Electronic Symposium, Osaka, Japan: Japan Institute of Electronics Packaging, 2006, pp. 207–210. [26] K. Suganuma, K.S. Kim, Y. Yorikado, M. Tsujimoto, I. Yanada, in: 136th TMS Annual Meeting & Exhibition, Orlando, FL, USA, February 25–March 16, 2007, pp. 153. [27] K.S. Kim, S.S. Kim, S.J. Kim, K. Suganuma, M. Tsujimoto, I. Yanada, in: 137th TMS Annual Meeting & Exhibition, New Orleans, LA, USA, March 9–March 13, 2008, pp. 187. [28] K.S. Kim, S.S. Kim, S.J. Kim, K. Suganuma, M. Tsujimoto, I. Yanada, in: 138th TMS Annual Meeting & Exhibition, San Francisco, CA, USA, March 9–March 13, 2009, pp. 74. [29] W. Tang, A. He, Q. Liu, D.G. Ivey, Acta Mater. 56–19 (2008) 5818–5827. [30] V. Simic, Z. Marinkovic, Mater. Chem. Phys. 47 (1997) 246–248.