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Software
Hardware Eckert, K 'A multiprocessor interface' IEEE Micro Vol 2 No 4 (November 1982) pp 67-70 The presence of intelligent peripherals in a microcomputer system makes it, in effect, a multiprocessor system. An interface between the central micro and the peripherals should be able to transmit all types of information (e.g. data, status and control) in both directions. This article describes a hardware link between two systems, each of which can be considered a peripheral of the other. The link uses two MC68230 parallel interface timer chips. It is said to be device independent.
Lamb, J 'Micro growing pains or the mainframe's death throes?' Comput. Management (August/September 1982) pp 18-24 The problem of retrofitting LANs ton existing data processing structures is discussed. Pros and cons of PABXs in LANs is considered followed by a description of Ethernet as an alternative. Operation of Cambridge Ring LANs are detailed, and its advantages outlined. It is pointed out that neither system is particularly suitable for voice transmission. An outline of the baseband versus broadband issue is followed by the location of LANs in the wider field of computer advances.
Okada, Y, Tajima, H and Mori, R 'A reconfigurable parallel processor with microprogram control' IEEE Micro Vol 2 No 4 (November 1982) pp 48-60 A parallel processor belongs to the class of single-instruction multiple data stream (SIMD) and consists of a control unit and multiple processing elements. Such devices can be implemented in VLSI, but a wide range of potential applications is needed to ensure economical production. This paper outlines various data structures and algorithms which should be fitted to allow this. They include variable word length, corn-
38
munication paths and reconfigurable structures. The system's microprogrammable features, implemented through a straightforward data routing scheme, require only about 18 per cent of the total number of processingelement ~ates.
Twaddell, W 'EDN's ninth annual/JP/#C chip directory' EDN Vol 27 No 21 (27 October 1982) pp 99-204 4-bit PMOS to 32-bit micromainframes are covered in this survey of microprocessor and single chip microcomputers. Each description gives priving and availability, as well as a 'status' assessment of the chip considering its history and market rivals. There is a hardware block diagram for each chip with a list of software functions. The descriptions end with an overview of support hardware and software. Zumchak, E M 'Mastering ~tP write timing creates design alternatives' EDN Vol 27 No 21 (27 October 1982) pp 207-210 To design output ports, it is necessary to understand the timing requirements of the output device and the writetiming sequence provided by the microprocessor. Zumchak considers both these and gives examples of variations that may occur. There are two main styles of read/write timing. Frequent clock edges characterize the 8080/Z80, and symmetry characterizes the 6800/6502. Advantages and disadvantages of both are outlined. TTL logic and gate write strobes are also covered.
Software Arora, R K and Sharma, N K 'On the design of a distributed operating system using a high level distributed programming language' Microproc. Microprog. Vol 10 No 4 (November 1982) pp 247-254 It is possible to build a general purpose system out of an independent microprocessor with distributed storage. However, a problem arises in the writing of distributed programs. This paper presents a methodology
for designing a distributed operating system. The advantages of using a high level distributed programming language as a design, documentation and implementation tool is illustrated.
Ortega, R 'Experimental evaluation of four microprocessor-based advanced control algorithms' Microproc. Microprog. Vol 10 No 4 (November 1982) pp 229-245 As microsystems find application in factory process control, new control theories emerge to take advantage of the software flexibility of stand alone units. This paper presents four algorithms which can be used in low computing power, discrete time environments and for direct digital control. Hardware and software requirements are described. Experimental results on both simulated and real plants are presented and the performance discussed.
Patterson, D A and Piepho, R S 'Assessing RISCs in high level language support' IEEE Micro Vol 2 No 4 (November 1982) pp 9-19 Increasingly complex computer architectures mean longer and more difficult debugging. This paper compares a reduced instruction set computer, RISC I, with five traditional machines. The five are a 68000 (19 MHz), Z8002 (6 MHz), VAX-11/780, 11/70 and C/70. Details of the benchmarks used are given, and the results indicate that the RISC I has the highest performance with the smallest penalty for using a high level language. Stigall, P D, Ziemer, R E and Hudec, L 'A performance study of 16-bit microcomputer-implemented FFT algorithms' IEEE Micro Vol 2 No 4 (November 1982) pp 61-66 Microcomputer tasks in digital signal processing include filtering and control. One form of filtering is performed using a fast Fourier transform, FFT, algorithm. This paper sets out the execution performance of Gold-Bially FFT algorithms on a 16-bit computer - Intel's SBC 86/12A. The author's example can calculate a 256 point transform in less than 400 ms. This
microprocessors and microsystems
Lamb, J 'Micro growing pains or the mainframe's death throes?' Comput. Management (August/September 1982) pp 18-24 The problem of retrofitting LANs ton existing data processing structures is discussed. Pros and cons of PABXs in LANs is considered followed by a description of Ethernet as an alternative. Operation of Cambridge Ring LANs are detailed, and its advantages outlined. It is pointed out that neither system is particularly suitable for voice transmission. An outline of the baseband versus broadband issue is followed by the location of LANs in the wider field of computer advances.
Okada, Y, Tajima, H and Mori, R 'A reconfigurable parallel processor with microprogram control' IEEE Micro Vol 2 No 4 (November 1982) pp 48-60 A parallel processor belongs to the class of single-instruction multiple data stream (SIMD) and consists of a control unit and multiple processing elements. Such devices can be implemented in VLSI, but a wide range of potential applications is needed to ensure economical production. This paper outlines various data structures and algorithms which should be fitted to allow this. They include variable word length, corn-
38
munication paths and reconfigurable structures. The system's microprogrammable features, implemented through a straightforward data routing scheme, require only about 18 per cent of the total number of processingelement ~ates.
Twaddell, W 'EDN's ninth annual/JP/#C chip directory' EDN Vol 27 No 21 (27 October 1982) pp 99-204 4-bit PMOS to 32-bit micromainframes are covered in this survey of microprocessor and single chip microcomputers. Each description gives priving and availability, as well as a 'status' assessment of the chip considering its history and market rivals. There is a hardware block diagram for each chip with a list of software functions. The descriptions end with an overview of support hardware and software. Zumchak, E M 'Mastering ~tP write timing creates design alternatives' EDN Vol 27 No 21 (27 October 1982) pp 207-210 To design output ports, it is necessary to understand the timing requirements of the output device and the writetiming sequence provided by the microprocessor. Zumchak considers both these and gives examples of variations that may occur. There are two main styles of read/write timing. Frequent clock edges characterize the 8080/Z80, and symmetry characterizes the 6800/6502. Advantages and disadvantages of both are outlined. TTL logic and gate write strobes are also covered.
Software Arora, R K and Sharma, N K 'On the design of a distributed operating system using a high level distributed programming language' Microproc. Microprog. Vol 10 No 4 (November 1982) pp 247-254 It is possible to build a general purpose system out of an independent microprocessor with distributed storage. However, a problem arises in the writing of distributed programs. This paper presents a methodology
for designing a distributed operating system. The advantages of using a high level distributed programming language as a design, documentation and implementation tool is illustrated.
Ortega, R 'Experimental evaluation of four microprocessor-based advanced control algorithms' Microproc. Microprog. Vol 10 No 4 (November 1982) pp 229-245 As microsystems find application in factory process control, new control theories emerge to take advantage of the software flexibility of stand alone units. This paper presents four algorithms which can be used in low computing power, discrete time environments and for direct digital control. Hardware and software requirements are described. Experimental results on both simulated and real plants are presented and the performance discussed.
Patterson, D A and Piepho, R S 'Assessing RISCs in high level language support' IEEE Micro Vol 2 No 4 (November 1982) pp 9-19 Increasingly complex computer architectures mean longer and more difficult debugging. This paper compares a reduced instruction set computer, RISC I, with five traditional machines. The five are a 68000 (19 MHz), Z8002 (6 MHz), VAX-11/780, 11/70 and C/70. Details of the benchmarks used are given, and the results indicate that the RISC I has the highest performance with the smallest penalty for using a high level language. Stigall, P D, Ziemer, R E and Hudec, L 'A performance study of 16-bit microcomputer-implemented FFT algorithms' IEEE Micro Vol 2 No 4 (November 1982) pp 61-66 Microcomputer tasks in digital signal processing include filtering and control. One form of filtering is performed using a fast Fourier transform, FFT, algorithm. This paper sets out the execution performance of Gold-Bially FFT algorithms on a 16-bit computer - Intel's SBC 86/12A. The author's example can calculate a 256 point transform in less than 400 ms. This
microprocessors and microsystems