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Software overhead for RAM is reduced
6300-gate arrays meet telecommunicationsspeed requirements ECL (emitter coupled logic) gate arrays with 6300 equivalent gates have been launched by FRG-based Fairchild. A member of the FGE series of gate arrays designed for highspeed computer and telecommunications applications, the FGE6300 features internal propagation delays quoted by the manufacturer as 225 ps. It incorporates 560 internal cells and allows 220 I/O signals. The FGE series is, according to Fairchild, the only ECL gate array family that can meet 565 MHz telecommunications system frequency requirements. The new 6300-gate device is stated to consume 30% less power per gate than previous FGE chips, which have equivalent gate counts from 100 to 2840. The FGE6300 is packaged in a
ASICs emulate standard chips &SIC library elements that emulate the functionality of standard LSI and VLSI products have been launched by US-based LSI Logic. The elements, known as 'megafunctions', are proprietary gate-level functions for incorporation into LSI Logic's arraybased or cell-based product lines and are available on the company's LDS design systems. The 'megafunction' range includes ASICs which emulate products by Advanced Micro Devices, Intel and Motorola; the devices emulated include, for example, microprogram controllers, DMA controllers and UARTs. Also in the range are a number of generic logic elements: twos-complement multipliers, carry select adders, three-port adders, barrel shifters, comparators, ALUs, FIFOs and contact addressable memories. 'The availability of these megafunctions means that &SIC designers no longer need to evaluate their designs solely in terms of gates,' explained LSl Logic's John Bern/. 'A design engineer can choose from a substantial list of industry standard LSI and VLSI components and place
460
proprietary multilayer ceramic 301pin grid array (5 cm square) designed to allow operation at speeds over 600MHz without special cooling. Decoupling capacitors can be mounted on the package to reduce noise. The FGE6300 is fabricated using 'essentially the same' 1.5 pm process and exactly the same macro library that has been used in previous FGE devices, says Fairchild. Power dissipation can be controlled using speed-power options, which allow the designer to assign the macro functional switching speed and drive current individually for each source and output of the internal cells. Thus ECL speed can be maximized where needed but overall power dissipation can be kept to a level that accommodates air cooling.
Power consumption is further reduced by on-chip internal termination to - 2 V, says the manufacturer. Circuit design, placement and routing for the gate arrays can be performed on the FairCAD design system at any of Fairchild's local design centres. Design and prototyping of the FGE6300 are already available; production delivery begins in late 1986 for commercial devices (temperature range 0-125°C) and in first-quarter 1987 for military versions (-10°C to 125°C). (Fairchild Semiconductor GmbH, Am Burg4rieden 1, 8090 Wasserburg Am Inn, Munich, FRG. Tel: (08071) 104-232. Fairchild Semiconductor Ltd, 230 High Street, Potters Bar, Hefts, UK. Tel: (0707)
those directly within their circuit net list, similarly to board-level techniques.' 'Megafunctions' are available at all I_gl Logic design centres and support the LL3000, LL5000, LL7000, LL8000 and LLg000 series channelled logic arrays. They can also be used, after modification, in LST20 standard cell, LSC20 structured cell and LCA10000 channelless compacted array chip designs. (LSI Logic Corp., 1551 McCarthy Blvd, Milpitas, CA 95035, USA. Tel: (408) 433-8000. LSI Logic Ltd, Grenville Place, The Rin& Bracknell, Berks RG12 1BP, UK. Tel: (0344) 426544) []
systems have been produced by Hitachi. The devices are intelligent RAMs configured to reduce software overheads, says the manufacturer, providing interprocessor communication paths of greater speed and functionality than in normal singleprocessor systems. The first such device is the HD63310, a l k x 8 bit RAM which may be used either as a dual-port RAM or as two FIFO (first in, first out) memories. The two ports can perform read and write operations independently and simultaneously. Two asynchronous multiplexed or nonmultiplexed microprocessor bus interfaces are included, as are semaphore registers to control RAM access. Other features include four programmable FIFO statuS~pinswhich provide DMA transfer control signals, and two multipurpose interrupt outputs. Access and cycle times for the HD63310 are 200ns and 250ns respectively. Power consumption is quoted as 100mW (maximum) during operation. The device comes in a 48-pin plastic dual in-line package. (Hitachi Ltd, New Marunouchi Building No 5, 1-chome Marunouchi, Chiyoda, Tokyo, Japan. Hitachi Electronic Components (UK) Ltd, 21 Upton Road, Watford, Hefts WD1 7TB, UK. Tel: (0923) 46488) []
Software overhead for RAM is reduced
Hitachi's RAM"
1 kbyte 'smart dual-port
'Smart dual-port RAMs' (SDPRAMs) designed to improve the efficiency of communications in multiprocessor
51111) []
microprocessors and microsystems
ASICs emulate standard chips &SIC library elements that emulate the functionality of standard LSI and VLSI products have been launched by US-based LSI Logic. The elements, known as 'megafunctions', are proprietary gate-level functions for incorporation into LSI Logic's arraybased or cell-based product lines and are available on the company's LDS design systems. The 'megafunction' range includes ASICs which emulate products by Advanced Micro Devices, Intel and Motorola; the devices emulated include, for example, microprogram controllers, DMA controllers and UARTs. Also in the range are a number of generic logic elements: twos-complement multipliers, carry select adders, three-port adders, barrel shifters, comparators, ALUs, FIFOs and contact addressable memories. 'The availability of these megafunctions means that &SIC designers no longer need to evaluate their designs solely in terms of gates,' explained LSl Logic's John Bern/. 'A design engineer can choose from a substantial list of industry standard LSI and VLSI components and place
460
proprietary multilayer ceramic 301pin grid array (5 cm square) designed to allow operation at speeds over 600MHz without special cooling. Decoupling capacitors can be mounted on the package to reduce noise. The FGE6300 is fabricated using 'essentially the same' 1.5 pm process and exactly the same macro library that has been used in previous FGE devices, says Fairchild. Power dissipation can be controlled using speed-power options, which allow the designer to assign the macro functional switching speed and drive current individually for each source and output of the internal cells. Thus ECL speed can be maximized where needed but overall power dissipation can be kept to a level that accommodates air cooling.
Power consumption is further reduced by on-chip internal termination to - 2 V, says the manufacturer. Circuit design, placement and routing for the gate arrays can be performed on the FairCAD design system at any of Fairchild's local design centres. Design and prototyping of the FGE6300 are already available; production delivery begins in late 1986 for commercial devices (temperature range 0-125°C) and in first-quarter 1987 for military versions (-10°C to 125°C). (Fairchild Semiconductor GmbH, Am Burg4rieden 1, 8090 Wasserburg Am Inn, Munich, FRG. Tel: (08071) 104-232. Fairchild Semiconductor Ltd, 230 High Street, Potters Bar, Hefts, UK. Tel: (0707)
those directly within their circuit net list, similarly to board-level techniques.' 'Megafunctions' are available at all I_gl Logic design centres and support the LL3000, LL5000, LL7000, LL8000 and LLg000 series channelled logic arrays. They can also be used, after modification, in LST20 standard cell, LSC20 structured cell and LCA10000 channelless compacted array chip designs. (LSI Logic Corp., 1551 McCarthy Blvd, Milpitas, CA 95035, USA. Tel: (408) 433-8000. LSI Logic Ltd, Grenville Place, The Rin& Bracknell, Berks RG12 1BP, UK. Tel: (0344) 426544) []
systems have been produced by Hitachi. The devices are intelligent RAMs configured to reduce software overheads, says the manufacturer, providing interprocessor communication paths of greater speed and functionality than in normal singleprocessor systems. The first such device is the HD63310, a l k x 8 bit RAM which may be used either as a dual-port RAM or as two FIFO (first in, first out) memories. The two ports can perform read and write operations independently and simultaneously. Two asynchronous multiplexed or nonmultiplexed microprocessor bus interfaces are included, as are semaphore registers to control RAM access. Other features include four programmable FIFO statuS~pinswhich provide DMA transfer control signals, and two multipurpose interrupt outputs. Access and cycle times for the HD63310 are 200ns and 250ns respectively. Power consumption is quoted as 100mW (maximum) during operation. The device comes in a 48-pin plastic dual in-line package. (Hitachi Ltd, New Marunouchi Building No 5, 1-chome Marunouchi, Chiyoda, Tokyo, Japan. Hitachi Electronic Components (UK) Ltd, 21 Upton Road, Watford, Hefts WD1 7TB, UK. Tel: (0923) 46488) []
Software overhead for RAM is reduced
Hitachi's RAM"
1 kbyte 'smart dual-port
'Smart dual-port RAMs' (SDPRAMs) designed to improve the efficiency of communications in multiprocessor
51111) []
microprocessors and microsystems