drain technologies for the scaling of nanoscale CMOS device

drain technologies for the scaling of nanoscale CMOS device

Solid State Sciences 13 (2011) 294e305 Contents lists available at ScienceDirect Solid State Sciences journal homepage: www.elsevier.com/locate/sssc...

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Solid State Sciences 13 (2011) 294e305

Contents lists available at ScienceDirect

Solid State Sciences journal homepage: www.elsevier.com/locate/ssscie

Source/drain technologies for the scaling of nanoscale CMOS device Yi Song*, Huajie Zhou, Qiuxia Xu Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

a r t i c l e i n f o

a b s t r a c t

Article history: Received 12 October 2010 Accepted 2 December 2010 Available online 13 December 2010

Continuous shrinking CMOS device into 21 nm technology node is facing fundamental challenges. The International Technology Roadmap for Semiconductors (ITRS) forecasts specific requirements to realize acceptable CMOS performance for the semiconductor industry. The innovations of various source/drain technologies are considered to be indispensable for the continuous scaling of CMOS device due to the requirements of high-performance and effective suppression of short channel effects. One of the key points is to realize ultra-shallow junction with steep concentration profile and low resistivity. There are many innovative solutions including advanced doping technologies and annealing technologies for ultrashallow junction formation. Additionally, new source/drain structures such as raised source/drain and Schottky barrier metal source/drain, and advanced silicidation technologies also serve as the important options. The state-of-the-arts of these new technologies are extensively discussed from the view point of technical innovation and performance gain. Source/drain technologies are promising and active areas of device research down to 21 nm technology node and even beyond. Ó 2010 Elsevier Masson SAS. All rights reserved.

Keywords: Nanoscale CMOS device Ultra-shallow junction Raised source/drain Schottky barrier source/drain

1. Introduction As MOSFET feature dimension shrinks down to 21 nm range, nanoscale processes encounter tremendous difficulties, for instance, severe short channel effects, degraded driving ability, boron penetration and poly-silicon depletion, high-field effects, direct gate tunneling current and high series resistance etc. Keeping Moore’s law valid encounters unprecedented difficulties. Table 1 gives the main projected targets for high-performance logic technology at 21 nm technology node proposed by ITRS [1]. The 21 nm technology node will be realized in 2015 with the physical gate length only 17 nm. Tremendous technical innovations in new material, new process techniques, new device architectures are required to promote CMOS device ahead towards 21 nm technology node. Source/drain region as a key component in MOSFET structure receives considerable attentions. Fig. 1 summarizes the main difficult challenges with source/drain in the scaling of traditional planar bulk MOSFET. The key of source/drain (S/D) engineering is to form abrupt and ultra-shallow junction, however, the ultra-shallow source/drain junction brings about extremely high parasitic resistance and contact resistance [2]. Significant challenges exist in silicides as device scaling, such as high sheet resistance, Fermi level pinning, linewidth effects, agglomeration for thinner silicides, high

* Corresponding author. E-mail address: [email protected] (Y. Song). 1293-2558/$ e see front matter Ó 2010 Elsevier Masson SAS. All rights reserved. doi:10.1016/j.solidstatesciences.2010.12.002

thermal budget, high Schottky barrier, poor phase control and interface quality and so on [3]. The dopants activation concentration is limited by its solid solubility. Moreover, the fast diffusion of boron makes ultra-shallow source/drain junction of pMOS more challenging. Intensive investigations such as ultra-low energy ion implantation with large beam current, surface pre-amorphous [4] and laser annealing technology [5], make it possible to obtain abrupt and uniform ultra-shallow junction. Moreover, raised source/drain and metal Schottky barrier source/drain also serve as potential solutions. These innovative technologies are extensively discussed below. 2. Ultra-shallow junction formation Source/drain junction depth scales continuously together with the gate lengths in order to suppress short channel effects. The formation of ultra-shallow junction with abrupt doping profile and low sheet resistance is pre-requisite. However, there are tremendous technical challenges such as the transient-enhanced diffusion [6] and solid solubility limitation [7] for achieving ultra-shallow junctions using the conventional doping strategies by the combination of ion implantation and spike annealing. Advanced doping technologies to obtain shallow doping profiles such as C coimplantation, heavier implantation dopant sources (cluster ion), plasma doping and molecular monolayer doping, and advanced annealing techniques to activate the dopants without causing significant diffusion such as flash and laser annealing are explored.

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Table 1 High-performance Logic Technology Requirements for extended planar bulk at 21 nm technology node proposed by ITRS 2009 edition. MPU physical gate length (nm) 17

Junction depth or body thickness (nm) 7.3

Electrical Equivalent Oxide Thickness in inversion (Å) 8.2

Effective parasitic S/D series resistance (U mm) 110

Average Vdd (V) 0.81

Maximal Ion/Ioff (mA/mm) 1680/0.1 (nmos), 1377/0.1 (pmos)

Saturated threshold voltage (V) j0.302j

Intrinsic delay (ps) 0.45 (nmos)/0.55 (pmos)

The junction uniformity, metal contamination, reliability and repeatability, dosimetry, junction leakage and subsequent process integration of these advanced doping and annealing techniques should be well considered. The main issues and recent progresses on these advanced technologies are discussed below. 2.1. Advanced doping technologies Co-implantation which include phosphorous (P) or arsenic (As) together with low energy carbon (C) implantation into crystalline Si is used for 45 nm nMOS ultra-shallow junction formation [8]. C coimplantation gives more abrupt, shallow and well activated junctions than dopant-only cases. A known drawback of this kind of co-implantation is junction leakage caused by Carbon deep levels, therefore, it is necessary to optimize the location and amount of Carbon with respect to Si interstitials [9]. High energy silicon pre-amorphous process and fast anneal step are necessary to locate the C atoms in substitutional sites. The role of C in reducing enhanced diffusion of dopants implanted in pre-amorphous Si is to trap Si interstitials that responsible of dopants diffusion [10]. Abrupt and well activated doping (P) profiles are realized by localizing the C profile at an optimum position. The junction with 20.5 nm in depth, Rs ¼ 318 U/ , and a 3 nm/dec trailing slope is achieved. Intensive efforts have been made to extend the co-implantation scheme into sub45 nm gate length devices [11]. The key of this scheme is the combination of co-implantation of a diffusionretarding species (i.e. Carbon) and Bþ for pMOS or Pþ for nMOS with a high temperature, millisecond annealing process after the conventional spike annealing. Thus reduced junction depths with abrupt profiles and improved dopant activation are achieved. Submelt laser annealing would further improve junction activation and reduce gate depletion. Fig. 2 shows the two-dimensional scanning spreading resistance microscopy (SSRM) images of

activated carrier concentration for a BF2 implanted device (left) and a C co-implanted device (right) after spike annealing. As for C co-implanted case, the boron vertical diffusion is significantly reduced as the SDE vertical junction depth is dramatically reduced from 38 to 14 nm and the heavily doped drain junction depth is decreased from 90 to 82 nm. In addition, C coimplant also strongly suppresses the boron lateral diffusion such that the gate/SDE overlap is shrunk from 22 to 10 nm. The overlap capacitance is reduced due to shallower junction depths and reduced lateral diffusion. The higher Ion is the reflection of lower series resistance due to improved dopant activation. It is more difficult to fabricate ultra-shallow pþn junction because of the lowmolecular weight and fast diffusion velocity of Boron. High-mass dopant species such as B18Hþ x ion implantation is another attracting solution for ultra-shallow source/drain formaþ tion [12]. B18Hþ x shows the same or better characteristics than B in junction depth and sheet resistance. Post-processing electrical measurements of the pMOS implanted with B18Hþ x show that they performed with nearly identical characteristics as ones implanted with Bþ. B18Hþ x implantation could be used to produce ultrashallow junctions for MOSFET fabrication at production-worthy throughputs with less energy contamination. Pulsed plasma doping (P2LAD) is another doping technique for the formation of ultra-shallow junctions in silicon wafers [13,14]. In the P2LAD technique, a pulsed negative voltage applied to the silicon substrate creates plasma containing the desired dopant species and accelerates the positive dopant ions from the plasma toward the substrate, where they are implanted. BF3 plasmas are used to form pþn junctions, while AsH and PH plasmas are used for the formation of nþp junctions. The wafer bias and implant dose determine the junction depth and sheet resistance. Good sheet resistance uniformity, charging performance, structural quality, and photoresist integrity are observed. The P2LAD process is compatible with CMOS device processing, and do not generate

Fig. 1. Difficult challenges with source/drain in CMOS device at 21 nm technology node.

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Fig. 2. The SSRM images of activated carrier concentration for a BF2 implanted device (left) and a C co-implanted device (right) after spike annealing [11].

much sources of damage. Silicon-on-insulator (SOI) nMOS with a 50 nm-length metal gate are fabricated [15], which the source and drain extensions (SDE) are formed by such plasma doping technique. A laterally abrupt source/drain junction with low sheet resistance is obtained without additional activation annealing. In-situ Helium pre-amorphization (He-PA) combined with flash-lamp annealing or laser annealing could be introduced to plasma doping (PD) method [16]. High dose and ultra-shallow asdoped profiles are optimized by adjusting B2H6 PD conditions. The junction depth and optical absorption rate in the amorphous layer are controlled by the He-PA conditions. Good abruptness of 1.5e2.4 nm/decade at Xj of around 10 nm and 750 U/, sheet resistance are achieved by this method. It is necessary to utilize conformal doping to form the extension on the sidewalls of fins in advanced CMOS multi-gate device. Good conformal projection could be achieved by plasma doping. However, the process controllability and sputter erosion need to be carefully addressed. A self-regulatory plasma doping (SRPD) technique with B2H6/ Helium gas plasma has been developed that provide conformal doping for fins and precisely controllable ultra-shallow doping for planar FET [17]. As shown in Fig. 3, a zero degree angle of ion’s incidence to the wafer surface from the plasma occurs with random radicals. Boron ion implantation, sputtering and boron radical adsorption are simultaneously occurred at the top surface of fin while the boron radical adsorption is the main process at the side surface. The ion density is extremely low because of low pressure, consequently, ion implantation and sputtering at the top surface is drastically suppressed compared to conventional plasma doping process. Therefore, conformal doping is achieved. Recently, the combination of molecular monolayer doping (phosphorus or boron atoms) and conventional spike annealing is developed for the formation of sub-5 nm ultra-shallow junctions

[18]. The junctions formed by this process which show a minimal junction leakage current of less than 1 mA/cm2, indicating no defects was generated during the process. As shown in Fig. 4, the key of monolayer doping (MLD) process is the formation of self-assembled dopant-containing monolayer on the crystalline silicon surfaces, followed by the diffusion of dopants from the surface into the lattice by a thermal annealing step. In detail, 4 in. p-type Si wafers are first treated with dilute hydrofluoric acid (1%) to remove the native SiO2. The Si surface is then reacted with diethyl-propylphosphonate and mesitylene as a solvent (25:1, v/v) at 120  C for 2.5 h to assemble a P-containing

Fig. 3. The schematic of the mechanism of the new conformal plasma doping method [17].

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Fig. 4. Process schematic for the wafer-scale monolayer doping approach [18].

monolayer for nþp junction, while allylboronic acid pinacol ester as a solvent (25:1, v/v) at 120  C for 2.5 h to enable a B-containing monolayer for pþn junction. Then the substrate is capped with SiO2 followed by spike anneal in Ar ambient to enable the formation of ultra-shallow junction. The junction uniformity is determined by the temperature homogeneity of the spike anneal tool. This technology utilizes the crystalline nature and self-limiting surface reaction properties of silicon to form self-assembled dopant monolayers, combining with conventional spike annealing for the diffusion of dopants. The transient-enhanced diffusion effect is minimized and sub-5 nm depth of nþp and pþn junctions with low sheet resistivity are demonstrated, even for fast diffusing dopants such as phosphorus. This surface-doping technology is not only useful for the nanoscale controlled doping for the contact extension of planar MOSFETs, but also may be applicable for the conformal and deterministic doping of nonplanar nanoscale device structures, such as FinFETs or nanowire-FETs. 2.2. Advanced annealing technologies Millisecond anneal (MSA), such as Flash-Lamp Annealing (FLA) and Laser Spike Annealing (LSA) are considered to be the promising candidates to substitute for spike rapid thermal annealing (RTA) as the source/drain dopant activation technology for sub-45 nm node [19]. Flash-lamp annealing (FLA) technology which reduces the time of the heating cycle to within the millisecond range is used to achieve abrupt profiles by strictly controlled diffusion of dopants [20]. The annealing time of FLA is 1e3 ms, about three orders of magnitude shorter than that of RTA. The dopant concentration can exceed the maximum carrier concentration obtained by conventional RTA or furnace annealing. The waver length in the Xe flash lamp is shorter than the wavelength at the absorption edge of Si. Therefore, the Xe flash

lamp is suitable for heating Si as the heat sources, and the luminescence spectra are white light. Fig. 5 shows the schematic of the FLA apparatus. This apparatus is composed of Xe flash lamps and W halogen lamps for assistant heating. The front of the substrate is heated by e Xe flash lamps and the back of the substrate is heated by W halogen lamps. The assist heating temperature is set at 200e500  C using the W halogen lamps. After 30 s, the Xe flash lamps are used for irradiation with an incident radiant energy density above 20 J/cm2. The temperature at the Si surface reaches 1000  C or above due to the Xe flash lamp. FLA is found to be an excellent technology for the activation of As, B, and In. The dopants activity using FLA is 4e5 times larger than that using RTA. Sub-15 nm ultra-shallow junction could be formed by extremely high-rate ramp-up and ramp-down thermal process. Flash annealing combined with solid phase epitaxial (SPE) regrowth could further improve the activation of B at high temperature. The SPE is carried in nitrogen ambient anneals at a furnace (450  C for 17 h) and a flash annealing tool for two step annealing. An active concentration of 6.5  1020/cm3 which is well above the electrical solubility limit of B is obtained [21]. The leakage in one step flash annealing SPE regrowth junction is caused by the end-of-range (EOR) damage left beyond the amorphousecrystalline interface. A second Flash anneal at higher peak temperatures anneals out the EOR defects while causing minimal diffusion and deactivation of B, consequently, results in nearly two orders of magnitude reduction in leakage currents compared to a single Flash SPE [22]. There are three major concerns related to flash-lamp annealing: process controllability, source/drain activation, and silicidation [23]. Even though non-equilibrium process of FLA, thermal status will saturate after some dummy wafer processing, and it is possible to create the stable condition at standby stage without wafer proceeding. S/D activation with longer pulse FLA results in no

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Fig. 5. Schematic of FLA apparatus [20].

dopants diffusion and small thermal stress annealing. Ge preamorphous step could enhance the flash spectra absorption, therefore resulting in 2e3 times activation enhancement [24]. Also, FLA has a capability to achieve very flat and thin NiSi layer for silicidation process. Therefore, FLA has a large capability to be a standard annealing technology for future generation device manufacturing. There are also some significant challenges with flash-lamp annealing, for example, the mechanical stresses generated by almost instantaneous heating of the wafer surface to very high temperatures. These stresses are considered to be the sources of high levels of slip defects which resulting in high leakage currents. Some of these stresses could be tempered through preheating the wafer and controlling heat energy through flash pulse width adjustment and pulse shaping. The pattern-related temperature non-uniformities are also severe issues due to insufficient heat diffusion.

Laser annealing, in which a laser melts a pre-amorphous surface layer and causes the dopants to be distributed throughout the region of melted silicon, is another promising candidate for the formation of ultra-shallow junctions. Higher laser fluence could increase the degree of activation, however, results in deeper junction. Using multiple-pulse laser annealing with moderate density of laser power can achieve a defect-free pþ/n junction with a good degree of activation of boron without compromising the junction depth [25]. The fabrication process starts with pre-amorphous implantation of Siþ ions to n-type (100) silicon wafers, then Bþ ion implantation is carried out, followed by an irradiation by a KrF excimer laser with a wavelength of 248 nm. The laser pulses are produced at a repetition frequency of 1 Hz and the pulse duration employed is 23 ns. The laser fluence is carefully adjusted to melt amorphous silicon layer but not monocrystalline silicon. The junction depth could be easily controlled by varying the pre-amorphous layer depth. The melt laser process may cause deformation of fine patterns by melting the gate stack and Si substrate under the isolating oxide. Moreover, it seems complicated because it requires forming an absorber layer and pre-amorphous implantation (PAI) prior to annealing to maintain the physical integrity. A non-melt laser spike annealing which keeps the peak temperature below the Si melt temperature is developed to activate source/ drain junction [26]. Unlike the conventional laser annealing, no additional layers are formed and good heating uniformity is achieved, therefore, completely compatible with conventional CMOS process flow. The process suppresses the transient-enhanced diffusion and avoids dopants to reach the end of the damage range of the amorphous layer by keeping the junction profile inside the PAI region during the re-growth of the Si from amorphous/crystalline interface. The fabricated 50 nm device by this method shown in Fig. 6 demonstrates 10% IoffeIon improvement and no appreciable degradation of gate oxide integrity and junction leakage comparing to control devices by conventional RTA. It is attracting to lower the annealing temperature and enlarge the process window of laser spike annealing (LSA). A novel junction profile engineering technique that uses LSA is implemented to modulate the junction profile with lower temperatures and wider process window [27]. Dramatic reduction of source-drain parasitic resistance with low sensitivity to LSA temperature is achieved, consequently, resulting in enhanced Ion. Laser-only annealing has been integrated into high-k/metal gate process to limit defect creation, reduce pre-doped poly-silicon resistance, and obtain good capping/high-k intermixing due to low thermal budget. Less oxide re-growth results in EOT reduction and less work function roll off comparing with traditional spike annealing [5]. Low temperature MSA at source/drain activation is effective to assist the activation of halo impurities with co-implant for nMOS, and it is also effective for pMOS with elevated SiGe S/D [28] to avoid the strain relaxation. Low temperature MSA and co-implant for nMOS and tilt-and-twist extension implantation with MSA and co-implant for pMOS are developed to improve device performance [29]. Fig. 7 shows the concept of tilt-and-twist extension ion implantation. With this configuration, an overlapped shallow (A) and a highly concentrated (B) (twice as high as (A)) extension profile are obtained and high overlap controllability and reduction of parasitic resistance could be achieved. High-performance 34 nm gate length bulk CMOS transistors with drive currents of 1282 (nMOS)/835 (pMOS) mA/mm and 100 nA/mm off-current at Vd ¼ 1 V are demonstrated. 3. Optional source/drain structures

Fig. 6. Cross-sectional TEM image of fabricated MOSFET: activated by LSA at 1.45 kW (1300  C) in 80 ms [26].

Optional source/drain structures provide other means to satisfy the requirements for high-performance application. Raised source/

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Fig. 8. Device structure of raised source/drain MOSFET [31].

Fig. 7. Concept of tilt-and-twist extension ion implantation. (A) shallow and (B) high concentration extension profile can be achieved [29].

drain or metal Schottky barrier source/drain are promising candidates that may provide with both low resistance and suppressed short channel effects simultaneously.

Another problem with the conventional-order source/drain formation is the difficulty to control xj,eff due to the sensitivity to SEG process time [33]. To achieve such eS/D structure and precisely controlled xj,eff, a reverse-order source/drain (ReS/D) with a self-limited SEG-Si film which is stuffed into a narrow slit underneath a SiN sidewall is developed to improve both the SCE and parasitic resistance [34]. Fig. 10 shows the schematic figures of conventional and reverseorder source/drain formations with both elevated source/drain extension (eSDE) and eS/D. After STI formation and channel doping, the gate insulator of SiON film is formed. After a notched gate electrode formation, the offset liners and dummy sidewall were formed. Then, after an isotropic wet etching process of the liner film, the tunneling SEG-Si film with the thickness of only 4 nm is

3.1. Elevated source/drain To aggressively suppress the short channel effect (SCE), it is required to reduce an effective junction depth (xj,eff ), however, the parasitic resistance increases. The elevated source/drain (eS/D) technique as shown in Fig. 8 is one of the solutions to this problem. Advanced multi-gate device such as FinFETs are in pressing need for this technique because the narrow extension regions impose large parasitic resistance [30]. Silicon selective-epitaxial growth (SEG) decreases overall parasitic resistance by providing more silicon for the source/drain silicide formation. However, it complicates the CMOS integration process as the deposition rate dependent on crystallographic direction and doping. Moreover, it suffers from severe problem of increased fringe capacitance. A ultra-high vacuum-CVD technology accomplish with selective epi-growth raised source/drain extension (RSD,ext) process is developed to reduce parasitic resistance and fringe capacitance simultaneously [32]. Elaborate facet-structure-control is explored. Selective epi-growth only on S/D-extension crystalline surface while no growth onto gate-poly sidewall is done by utilizing different incubation times for poly-Si and mono-Si as shown in Fig. 9. The advanced millisecond annealing with limited additionalslight-diffusion is precisely controlled by pre-heat/post-heat temperature TPRE. A relatively high TPRE is benefit for significant reduction of the sheet resistance and junction leakage. Multi-ionspecies are applied for tailoring S/D profiles as slightly deeper in depth direction while enhancing lateral-steepness. This careful source/drain design enables further reducing halo-dose, reducing junction leakage at the bottom region and increasing dopant concentration near the NiSi interface that contributes to further on current enhancements.

Fig. 9. Cross-sectional TEM image after selective-epitaxial growth upon SDext. The selective growth is done by utilizing different incubation times for poly-Si and mono-Si [32].

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Fig. 10. Schematic figures of process flow for (a) conventional- and (b) reverse-order source/drain formations with both eSDE and eS/D [34].

achieved for the eSDE regions, in which a fringing capacitance could be almost negligible. Ion implantation is carried out to dope the impurities into a simultaneously-formed 25-nm-thick SEG-Si film for the eS/D regions. After the removal of dummy sidewall film, the SEG-Si films are doped by various ion-implantation doses. After a final sidewall formation, a spike annealing is carried out with the high temperature at 1050  C. Finally, interconnects are implemented after the NiSi formation. The fabricated sub-10 nm CMOS devices show improved Ioff/CV/I characteristics due to the suppressions of both the short channel effect and parasitic resistance. Accompanying Co-implantation and/or pre-amorphous of source/drain region with raised source/drain technology would be

another way to achieve both low parasitic resistance and low junction leakage. Carbon cluster co-implantation enables to enhance SDE boron concentration at the silicide interface and reduce deep halo dosage as well as junction leakage. Pre-amorphous of source/drain region by C or Ge implantation could control the extension doping depth profile and reduce Schottky barrier height between silicide and source/drain extension. The combination of these technologies achieves improved Ion/Ioff characteristics for CMOS device with an aggressively reduced silicide position down to 5 nm from the gate edge [35]. Elevated S/D could also be achieved by epitaxial growth SiGe (for pmos) [36] or SiC (for nmos) [37] to induce compressive and tensile stress respectively, for additional performance benefits.

Fig. 11. Schematic outline of a typical Schottky barrier pMOS transistor fabrication process [47].

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Fig. 12. Process flow and XTEM image of NiSi SB nMOS featuring gate length of 39 nm and ultra-thin gate oxide of 1.2 nm [49].

Low-field mobility enhancement of 140% is observed with the longitudinal compressive stress in the channel exceeding 1 GPa [38]. While 35% electron mobility improvement at tensile stress of 615 MPa is observed for SiC S/D nmos [39]. The robust improvement is explained by band repopulation and transverse mass modulation. Besides local strain for enhanced mobility, this technique features superiorities such as high dopants activation and small barrier height for low-contact resistivity, low-temperature processing for compatibility with high-k dielectrics and metal gate electrodes, and abrupt Junctions for small overlap resistance. 3.2. Schottky barrier source/drain As mentioned previously, serious challenges in the source/drain are high leakage current, junction punch through, and high parasitic resistance/capacitance. Traditional pn junction source/drain have some inevitable deficiencies, such as complicated process, large parasitic capacitors and tight compromises between thermal budgets and parasitic resistance [40]. Another critical problem with traditional p-n junction source/drain is the high activation temperature which is not well compatible with metal gate/high-k integration, thus prohibits further scaling. Schottky Barrier MOSFET (SBMOS) offers an alternative technology in which the source and drain are formed using Schottky Barrier contacts, usually implemented with metal silicides, resulting in low parasitic resistance and high transconductance [41]. Meanwhile, Schottky barrier source/drain process features low annealing temperature. It becomes promising solution as long as the thermal and phase stability issues are well solved.

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SBMOS could provide high driving current as well as low leakage current if the intrinsic Schottky barrier is sufficiently low. Therefore, it is urgent to find proper metal with low Schottky barrier for nMOS and pMOS respectively. So far, the most promising material for nMOS includes ErSix [42e44], YbSi2-x [45] and DySix [46] while PtSi [42] for pMOS. The typical fabrication process for Schottky barrier MOSETs is much simplified comparing with traditional pn junction S/D MOSFETs [47]. Fig. 11 shows the schematic outline of a Schottky Barrier pMOS fabrication process. After LOCOS isolation formation, the lithography and etch of gate stack are performed. Then thin oxide spacers and Pt-silicide with a low barrier (0.23 eV) for pMOS source/drain junction are formed. No implantation is used in this process. The fabricated pMOS device with gate length less than 30 nm exhibits a cut off frequency of 280 GHz. The manufactured 20 nm gate length Er/Pt silicide n/p type SBMOS show enhanced short channel characteristics due to the low Schottky Barrier (SB) between source and drain, giving very low leakage current and high on current (550 mA/mm at Vg ¼ 3 V and Vd ¼ 2 V) [33]. N2 annealing is beneficial for eliminating the interface traps in the erbium silicide thus improves subthreshold characteristics. Er-silicide formation with W capping smoothes the ErSi2-x film without any pinhole or pyramidal defect and reduces electron barrier height to 0.41 eV [48]. YbSi2-x is even more suitable for N-SBMOS as it provides a higher drive current and a lower leakage current (Ion/Ioff ratio ∼107 and Ss 75 mV/dec). This is attributed to lower electron barrier height (0.27 eV) and higher hole barrier height (0.82 eV) of the YbSi2-x/Si Schottky contact and smooth YbSi2-x/Si interface [45]. Using rare earth metal silicide materials with low SBH could achieve an inherent improvement in transistor drive current. However, the rare earth metal is not suitable to implement into mass production due to its high price, and it also sophisticates the CMOS integration due to the requirement of dual rare earth metal silicide formation. Mid-gate material such as NiSi [49] which has low resistivity, linewidth effect, Si consumption and temperature of formation is more attracting to fulfill CMOS application as it makes the fabrication process less cost and simplified. NiSi is inappropriate for directly being as the source/drain silicidation material due to large Schottky barrier between NiSi and both n and p substrate. Varies technologies are explored to reduce the effective SB barrier height, such as by introducing an interfacial layer of doping or a thin insulator between the metal S/D and the channel region. MOSFETs with fully NiSi source/drain contacts and ultra-short and defect-free source/drain extension (SDE) show that arsenic/ boron segregation during silicidation lead to strongly improved

Fig. 13. Id-Vg (a) and Id-Vd (b) characteristics of PSS CMOS with 39 nm gate length [49].

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Fig. 15. Band diagram illustrating the high-k dipole for (a) AlOx and (b) LaOx containing diodes. Dipole at the high-k/SiO2 interface can tune the SBH more p-type (a) or n-type (b) [62].

Fig. 14. (a) Process sequence for fabricating an N-FET with Sb segregated S/D regions as well as a control N-FET. Cross-section schematic of (b) control N-FET and (c) N-FET with Sb segregation in the nickel silicided S/D regions [61].

suppress the formation of active deep-level defects [54]. Therefore, incorporating C into NiSi silicide could improve the morphological and phase stability of NiSi:C contacts. Moreover, incorporating C in combination with B or As in Si could influence the effective SBH of NiSi [55]. Carbon would inhibit B from diffusion and keep B assembling at interface which yield desired high values of 4bn (>0.9 eV) as long as the anneal temperature is above 600  C, while C also increases As segregation at the silicide/Si interface which results in an effective tuning of 4bp above 1.0 eV. An amazing conclusion is that an arbitrary kind of elements which are of no use as dopants in Si technology such as group II elements may be promising candidates for modulating Schottky barrier as long as it can generate a large dipole at the interface. Other elements are also feasible for modulating Schottky Barrier by dopant segregation. Implantation of S or Se prior to silicidation (IBS) could also lead to effective reduction of contact resistance and SB height (as low as 0.12e0.13 eV) at the NiSi/n-Si interface [56]. Se is more robust to withstand high temperature annealing than S to restrict the outdiffusion. Incorporating Antimony (Sb) as the solid dopant segregation source into Ni silicide on Si (100) is attractive to achieve low contact resistance by tuning Schottky barrier as low as 0.074 eV [57]. The fabrication flow of nickel silicide source/drain nMOS with Sb incorporation is shown in Fig. 14. A thin solid Sb layer is deposited beneath a metallic nickel layer prior to source-drain silicidation. The very high concentration of Sb at the NiSi/Si interface reduces the effective SB height and parasitic series resistance, leading to enhanced drive current performance without degradation in the leakage current. Fluorine pre-silicidation implantation (IBS) is proved to be effective to reduce leakage current and electron Schottky barrier of NiSi/Si to 0.12 eV. More importantly, the lateral source/drain extension junction depth as well as SCE are reduced due to F segregation at the NiSi/Si interface [58,59]. Incorporation NiSi with metallic elements may also contribute to parasitic resistance reduction. It was found that the NiAl-alloy silicide provides an effective Schottky Barrier height lowering (250 meV) on n-Si(001) substrates [60].

device characteristics. This could be attributed to a strong conduction/valence band bending at the contact interface induced by a very thin, highly doped silicon layer formed during the silicidation. The SB width between source/channel would be effectively thinned out during on-state while the one between drain/channel would be broadened and elevated during off state, therefore, achieve excellent on and off state. The Schottky barrier modulation effects by dopants segregation could be explained by dipoles which generate at the mid-gap metal silicide/silicon interface, through both first principles calculations and experimental methods [50]. Ion implantation before (IBS for nMOS) [51] and after (IAS for nMOS and pMOS) [52] silicidation are two ways to modulate NiSi/Si Schottky junction. Scheme IBS is relatively simple in processing, but the silicidation process is dopant-dependent, while scheme IAS addresses the adverse effects of dopants on silicidation by separating silicidation from dopant incorporation [53]. In the IBS process which uses silicidation to induce dopant segregation, most B atoms remain in the bulk NiSi layer after silicidation, while in the IAS process in which silicide used as the diffusion source, many B atoms migrate to the Si side resulting in a higher B concentration at the interface after a post-implantation drive-in anneal. Therefore, significant SBH changes occur in the IAS process as B atoms replace Si atoms on the silicon side of the interface, generating dipoles to comfort SBH. As atoms preferentially stay on the silicon side of the interface due to lower total energy, therefore, in both IAS and IBS processes, As atoms can migrate into the Si layer and pileup at the interface, resulting in lager SBH modulation compared with the B doped case. Fig. 12 shows the typical process flow and XTEM image of NiSi SBNMOS by IBS dopants segregation. Fig. 13 shows the Id-Vg (a) and Id-Vd (b) characteristics of SB process strained Si (PSS) CMOS with 39 nm gate length, indicating excellent performances are obtained. Carbon at the NiSi:C grain boundaries and NiSi:C/Si interface could modify the grain-boundary and interfacial energies and

Table 2 State of the art of Schottky barrier lowering by dopants segregation, the data are collected from the typical values reported recently. Electron Element Schottky barrier (eV) Ref

Al 0.25 [60]

Hole As 0.27 [62]

In 0.36 [62]

P 0.22 [62]

S 0.12 [56]

Se 0.13 [56]

Sb 0.074 [57]

F 0.12 [59]

As & C 0.12 [55]

B 0.16 [62]

B&C 0.14 [55]

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Fig. 16. Schematics of (a) DSS-nFETs with N modulated NiSi2 and bulk NiSi. Inset shows the N diffusion barrier resulting in phase modulation of NiSi and (b) DSS-pFETs with conventional NiSi [63].

Table 2 summaries the state of the art of modulating Schottky barrier between NiSi/Si by dopants segregation. As shown in Table 2, most researches focus on electron Schottky barrier for nmos. The best result is obtained by Sb segregation (0.074 eV), indicating a promising application of Sb for SB nmos. C co-implantation with B segregation benefits both from the reduction of Schottky barrier of NiSi/p-Si and the improvement of thermal stability. An arbitrary kind of elements as long as it can generate a large dipole at the interface may be suitable for SB modulation as mentioned previously. Therefore, the SB height modulation by using single metal (TaN) and dual interfacial layer of SiO2/high-k (AlOx or LaOx) dipoles resulting in SBH < 0.1 eV from the conduction bandedge (CBE) and SBH < 0.2 eV from the valence band-edge (VBE) has been reported [62]. Fig. 15 illustrates the SBH dipole-tuning effects. AlOx and LaOx generate complementary dipole at the higk-k/ SiO2 interface that can be thought of as modulating the depletion region field or the metal work function. The band-edge SBH reduction with a minimal increase in process complexity enables Cu metallization directly to the source/drain region. In addition, dual phase-modulated Ni silicide is effective for SB and series resistance reduction in dopant segregated source/drain (DSS) nMOS [63]. As shown in Fig. 16, selectively form interfacial epitaxial Si-rich NiSi2 by pre-silicide Nþ 2 implant could reduce the electron Schottky Barrier from 0.7 eV to 0.34 eV, while maintaining a low resistive bulk NiSi at the same silicide formation temperature. Devices using dual phase-modulated NiSi show enhanced thermal stability and saturation gm as well as low series resistance. The process features low cost and CMOS compatibility, thus is promising for CMOS integration. The DSS MOSFET suffers its bottle-neck of tunneling through the SDE regions and band-to-band tunneling that limits the design space. The eS/D MOSFETs provide a considerable increase in contact area and allow one to use both high doping and low doping in different portions of the S/D regions to reduce both the leakage flow and specific contact resistivity. Therefore, the eS/D structure ends up prevailing both in terms of leakage design space and on-state performance for meeting low-standby-power leakage specifications. For high performance (HP) design, the performances of optimized DSS and eS/D MOSFETs are shown to be very similar [64]. Thus, the optimal source/drain design for HP is more likely to be decided by practical considerations such as integration compatibility. As the linewidth and thickness of NiSi scales continuously, thermal stability such as agglomeration and NiSi2 nucleation becomes a critical issue [65] among other challenges mentioned previously. There exists a critical thickness (3.7 nm) below which forms epitaxylike nickel-silicide layer on Si (100) with low resistivity and good thermal stability [66]. However, such thin NiSi is not applicable due to extremely large total resistance. Traditional twostep RTA encounters problems of excessive silicidation due to oxygen contamination [67]. An optimized RTA scheme of a higher

temperature RTA1 and a spike anneal RTA2 combining within suit chemical dry clean improves electrical properties and thermal stability of NiSi [68]. The activation energy for NiSi agglomeration is lower on singlecrystal SOI than on annealed poly-Si, and agglomeration becomes severe when thickness of NiSi getting smaller. Pre-annealing the poly-Si would delay the agglomeration of the NiSi films. Indicating that pre-amorphization of source/drain region may be a meaningful method for suppress NiSi from agglomeration. Various additive alloying elements are studied their effects on formation and morphological stability of nickel monosilicide [69]. Mo, Re, Ta and W are most efficient to retard NiSi agglomeration while Pd, Pt and Rh are most efficient to retard the formation of NiSi2. Among them, Pt produces the most promising results that raise the silicidation temperature as high as 750  C [70]. Pt incorporation not only improves thermal stability of NiSi but also achieves low contact resistance (RC) at silicide/Si interface below 108Ucm2 [71]. For pMOS, Ni1-xPtxSi films enable RC reduction due to the segregated Pt and B at silicide/Si interface. First principles calculation indicates that RC reduction could also be explained by higher boron activation beyond solubility limit at silicide/Si interface [72]. For nMOS, the gradual RC reduction could be explained by the increased silicide granularity or Pt-As bond creation [73]. Thermal stability could also be improved by non-metal elements incorporation such as high dose Ge ion implantation for NiSi on poly-silicon [74] or silicon [75]. A very smooth NiSi/Si interface with low interface energy is obtained due to Ge atom pileup at the NiSi/Si interface. A drawback of this method is the slightly increased leakage due to Ni diffusion and dissolution enhancement caused by Ge ion implantation induced extra defects. Carbon ion implantation with high dose would also achieve good thermal stability of NiSi as mentioned previously [76]. However, a balance between thermal stability and junction leakage is needed because the implanted C may result in crystal defects due to the low solid-state solubility. Another drawback is the slightly increased sheet resistance owing to the C segregation at the grain boundaries. Additional Pt on epi-Si:C source/drain could greatly enhances thermal stability of Ni(Pt)Si:C, thus raises the silicidation temperature and achieves low sheet resistance of Ni-Pt/Si0.998C0.012 [77]. Recently, nickel nitride (NiNx) is found to be a possible substitute for pure Ni to improve the thermal stability of NiSi [78]. The amorphous Si-N layer at the nickel nitride/Si interface retards Ni diffusion into the Si substrate, thus keeping the sustain temperature as high as 700  C. 4. Conclusions Continuous scaling of CMOS device according to Moore’s law needs to boost on current, lower off current, suppress the short channel effects and increase the uniformity and reliability of device

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performance. Innovations are pre-requisite in various aspects of MOSFET structure. Among them, source/drain is of much significance. Major difficulties with source/drain in propelling the scaling of nano-CMOS device have been summarized. Among them, the parasitic series resistance is a grand challenge for future CMOS generations. Audacious technical innovations in source/drain are needed to figure out the involved severe challenges. Progresses and breakthroughs in advanced source/drain technologies including ultrashallow junction formation and new source/drain structures have been extensively discussed. Combination of advanced doping and anneal technologies are crucial for ultra-shallow junction formation. Novel source/drain structures such as raised source/drain and metal Schottky barrier source/drain are promising solutions to satisfy the requirements of low resistance and excellent short-channel immunity. Critical issues such as parasitic parameters reduction and Schottky barrier adjustment need to be carefully optimized according to different application situations. Thermal stability issues of advanced scaled silicides have also been addressed. The encourage benefits offered by source/drain technologies continue to make these technologies a promising and active area of device research down to 21 nm and beyond. Acknowledgements This project was supported by the State Key Development Program for Basic Research of China (Contract No. 2006CB302704). References [1] International Technology for Semiconductor Roadmap (2009).www.itrs.net. [2] C.M. Osburn, K.R. Bellur, Thin Solid Films 332 (1e2) (1998) 428e436. [3] J.A. Kittl, K. Opsomer, C. Torregiani, C. Demeurisse, S. Mertens, D.P. Brunco, M.J.H. Van Dal, A. Lauwers, Materials Science and Engineering B-Advanced Functional Solid-State Materials 154 (2008) 144e154. doi:10.1016/ j.mseb.2008.09.033. [4] X. Qiuxia, D. Xiaofeng, L. Haihua, H. Zhengsheng, Y. Tianchun, IEEE Transactions on Electron Devices (2007). doi:10.1109/TED.2007.895871. [5] C. Ortolland, L.-A. Ragnarsson, P. Favia, O. Richard, C. Kerner, T. Chiarella, E. Rosseel, Y.Okuno (2009), VLSI technology, 2009 Digest of Technical Papers 2009 Symposium on 3A-3:38e39. [6] P.A. Stolk, H.J. Gossmann, D.J. Eaglesham, J.M. Poate, Nuclear Instruments & Methods in Physics Research Section B-Beam Interactions with Materials and Atoms 96 (1e2) (1995) 187e195. [7] V.E. Borisenko, S.G. Yudin, Physica Status Solidi A 1 (101) (1987) 123e127. [8] E.J.H. Collart, S.B. Felch, B.J. Pawlak, P.P. Absil, S. Severi, T. Janssens, W. Vandervorst, Journal of Vacuum Science & Technology B 24 (1) (2006) 507e509. doi:10.1116/1.2151906. [9] N. Cagnat, C. Laviron, D. Mathiot, C. Rando, M. Juhel, Semiconductor Defect Engineering-Materials, Synthetic Structures and Devices II 994 (2007) 217e222. [10] B.J. Pawlak, R. Duffy, T. Janssens, W. Vandervorst, S.B. Felch, E.J.H. Collart, N.E.B. Cowern, Applied Physics Letters 89 (6) (2006) 062102, doi:10.1063/ 1.2227863. [11] S.B. Felch, E. Collart, V. Parihar, S. Thirupapuliyur, R. Schreutelkamp, B.J. Pawlak, T. Hoffmann, S. Severi, P. Eyben, W. Vandervorst, T. Noda, Journal of Vacuum Science & Technology B 26 (1) (2008) 281e285. doi:10.1116/1.2831490. [12] Y. Kawasaki, T. Kuroi, T. Yamashita, K. Horita, T. Hayashi, M. Ishibashi, M. Togawa, Y. Ohno, M. Yoneda, T. Horsky, D. Jacobson, W. Krull, Nuclear Instruments & Methods in Physics Research Section B-Beam Interactions with Materials and Atoms 237 (1e2) (2005) 25e29. doi:10.1016/ j.nimb.2005.04.073. [13] S.B. Felch, Z. Fang, B.W. Koo, R.B. Liebert, S.R. Walther, D. Hacker, Surface & Coatings Technology 156 (1e3) (2002) 229e236. [14] Y. Sasaki, H. Ito, K. Okashita, H. Tamura, C.G. Jin, B. Mizuno, T. Okumura, I. Aiba, Y. Fukagawa, H. Sauddin, K. Tsutsui, H. Iwai, Ion Implantation Technology 866 (2006) 524e527. [15] W.J. Cho, K. Im, C.G. Ahn, J.H. Yang, J. Oh, I.B.O. Baek, S. Lee, in: 48th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication, A V S American Institute of Physics, San Diego, CA, Jun 01 04 2004, pp. 3210e3213. doi:10.1116/1.1813461. [16] Y. Sasaki, C.G. Jin, H. Tamura, B. Mizuno, R. Higaki, T. Satoh, K. Majima, H. Sauddin, K. Takagi, S. Ohmi, K. Tsutsui, H. Iwai, IEEE, in: Symposium on VLSI Technology. IEEE, Honolulu, HI, Jun 15 17 2004, pp. 180e181. [17] Y. Sasaki, K. Okashita, K. Nakamoto, T. Kitaoka, B. Mizuno, M. Ogura, IEEE International electron devices meeting 2008, Technical Digest (2008) 917e920.

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