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Spin coating over topography
1422
World Abstracts on Microelectronics and Reliability
analytical expressions relating layout geometries to likelihood of opens and shorts appearing during fabrication, and (2) efficient CAD methods to extract these geometries from the layout. This paper describes all these aspects as implemented in one unified CAD tool. Accuracy is enhanced through the addition of edge information and the validation of shorting defects. Advanced "contact engineering" for submicron VLSI multilevel metallization. K. KONRAD YOUNG et al. IEEE Transactions on Semiconductor Manufacturing, 6(1), 22 (1993). Two novel contact engineering methods have been developed for submicron contact openings. The two methods, abbreviated as SCOPE (Simultaneous COntact and Planarization Etch) and PACE (Planarization After Contact Etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow, thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth. Automated wafer level QBD measurement for production control. IVOR R. EVANS and DAVIDGARRATT. IEEE Transactions on Semiconductor Manufacturing, 6(1), 83 (1993). A novel technique is presented for the swift measurement of the charge necessary to induce failure in a thin SiO2 film (QBD). This can form part of a powerful wafer level reliability evaluation program through inclusion within an automated test system. The method is demonstrated here by extracting the distribution of QBD values from across several 150 mm wafers. Spin coating over topography. LON!M. PEURRUNG and DAVID B. GRAVES. IEEE Transactions on Semiconductor Manufacturing, 6(1), 72 (1993). We present a model for predicting film thickness profiles around topographical features during spin coating. This model is applicable to features of arbitrary geometry in the two lateral dimensions. This generality permits study of the planarization of real device structures, including both isolated and neighboring features, with any orientation with respect to the wafer center. Predictions from this model agree qualitatively with measured film profiles from interferograms taken during spinning. Phenomena such as "pile-up" and "wakes" result from interactions
between surface tension and other driving forces in the flow. A study of failures identified during board level environmental stress testing. T. PAUL PARKER and CATHYW. WEan. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1086 (1992). AT and T has investigated and implemented environmental stress testing (EST) in the production of a variety of circuit board designs as a means of reducing the incidence of early life failures. EST techniques include thermal cycling (TC), random vibration, etc. These techniques have proven more effective than traditional burn-in techniques. In addition, studies have revealed that functional monitoring during thermal stressing of circuit cards more than doubles the effectiveness of EST. Outgoing quality audits and customer first month failure rates have improved by factors of two to four since the implementation of EST. Reliability assessment of high lead count TAB package. JAMIN LING, HONGBEE TEOH, DAVID SORRELLS and JACK JONES. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1105 (1992). This paper describes the reliability assessment of a high lead count tape automated bonding (TAB) package using advanced packaging technology. The package was developed to replace existing leaded chip carriers for high I/O and high performance applications. The package technology uses Au bumps and Au plated, single-metal 2-layer 70-ram Cu tape with a polyimide support ring. After inner lead bonding and chip encapsulation, the chip-on-tape was epoxy attached to a ceramic base and lid. This clamshell design provided both mechanical as well as environmental protection to the integrated circuit device. Two test vehicles, with up to 332 leads, were assembled using the new packaging technology. Due to their physical constructions, the packages contained the characteristics of both hermetic ceramic packages as well as nonhermetic packages. To assess the reliability concerns arising from this technology, the packages were subjected to a comprehensive array of reliability tests consisting of military/industry standard thermal, mechanical and environmental test methods. In addition, to address the module assembly process compatibility and its effects on reliability, some samples were attached onto printed wiring board test coupons before being subjected to biased temperature humidity and pressure cooker tests. Details of the reliability testing are described and the results presented. After stress testing, the samples passed all electrical testing. Furthermore, the corrosion resistance of the package was demonstrated via high temperature, high humidity and industrial environment tests. However, certain unexpected observations were also revealed, including lid cracking, low inner lead bond
World Abstracts on Microelectronics and Reliability
analytical expressions relating layout geometries to likelihood of opens and shorts appearing during fabrication, and (2) efficient CAD methods to extract these geometries from the layout. This paper describes all these aspects as implemented in one unified CAD tool. Accuracy is enhanced through the addition of edge information and the validation of shorting defects. Advanced "contact engineering" for submicron VLSI multilevel metallization. K. KONRAD YOUNG et al. IEEE Transactions on Semiconductor Manufacturing, 6(1), 22 (1993). Two novel contact engineering methods have been developed for submicron contact openings. The two methods, abbreviated as SCOPE (Simultaneous COntact and Planarization Etch) and PACE (Planarization After Contact Etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow, thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth. Automated wafer level QBD measurement for production control. IVOR R. EVANS and DAVIDGARRATT. IEEE Transactions on Semiconductor Manufacturing, 6(1), 83 (1993). A novel technique is presented for the swift measurement of the charge necessary to induce failure in a thin SiO2 film (QBD). This can form part of a powerful wafer level reliability evaluation program through inclusion within an automated test system. The method is demonstrated here by extracting the distribution of QBD values from across several 150 mm wafers. Spin coating over topography. LON!M. PEURRUNG and DAVID B. GRAVES. IEEE Transactions on Semiconductor Manufacturing, 6(1), 72 (1993). We present a model for predicting film thickness profiles around topographical features during spin coating. This model is applicable to features of arbitrary geometry in the two lateral dimensions. This generality permits study of the planarization of real device structures, including both isolated and neighboring features, with any orientation with respect to the wafer center. Predictions from this model agree qualitatively with measured film profiles from interferograms taken during spinning. Phenomena such as "pile-up" and "wakes" result from interactions
between surface tension and other driving forces in the flow. A study of failures identified during board level environmental stress testing. T. PAUL PARKER and CATHYW. WEan. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1086 (1992). AT and T has investigated and implemented environmental stress testing (EST) in the production of a variety of circuit board designs as a means of reducing the incidence of early life failures. EST techniques include thermal cycling (TC), random vibration, etc. These techniques have proven more effective than traditional burn-in techniques. In addition, studies have revealed that functional monitoring during thermal stressing of circuit cards more than doubles the effectiveness of EST. Outgoing quality audits and customer first month failure rates have improved by factors of two to four since the implementation of EST. Reliability assessment of high lead count TAB package. JAMIN LING, HONGBEE TEOH, DAVID SORRELLS and JACK JONES. IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 15(6), 1105 (1992). This paper describes the reliability assessment of a high lead count tape automated bonding (TAB) package using advanced packaging technology. The package was developed to replace existing leaded chip carriers for high I/O and high performance applications. The package technology uses Au bumps and Au plated, single-metal 2-layer 70-ram Cu tape with a polyimide support ring. After inner lead bonding and chip encapsulation, the chip-on-tape was epoxy attached to a ceramic base and lid. This clamshell design provided both mechanical as well as environmental protection to the integrated circuit device. Two test vehicles, with up to 332 leads, were assembled using the new packaging technology. Due to their physical constructions, the packages contained the characteristics of both hermetic ceramic packages as well as nonhermetic packages. To assess the reliability concerns arising from this technology, the packages were subjected to a comprehensive array of reliability tests consisting of military/industry standard thermal, mechanical and environmental test methods. In addition, to address the module assembly process compatibility and its effects on reliability, some samples were attached onto printed wiring board test coupons before being subjected to biased temperature humidity and pressure cooker tests. Details of the reliability testing are described and the results presented. After stress testing, the samples passed all electrical testing. Furthermore, the corrosion resistance of the package was demonstrated via high temperature, high humidity and industrial environment tests. However, certain unexpected observations were also revealed, including lid cracking, low inner lead bond