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Sputtering under ultrahigh vacuum environment
World Abstracts on Microelectronics and Reliability into 12 areas with 86 lectures and a presentation of posters with 59 contributions. Research and technology in microelectronies. J. DANNEELS, M. RAHIER and A. MOZER. Elect. Commun. 62(3/4), 352 (1988). Microelectronics technology is the key to the development of increasingly complex telecommunication products. Alcatel maintains a strong research activity in this area with the aim of providing an advanced design methodology and tools for the development of "VLSI systems on silicon".
. MICROELECTRONICS--DESIGN Research reveals differences in coating effects on die stress. FEREYDOUN SHORAKA, CHARLES A. GEALER and ERIC BETTEZ. Semiconductor Int. l l0 (October 1988). Finite element and piezo stress analyses provide practical information on silicone- and polyimide-based die coatings. Application of a two-layer planarization process to VLSI intermetal dielectric and trench isolation processes. D. J. SHELDON, C. W. GRUENSCHLAEGER, L. KAMMERDINER, N. B. HENIS, P. KELLEHER, and J. D. HAYDEN. IEEE Trans. Semicond. Manufact. 1(4), 140 (1988), The application of a novel planarization process using a sacrificial fill layer of photoresist is presented. The process is shown to solve the planarization problems encountered in both intermetal dielectric for a 1.2 ,am 265K SRAM technology and trench isolation for a 0.8-/~m 1M SRAM technology. The process is a simple extension of the standard dielectric etch-back scheme. A discussion of how to precisely quantify circuit planarization using well-known techniques is also presented. This information can then be adapted for statistical quality control purposes.
VLSI: linking design and manufacturing. ANDRZEJ J. STROJWAS and STEPHEN W. DIRECTOR. IEEE Spectrum 24 (October 1988). New CAD tools use data on process parameters and device geometries to predict the characteristics and their statistical distributions, as well as the yields, of complex chips. Sputtering under ultrahigh vacuum environment. G. PE'fER, J. A. KOPRIO and R. SLEPICKA. Vacuum 38(8-10), 795 (1988). An ultrahigh vacuum sputter deposition plant with three sputter targets and a load lock facility for up to 3" wafers is described below. The reasons for transferring such a process into an ultrahigh vacuum plant are explained. The paper concentrates on the method. Some results for Si, W and Ti are presented and compared with results from the literature obtained under high vacuum conditions. Polyimide enables high lead count TAB. IVANAMILOSEVIC, ANDRE PERRET, EWALD LOSERT and PETER SCHLENKRICH. Semicond. Int. 122 (October 1988). Photosensitive polyimide is the key change in our straight wall bumping process for 100 pm pitch, or better, TAB. Change your surfactant formula and use etch baths for a week, KHALID M. SHAH, PENNY MIKKELSEN and WILLIAM CUMMINGS. Semiconductor Int. 132 (October 1988). By altering the ratio of ingredients in surfactant formulations in a filtered etch bath, you can increase their effectiveness. Robotic systems enhance manufacturing efficiency. ANN CHESTNUT, PETER H. SINGER and KATHLEEEN KEARNEY. Semiconductor Int. 58 (October 1988). Automation can help you reduce contamination while enhancing safety, process control and process flexibility.
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Unusual electron beam effects in the GaAs (100)]Ci 2 system. S. M. MOKLER and P. R. WATSON. Solid St. Commun. 70(4), 415 (1989). We find that chlorine adsorbed on a (1 × 1) GaAs(100) surface is very sensitive to electron-induced desorption. Loss of chlorine appears to occur via at least one fast, and one slow, route with very different cross-sections. Change in the Ga Auger signal indicate that significant Ga-C1 interactions occur during adsorption and electroninduced desorption.
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CONSTRUCTION
Dry etch development for silicon processing within a teaching institution. M. A. CARTER. Vacuum 38(8-10), 873 (1988). Reactive ion etching for SiO 2 and for A1/l% Si is described where the requirement is for reliable but low volume processing. The effects of process parameters for one particular system have been investigated. Thermal characterization of a 149-lead VLSI package with heatsink. PAUL B. WESLING. IEEE Trans. Comp. Hybrids Manufact. Tech. 11(4), 512 (December 1988), High power ECL circuits in large pin-grid array (PGA) packages must be optimized for thermal dissipation in order to operate with high reliability in computer applications. In this paper, the steady-state and dynamic thermal characteristics of a 149lead hermetic PGA package are studied, with focus on three different configurations of a stacked-fin heatsink and on two types of fillers for the epoxy heatsink attach adhesive. The package described has high thermal performance in an air-cooled regime. Data are presented showing thermal resistance from junction to ambient as a function of number of heatsink fins and composition of heatsink-attach epoxy. At nominal conditions, thermal resistance from junction to ambient, 0~, of the selected 5-fin heatsink and aluminumfilled epoxy adhesive is less than 6°C/W at an airflow of 2.5 m/s (500 linear ft/min). Also discussed is the junction-to-case thermal resistance, measured per SEMI Standard G30-86. A value of 2.1°C/W was measured for the package. Air bridge and via hole technology for GaAs based microwave devices. Microelect. J. 19(5), 23 (1988). This paper describes the process parameter dependence of air bridges and via holes of different dimensions for GaAs based microwave devices and ICs. Process conditions and technologically feasible optimum dimensions of the air bridges for circuit layout are suggested. A wet etching technique for the formation of extremely small (15 × 15 micron) via holes is also described. New Mnllite ceramic packages and substrates. MICHIO HORIUCHI, KIHOU MIZUSHIMA, YUKIHARUTAKEUCHI and SmN-ICm WAKABAVASm. IEEE Trans. Comp. Hybrids Manufact. Tech. 11(4), 439 (December 1988). Recent VLSI packaging technology requires high propagation speed, high wiring density, and high thermal dissipation. In order to achieve these requirements, ceramic packages need to have a low thermal expansion coefficient, a low dielectric constant, and high thermal conductivity. For these purposes, new mullite ceramics have been developed. The advantages and characteristics of the new mullites are as follows; (1) Low dielectric constants (5.4--7.3 at 1 MHz), favorable for the high propagation speed. (2) Low thermal expansion coefficients (3.0-4.5× 10 6/°C), which permit the direct attachment of large silicon chips. (3) Higher mechanical strength (2~31 kg/min 2) than that of old mullite ceramics.
. MICROELECTRONICS--DESIGN Research reveals differences in coating effects on die stress. FEREYDOUN SHORAKA, CHARLES A. GEALER and ERIC BETTEZ. Semiconductor Int. l l0 (October 1988). Finite element and piezo stress analyses provide practical information on silicone- and polyimide-based die coatings. Application of a two-layer planarization process to VLSI intermetal dielectric and trench isolation processes. D. J. SHELDON, C. W. GRUENSCHLAEGER, L. KAMMERDINER, N. B. HENIS, P. KELLEHER, and J. D. HAYDEN. IEEE Trans. Semicond. Manufact. 1(4), 140 (1988), The application of a novel planarization process using a sacrificial fill layer of photoresist is presented. The process is shown to solve the planarization problems encountered in both intermetal dielectric for a 1.2 ,am 265K SRAM technology and trench isolation for a 0.8-/~m 1M SRAM technology. The process is a simple extension of the standard dielectric etch-back scheme. A discussion of how to precisely quantify circuit planarization using well-known techniques is also presented. This information can then be adapted for statistical quality control purposes.
VLSI: linking design and manufacturing. ANDRZEJ J. STROJWAS and STEPHEN W. DIRECTOR. IEEE Spectrum 24 (October 1988). New CAD tools use data on process parameters and device geometries to predict the characteristics and their statistical distributions, as well as the yields, of complex chips. Sputtering under ultrahigh vacuum environment. G. PE'fER, J. A. KOPRIO and R. SLEPICKA. Vacuum 38(8-10), 795 (1988). An ultrahigh vacuum sputter deposition plant with three sputter targets and a load lock facility for up to 3" wafers is described below. The reasons for transferring such a process into an ultrahigh vacuum plant are explained. The paper concentrates on the method. Some results for Si, W and Ti are presented and compared with results from the literature obtained under high vacuum conditions. Polyimide enables high lead count TAB. IVANAMILOSEVIC, ANDRE PERRET, EWALD LOSERT and PETER SCHLENKRICH. Semicond. Int. 122 (October 1988). Photosensitive polyimide is the key change in our straight wall bumping process for 100 pm pitch, or better, TAB. Change your surfactant formula and use etch baths for a week, KHALID M. SHAH, PENNY MIKKELSEN and WILLIAM CUMMINGS. Semiconductor Int. 132 (October 1988). By altering the ratio of ingredients in surfactant formulations in a filtered etch bath, you can increase their effectiveness. Robotic systems enhance manufacturing efficiency. ANN CHESTNUT, PETER H. SINGER and KATHLEEEN KEARNEY. Semiconductor Int. 58 (October 1988). Automation can help you reduce contamination while enhancing safety, process control and process flexibility.
197
Unusual electron beam effects in the GaAs (100)]Ci 2 system. S. M. MOKLER and P. R. WATSON. Solid St. Commun. 70(4), 415 (1989). We find that chlorine adsorbed on a (1 × 1) GaAs(100) surface is very sensitive to electron-induced desorption. Loss of chlorine appears to occur via at least one fast, and one slow, route with very different cross-sections. Change in the Ga Auger signal indicate that significant Ga-C1 interactions occur during adsorption and electroninduced desorption.
AND
CONSTRUCTION
Dry etch development for silicon processing within a teaching institution. M. A. CARTER. Vacuum 38(8-10), 873 (1988). Reactive ion etching for SiO 2 and for A1/l% Si is described where the requirement is for reliable but low volume processing. The effects of process parameters for one particular system have been investigated. Thermal characterization of a 149-lead VLSI package with heatsink. PAUL B. WESLING. IEEE Trans. Comp. Hybrids Manufact. Tech. 11(4), 512 (December 1988), High power ECL circuits in large pin-grid array (PGA) packages must be optimized for thermal dissipation in order to operate with high reliability in computer applications. In this paper, the steady-state and dynamic thermal characteristics of a 149lead hermetic PGA package are studied, with focus on three different configurations of a stacked-fin heatsink and on two types of fillers for the epoxy heatsink attach adhesive. The package described has high thermal performance in an air-cooled regime. Data are presented showing thermal resistance from junction to ambient as a function of number of heatsink fins and composition of heatsink-attach epoxy. At nominal conditions, thermal resistance from junction to ambient, 0~, of the selected 5-fin heatsink and aluminumfilled epoxy adhesive is less than 6°C/W at an airflow of 2.5 m/s (500 linear ft/min). Also discussed is the junction-to-case thermal resistance, measured per SEMI Standard G30-86. A value of 2.1°C/W was measured for the package. Air bridge and via hole technology for GaAs based microwave devices. Microelect. J. 19(5), 23 (1988). This paper describes the process parameter dependence of air bridges and via holes of different dimensions for GaAs based microwave devices and ICs. Process conditions and technologically feasible optimum dimensions of the air bridges for circuit layout are suggested. A wet etching technique for the formation of extremely small (15 × 15 micron) via holes is also described. New Mnllite ceramic packages and substrates. MICHIO HORIUCHI, KIHOU MIZUSHIMA, YUKIHARUTAKEUCHI and SmN-ICm WAKABAVASm. IEEE Trans. Comp. Hybrids Manufact. Tech. 11(4), 439 (December 1988). Recent VLSI packaging technology requires high propagation speed, high wiring density, and high thermal dissipation. In order to achieve these requirements, ceramic packages need to have a low thermal expansion coefficient, a low dielectric constant, and high thermal conductivity. For these purposes, new mullite ceramics have been developed. The advantages and characteristics of the new mullites are as follows; (1) Low dielectric constants (5.4--7.3 at 1 MHz), favorable for the high propagation speed. (2) Low thermal expansion coefficients (3.0-4.5× 10 6/°C), which permit the direct attachment of large silicon chips. (3) Higher mechanical strength (2~31 kg/min 2) than that of old mullite ceramics.