Stacked field effect transistor integration in double channel transistors (DCT) with tri-state transfer slope and ballistic field effect behavior

Microelectronic Engineering 87 (2010) 2456–2462

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Stacked field effect transistor integration in double channel transistors (DCT) with tri-state transfer slope and ballistic field effect behavior Frank Wirbeleit GLOBALFOUNDRIES, 2070 Route 52, Hopewell Junction, New York 12533, United States

a r t i c l e

i n f o

Article history: Received 11 January 2010 Received in revised form 1 April 2010 Accepted 9 May 2010 Available online 22 May 2010 Keywords: MOS devices MOSFETs FET memory integrated circuits Logic devices Static memory cell SRAM

a b s t r a c t Implants create isolated electric charge under the channel region of nFET and pFET. By this, a new local extrema in the transfer slope is obtained while maintaining low leakage in off state. The results are explained by electro-static field simulation and yield in a circuit model with two parallel channel resistors, indicating a double channel field effect transistor (DCT). The new DCTs allow complex functions in logic or small transistor bit cells in the future. Ó 2010 Elsevier B.V. All rights reserved.

1. Introduction Because of the aggressive and very expensive pitch scaling in microelectronic technology, stacked and modified field effect transistor (FET) device integration is widely under discussion [1]. Improved FET devices with double or triple gate provide improvements by better control of short channel effects and with respect to performance [2,3], while multiple independent gate (MIG-) FETs [4] use an additional voltage biased gate electrode to dynamically modulate the sub-threshold swing. Dual channel devices enable negative differential channel resistance by using a two parallel device channel hetero structure [5] at expense of microelectronic technology costs. In [6] double channel nFET and pFET devices are demonstrated first time, implemented at low cost in standard 65 nm microelectronic device technology and applicable as static memory devices. In contrast to dual channel devices [5], double channel devices [6] have only one channel but acting dual, in enhancement or depletion mode, depending on applied body bias voltage [6]. This work demonstrates double channel devices manufactured in 45 nm silicon on insulator (SOI) technology and basic measurement results in floating body mode for improved device understanding and further application. As presented in this work, double channel devices in floating body measurement mode have a negative transconductance region in the transfer slope also, reported so far from DCT measurements with forced body only [6]. This third state is a high resistance state E-mail address: [email protected] 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.05.003

at a gate voltage VDCT below threshold voltage and at low VDS, with a minimum leakage current even below IOFF at VGS = 0. This enables further development of DCT as memory devices in small transistor bit cells without body contact design and at low power consumption for large low voltage SRAM applications. Since in static memory cell application (SRAM) the maximum drive current in ‘‘on” state can be clearly reduced from high logic device FETs down to few lA, DCT are not necessarily high performance/high power devices. Because, the decoupled mechanism for minimum off-current and maximum on-current from threshold voltage (Vth) is a new property of DCT compared to FET devices, a further DCT device performance and technology optimization is promising. The DCT on-current was found initiated by the ballistic carrier transport effect in the output slope of the DCT devices, which might gain an DCT drive current (IDS) advantage in low power application compared to standard FET. Based on the measurement results a first order DCT SPICE model is presented in this work which suggests a circuit transistor model with two stacked parallel channels for further DCT circuit simulation. 2. Experiments 2.1. Technology of DCT manufacturing As illustrated in Fig. 1a (process sequence order goes from top left to bottom right) a standard 45 nm CMOS technology on SOI substrates (88 nm silicon, 144 nm buried oxide on bulk silicon) was used to manufacture double channel devices. Prior the channel

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Fig. 1. (a) Schematic process flow of DCT device manufacturing in sequence from top left to bottom right. The numbers indicate: 1 – channel implant; 2 – double channel implant; 3 – silicon substrate; 4 – gate electrode; 5 – implant spacer; 6 – HALO implant; 7 – extension and junction implants. (b) Final sketch after source/drain implant and activation anneal out of the simulated double channel process flow to illustrate implant profiles and the location of the isolated dopant area under the gate electrode.

sub-threshold implant (1) one additional deep implant step (2), for n- and p-channel FET separate, was done into the surface silicon layer (3), pre-gate (4) and implant spacer (5) formation. This implant step (2) is called double channel transistor (DCT-) implant and forms a buried counter doped layer under the surface channel by using the same species and nearly the same implant energy and doses, as common for the post gate HALO implants (6) later in the process flow. The regular post gate pattering HALO implant (6) forms together with the DCT implant (2) a dopant island, isolated from junction implant area (7). In Fig. 1b a sketch of the simulated process flow after junction implant (7) and dopant activation anneal is shown. The isolated implant area under the surface channel affects the device transfer behavior electro-statically, by super positioning the gate potential and shortening the effective channel length for charge carrier transport along the drain-to-source path and depending on applied gate and drain voltage as discussed in following. 2.2. Electrical measurement results The n- and p-DCT devices are measured in the lab at floating body and grounded source potential. As shown in Fig. 2 (left) DCT transfer slopes are measured at drain voltages (VDD) of 50 mV and 1 V as common for device characterization in linear and saturation mode and at 100 mV steps in between for further discussion. The measured output characteristics of DCT devices are shown in Fig. 2 also (right). From n- and p-DCT transfer slopes given in Fig. 2 the maximum drain-source-current IDS(VDD = 1 V) was measured of 190 lA/lm for nDCT and of 35.1 A/lm for pDCT. In linear mode (VDD = 50 mV) IDS is 23 lA/lm for nDCT and 8.3 lA/lm for pDCT. The IOFF(VGS = 0 V, VDD = 50 mV) is measured for nDCT at 4.7 pA/lm and for pDCT at-0.93 pA/lm. Maximum IOFF(VGS = 0 V, VDD = 1 V) is 2.5 nA/lm for nDCT and 8.2 nA for pDCT. For further characterization the linear and saturation trans-conductivities gmlin and gmsat are used as given in Eqs. (1) and (2)

gmlin ¼

gmsat ¼

@IDS ; @VGS @

VDS ¼ 50 mV

pffiffiffiffiffiffiffiffiffiffi jIDSj ; @VGS

VDS ¼ 1 V

ð1Þ

ð2Þ

The slopes for transconductance are shown in Fig. 3. Transconductance slopes are calculated by non linear function approximation analytical differentiation of the approximated graphs as described in [7] in order to avoid mathematical uncertainties of the local tangent method. Characteristic transconductance parameters of slopes in Fig. 3 are summarized in Table 1. To describe the

DCT transfer slope, the gate-source voltage (VGS) at transconductance of zero (gmlin = 0) is unique for double channel devices and labeled as VDCT therefore (see Table 1). 3. Discussion 3.1. Tri-state transfer slope of DCT In Fig. 3a the DCT’s transconductivity at 50 mV VDS is negative at zero gate voltage VGS and remains negative up to VGS = VDCT of around |0.17| V. The drain-source-current as a function of gate voltage, IDS(VGS, VDS = 50 mV), reaches a minimum at this point in Fig. 2. Beside VGS = 0 and VGS = 1 V, VDCT is a third state of DCT devices therefore. It is a low power and high channel resistance state, supporting the intended application of DCT devices in small transistor static memory cells [6]. The gate voltage VGS at gmlin = 0 at VDS = 50 mV is called double channel threshold voltage VDCT. From transfer slope measurements shown in Fig. 2 it becomes obvious that the characteristic VDCT value diminishes above 200 mV of VDS for the given n- and p-DCT devices, which will be explained next. From general point of view, VDCT at low VDS only is not an issue with respect to the intended application of DCT for small transistor static bit cells, because in this case DCTs are required to act in non-inverter circuits, where low VGS is always correlated to low VDS. Furthermore, today’s industry bit-cell stability is pushed towards low VDD values (actually 0.6 V and below) for general circuit applications with different sleep states, supporting DCT in tri-state transfer slope application. The stability of the VDCT state against electric noise is a concern, at least for the presented nDCT device transfer slope in Fig. 2, because the minimum IDS(VGS = VDCT) is just or even less than one order of magnitude below IDS(VGS = 0). Further DCT technology improvement will enhance the stability of the VDCT state against electric noise and exploratory research at DCT devices below 56 nm channel length is necessary. Another option to improve DCTs tri-state effect is the application in forced body mode circuits as illustrated in Ref. [6] first, but this is not subject of this work about basic DCT device properties. To understand the double channel effect, that means the appearance of VDCT in the transfer slope of a FET, e.g., the effect of a buried charge under the gate on the electrical current flow between source and drain electrode, a simple superposition of coulomb fields from electro-static charges at drain Q(Drain) and gate Q(Gate) electrodes with and without a buried isolated charge Q(buried) is simulated in the arrangement shown in Fig. 4. The simulation results are shown in Fig. 5, by the electro-static field E given in unit vectors and the electro-static field strength /

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N-DCT tran sf er slope

N-DCT ou tpu t slope

0.0001

IDS [A/µm]

1e-006

1e-008

1V 1V

875mV

600mV

750mV

1e-010

625mV

400mV

VGS=

VDS= 200mV

1e-012

375mV

100mV

250mV

50mV

125mV

1e-014

0

0.2

0.4

(a)

500mV

0.6

0.8

1

0

0.2

VGS [V]

0.4

0.6

0V 0.8

1

VDS [V]

P-DCT output slope

P-DCT transfer slope

0.0001 0.0001

1e-006 1e-006

abs(IDS) [A/um]

1e-008

1V 500mV

1e-010

1e-008

VDS= 300mV 1e-012

200mV

1V

100mV

875mV 1e-010

50mV

750mV

1e-014 -1e-014

625mV VGS= 1e-012

500mV 375mV

-1e-012

250mV 125mV

-1e-010

(b)

0V

1e-014

0

0.2

0.4

0.6

0.8

|VGS [V]|

1

0

0.2

0.4

0.6

0.8

1

|VDS [V]|

Fig. 2. Sub-threshold and output slopes of floating body measurements at (a) nDCT and (b) p-DCT test structures with 1 lm channel width and 56 nm channel length.

indicated by color intensity. Comparing Fig. 5a and b first, the impact of a buried charge under the surface channel on the electric field along the carrier flow direction (IDS) is illustrated. Regardless, that the simulation in Fig. 5 is performed at arbitrary units, is can be assumed that the transistor state in Fig. 5a and b represent the effect of reduced IOFF current for n- and p-DCT around VDCT, below Vth and at low VDD, as measured in the transfer slopes of Fig. 2. The presence of a buried charge under the gate electrode adds an electric field component Ey perpendicular to the IDS flow direction Ex and lowers the electrical current flow from source to drain thereby. This effect reaches a maximum impact on IDS, if Q(Gate) and Q(buried) act in balance as mirror charges at VDCT. As suggested

by Fig. 5b, the double channel effect becomes even stronger, if the electric field direction goes from a focused positive Q(buried) to an surface negative Q(Gate) charge as in case of pDCT, compared to nDCT with positive Q(Gate) and negative Q(buried) charge and electro-static field lowering by source and drain potential. This is in agreement with transfer slope measurement results shown in Fig. 2, where the dual channel effect at pDCT becomes at VDCT so strong, that the electric field direction between the buried charge and the drain electrode of the pDCT device gets turned and causes a reverse IDS flow. Increasing the amount of the charge of the gate electrode, as shown in comparison of Fig. 5b and c for nDCT and pDCT, the electro-static gate electrode field generates an electric

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A V

pDCT nDCT

0.035

[ gm sat

0.025 0.02

pDCT nDCT

0

0.2

0.4

0.01 0.005 0

-0.005

0.8

1

0.8

1

0.014 0.012 0.01 0.008 0.006 0.004 0.002 0

(a)

0.6

|VGS| [V]

0.015

∂ gm sat ∂ VGS

∂ [log (IDS

)]

∂ VGS

0.03

0.0045 0.004 0.0035 0.003 0.0025 0.002 0.0015 0.001 0.0005 0

0

0.2

0.4

0.6

0.8

1

|VGS| [V]

(b)

0

0.2

0.4

0.6

|VGS| [V]

Fig. 3. (a) Gradient of sub-threshold plot and (b) gmsat plots for nDCT and pDCT calculated from transfer slopes shown in Fig. 2 at VDS 50 mV.

Table 1 Characteristic values from transfer and transconductivity plots shown in Figs. 1 and 2 for nDCT (range of VGS from 0 to 1 V) and pDCT (range VGS from 1 to 0 V) devices. Parameter max ½gmlin  IDSðmax ½gmlin Þ VGSðmax ½gmlin Þ Vtlin VGSðgmlin ¼ 0Þ max ½gmsat  IDSðmax ½gmsat Þ VGSðmax ½gmsat Þ Vtsat

(lA/V) (lA/lm) (V) (V) (V) p ( (A)/V) (lA/lm) (V) (V)

nDCT

pDCT

133 20.4 0.98 0.80 0.15 4.15  105 143 0.94 0.9

63.1 7.2 0.98 0.84 0.19 3.45  105 24.8 0.96 0.95

¼ VDCT

y 10 field simulation area Q (buried) 2

x -12 -10 Source

-0.5

Q (Gate)

10

12 Q (Drain)

Fig. 4. Simulation arrangement for electro-static field simulation of coulomb charges at drain, gate and buried charge in DCTs.

field component along the surface and stimulates an electric carrier flow as known form standard FET above Vth. Because of the described effect, that a buried charge acts stronger for pDCT than for nDCT, the IDS above VDCT raises stronger for nDCT than for pDCT in agreement to the measured results in transfer slopes of Fig. 2. As a result of this discussion, the double channel effect in nDCT and pDCT can be adjusted by appropriate DCT implant dose settings in the process flow shown in Fig. 1a for pDCT drive currents (IDS) improvements. Because the penetration depth of DCT implants localizes the strength of the double channel effect under the gate (zero plane between Q(Gate) and Q(buried) as mirror charges), DCT implant energy is an important parameter to control the double channel effect below Vth and minimize the impact on IDS in DCT on state. Regardless that the double channel impact on IDS below Vth is small, is enables about one magnitude order

lower IOFF current and provides desired low power DCT self-bi-stability in appropriate SRAM cell design because of the negative transconductivity below VDCT. Down scaling the DCT device geometry the double channel effect is expected to become stronger, because the buried charge volume scales less than the gate surface charge. 3.2. Ballistic field effect of DCT As shown in output slope measurement results of Fig. 2, the presented DCTs do not expose a channel cut off effect in high VDD voltage range as commonly expected for regular FET and covered by an early voltage device parameter. The total amount of IDS increases with increasing VDS for both DCT devices in the measured output slopes of Fig. 2 as described in [8] as ballistic carrier transport phenomena in nano-devices. Comparing simulation results in Fig. 5c and d it is suggested, that an increased Q(Drain) charge amount (increased VDD) focuses the electric field component along carrier flow direction and points from drain to buried charge and from buried charge to source electrode of the device, shortening the effective channel length by half. This enables a ballistic carrier transport in mid range VDD as measured and shown in transfer slopes of Fig. 2 (designed DCT total channel length is 56 nm). Fig. 5d suggests that at very high VGate voltage the buried charge under the gate electrode gets over flooded by the surrounding field and the ballistic carrier transport diminishes. In this case the buried charge acts a carrier transport barrier mainly, reducing the effective channel cross section area and causing IDS current degradation for DCT devices compared to standard FET at the same geometry. The ballistic carrier transport, seen at DCT in electrical output measurements of Fig. 2, provides an additional IDS current at low VGS however, which might advantage DCT against regular FET comparing maximum IDS in low power digital application (low VDD and low VGate). In order to characterize the ballistic channel resistance in DCT’s output slopes given in Fig. 2, the ballistic channel conductance GDS as given in Eq. (3) (W – channel width, pls. compare [9]) is shown in Fig. 6 for n- and p-DCT devices

GDS ¼

IDS W VDS

ð3Þ

According to Fig. 2, the pinch off of the DCT channel for n- and p-DCT starts above a absolute value of VDS of about 0.2 V. Below this voltage the channel conductance is found to be higher as for all FET devices. For VDS above 0.2 V, the channel conductance

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nD C T

pD C T 12

12

Q(Drain)=5000; Q(buried)=0; Q(Gate)=1

200 180 160 140 120 100 80 60 40 20 0

10 8

(a)

6 4 2 0 -5

0

5

Q(Drain)=5000; Q(buried)=-100; Q(Gate)=1

6 4 2

-10

200 180 160 140 120 100 80 60 40 20 0

10 8 6 4 2

-5

0

5

10

12

Q(Drain)=-5000; Q(buried)=100; Q(Gate)=-1

0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200

10 8 6 4 2

0

0 -10

-5

0

5

10

-10

-5

0

5

10

12

12 Q(Drain)=5000; Q(buried)=-100; Q(Gate)=15

200 180 160 140 120 100 80 60 40 20 0

10 8 6 4 2 0

Q(Drain)=-5000; Q(buried)=100; Q(Gate)=-15

0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200

10 8 6 4 2 0

-10

-5

0

5

10

-10

-5

0

5

10

12

12

Q(Drain)=50000; Q(buried)=-100; Q(Gate)=15

2000 1800 1600 1400 1200 1000 800 600 400 200 0

10 8

(d)

8

10

12

(c)

0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200

0 -10

(b)

Q(Drain)=-5000; Q(buried)=0; Q(Gate)=-1 10

6 4 2 0

Q(Drain)=-50000; Q(buried)=100; Q(Gate)=-15

0 -200 -400 -600 -800 -1000 -1200 -1400 -1600 -1800 -2000

10 8 6 4 2 0

-10

-5

0

5

10

-10

-5

0

5

10

Fig. 5. Electro-static field simulation in the channel area for n- and p-DCT by the superposition of electro-static fields and in the arrangement shown in Fig. 4: (a) w/o buried charge, sub-threshold mode, (b) same as (a) but w/o buried charge, (c) same as (b) but VGS > Vth and starting channel formation under the gate, (d) same as (c) but high Q(Drain) charge for extra ballistic transport via buried charge at half channel length.

GDS is expected to drop with raising VDS for standard FET after Eq. (3), because IDS remains almost constant at further increased VDS. In case of ballistic carrier transport, GDS is expected to become a

constant with raising VDS, because IDS also raises linearly [9], as found in Fig. 6 for the VGS slope of 1 V (top slope in Fig 6a and b with triangles). For the GDS slopes in Fig. 6 it is assumed, that

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0.0001 VGS= 1V 875mV 750mV 625mV

1e-005

500mV 375mV

|GSD| [S]

1e-006

250mV 125mV 0V

1e-007

1e-008

1e-009

1e-010 0

0.2

0.4

(a)

0.6

0.8

0

1

0.2

0.4

(b)

VDS [V]

0.6

0.8

1

|VDS [V]|

Fig. 6. Ballistic channel resistance of (a) nDCT and (b) p-DCT, calculated from output slopes shown in Fig. 2 after Eq. (3).

the ballistic transport effect (constant GDS) is dominant in mid and high VGS voltage range from 1 V down to about 0.7 V. For low VGS (below 0.7 V), the channel conductance of DCT shows a pronounced minimum at maximum channel pinch-off and rising exponential with increased VDS again, indicating an minor extra carrier tunnel current in addition to the ballistic transport described above, but one or two orders of magnitude lower.

3.3. Stacked field effect transistor behavior – a first order SPICE model Fig. 8. Small signal equivalent circuit of DCT with one additional channel conductance dm parallel to standard channel conductance gm (for details of standard small signal circuit FET model pls. see [10]).

The transfer slopes of DCT as shown in Fig. 2 suggest, that electrical currents of two gate voltage dependent sources are adding up to the total amount of drain current IDS. An n- and p-channel FET is super-positioned in Fig. 7a schematically for circuit simulation (SPICE modeling) therefore, together with a suggested circuit symbol for DCT devices based on a standard FET circuit symbol with an implied buried charge circle symbol under the gate. In the SPICE model of Fig. 7a the nDCT is modeled by a nFET device with high and a pFET device with low channel conductivity in parallel, both with different threshold voltages for appropriate Vth and VDCT simulation. The ballistic carrier transport discussed in section C can be modeled by an advanced nFET device SPICE model, if required in advanced DCT circuit simulations. The SPICE model representation of DCT shown in Fig. 7a can be transferred into the DCT small signal circuit model based on the established one for standard FET [10] by a new channel conductance dm, in parallel to the standard channel conductance gm as shown in Fig. 8.

4. Conclusion By the introduced fixed charge under the channel the electrostatic field in the channel region is affected measureable. In optimum condition the electrical current between drain and source reaches a new minimum at VDCT (VDCT < Vth) of about one magnitude order below the IOFF at VGate = 0. By this, a negative transconductance and a third state in the transfer slope is achieved at lower power consumption. This makes DC-FETs suitable to build complex logic functions or reduces the number of devices for established applications such as a small transistor static bit cell. By the same buried fixed charge under the gate a ballistic carrier transport effect was found at DCT transfer slope measurements, which increases the IDS about one magnitude order compared to the anticipated pinch off IDS level in mid range of VDD. The double

(b) 10^-4 10^-5

nDCT

=> SPICE model nFET

pFET

10^-6

IDS [A/µm]

(a)

Spice Model

nDCT

10^-7 10^-8 10^-9 10^-10 10^-11 10^-12

pFET

nFET

10^-13 -1.0 -0.8 -0.6 -0.4 -0.2

0.0

0.2

0.4

0.6

0.8

1.0

VGS [V] Fig. 7. (a) Proposed new circuit symbol for double channel transistor (DCT) device and first order SPICE model representation. (b) First order SPICE model simulation result of transfer slope for parallel nFET for high channel transconductivity (IDS) and pFET with low channel transconductivity for nDCT.

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channel effect and the ballistic carrier transport effect might support further application of DCT devices in low power and low VDD applications both. The double channel effect can be introduced in standard FET technology just by modifying implant scheme in a very cost effective manner and compatible to standard microelectronic planar and 3D technology. Further pitch downscaling in microelectronic will improve the double channel effect, because the ratio between gate surface charge to buried volume charge and the applied maximum VDD decrease both and enhance the found effects.

Acknowledgement For the effort at the lab measurements and the long lasting cooperation I like to thank very much Mr. Martin Majer.

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