- Email: [email protected]
Standards for μP systems (III)
Q Euromicro, 1976 North-HollandPublishing
Co., Amsterdam
STANDARDS FOR ~P SYSTEMS
(III)
Jean-Pierre VUILLE ALCYON Electronique & Physique SA Lausanne, Switzerland
it accepts different CPUs it carries all necessary signals for memory and I/0 operation with any kind of device it allows interrupts it allows DMA it has a 16-bit address and 16-bit word length capability.
My first article (Newsletter Nr. 3) about standards brought an encouraging mail back, confirming the interest in this subject. Unfortunately, the 5th issue of the Newsletter is not published when I am writing the present paper. As it contents a preliminary proposal for P/C boards and bus standards, it is preferable to wait for some comments about it before publishing the most interesting general remarks, as well as the further announced topics (suggestions for mother P/C boards, interrupt chains, list of connectors, basic schemas). This will probably be done in the next issue. Looking towards
Detailed diagrams As a matter of example, basic diagrams for the following P/C boards will be given in the next issue : CPU (with a few RAM and PROM, allowing to realize a minimal system with a single board) RAM ROM and/or PROM Parallel and serial I/O
16-bits processors
The preliminary proposal for bus standards (please refer to the above mentioned article in Newsletter Nr. 5, fig. 3) did not appear satisfactory after some time to the team which worked it out (Prof. J.-D. Nicoud, Swiss Federal Institute of Technology and a group of industrial engineers of West Switzerland) : all status and control signals carried by the bus suit as well an 8-bit or 16-bit processor. Consequently, why not to extend data path to 8 further lines, chosen among the free ones ? They will remain free as far as an 8-bit processor is used.
The purpose of such pub ications is essentially to demonstrate the flexibi ity of the bus and its signals. At this point, I would ike to raise up a discussion on the following subject : is it suitable, in the chosen standards, to bufferize all the elements connected to the bus ? If so, should non-inverting buffers be systematically implemented ?
This decision logically leads to group the 8 extra data lines either opposite to the former 8, or beside. The first solution was chosen, for P/C lay out ease. It was thus necessary to move up some control signals. The final proposal is described on fig. 2. Hardware functional
Advantages of bufferizing and I/0 capability.
: greater addressing
Drawbacks : chip count (in terms of cost, surface occupation and power consumption). The introduced complexity would be in opposition with the label of simplicity the standards should deserve.
standards
Prof. Nicoud's paoer "Hardware Standards for Microprocessors and Peripherals" (Euromicro Newsletter Nr. 3) described the function of all control signals. The exact timing characteristics are now given on fig. 3, 4, 5.
As a compromise, P/C boards could be designed with buffers and some copper ribbons to short-cut them when not used. Please write me your comments about it.
Please note that all control signals are active in the low state. Thus completed, the bus serves the desired purpose :
10
11
STANDARDS FOR ~P SYSTD,IS (I I I)
lU P
Systems
p/c boards
Fig. I 2.5
,~
components
1,6
~, _2"5min"
/// /
I
1.75 I°'s~--~-.~96,3-g,=
~
1,75
~]-~
'6x~'5°
+0,3
lO0 o
co e,,,.
2x22p
2x 37p
=
96,3~,= 100
-=
_
j.Ts &5 3 3,~ 2 33.~
...=4,5
_
I00
/
J.-P. VUILLE
12
IJP Systems board
P/C
to bus
Components
+24
AO/ = I
Vn.r
÷12 V
J
-9V
f
AD3 AD4 AD5 AD6 AD?" ----
IN TREO L 0 W HOL DREQLO W R E S E TLO W WRITELOW NOTYETLOW DA 0 DA 1 DA 2 DA 3 DA~ DA 5 DA6 DA 7
CHAIN)
{free free -5V +5V
GND
OV
3
~
• ÷2~ Vn.r
"
~12V
=6=
AD 0 AD I AD2
free
=
We/dings
. . 5 =
coding
(DAISY
connector
"~
"
7
--
=
8
"
"
9
----"
-I t O = =11 = = 12= =13 = =1/,, - 15= = 16 = =
~
free
17=
=18-19= = 20= = 21-= 22" = 23= =24= - 25~ -26= " 2?-" 28= = 29= =30, =31, = 32, = 33 = = 3Z." 35= " 36= =3?" =
Reor
c o ding ADS AD9 A D I0 A D 11 A D 12 A D 13 AD1/~ -- A D 1 5
I N TA CKL OW HOL DA CKLOW SYNLOW •- A D M E M L O W AD PERLOW DA 8 DA 9 D A 8 - D A 15 DA 10 For 16-bit CPU .- DA l l ( free with D A 12 8-bit C PU ) .... DA 13 DA 14 DA 15 free (DAISY CHAINJ free
-5V ÷5V GND
}
OV
view
Fi9 2
STANDARDS FOR pP SYSTE~ ( I I I )
13
pP Systems Timing
definition (See
of bus signals
notes at the
end)
1. MEMORY SIGNALS Ao
Read ADDR
½
WRITE A DMEM NO T YE
r'-
h
5 r
r
r
gMENORY DAT, t"
I__
7
(ADDR/ADMEM)>O (>200 ~') (ADDR/ADMEM) > 0 (WRITE/ADMEM)>O (>200"] (WRITE/ADMEM) >0 [ND TYET/ADMEi~I) < 100 * (DATA/A DMEM) ) d e p e n s i
7 q (DATA/ADDR) I
tL__
DA TA
s h 3 s 4 h 5 d Ga
8
m°nm°ry
s (DA TA/ADMEM-) depens on/uP h (DATA/ADMEki-) >20, < 300"
address set-up time address hold time write set-up time write hold time delay time of NOTYET access time from ADMEM qccess fime from ADDR set-up time of DATA hold time of DATA
NOTYET duration change ADMEM duration and allow to match processor and memory.
8
B.
Write A DDR
~_~1 S (ADDR/ADMEM)~200* &~
WRI TE ADMEM I L--
NOTYET S YN
i
2, 3, 4, 5 same as above G S {SYN/ADMEM)>50 7 s (DATA / S Y N - ) > O 8 s (DATA/ADMEM-) depens on memory 9 h (DATA/ADMEM-}>50 10 e (DATA/ADMEM} depens on pP
set-up time of SYN data set-up time before SYNdata set-up time data hold time data access time
Negative edge of SYN indicates that data is valid (necessary for dynamic memories).
6
DATA 10
,L=J
J.-P.
14
o
VUILLE
SIGNALS
PERIPHERAL
A. Input ADDR
~
WRITE ADMEM DA TA
I, 2, 3, 4 same as above 5 a (DATA/ADMEM) depends on peripheral, usually<300 _ 6 s (DATA/ADMEM-) depends on 7 h (DATA/ADMEM-) > 20
[ .~l
t 5
~PERIPHEttAL ~1_
m
DATA
6
r
B.
Output ADDR
2
WRI TE
~
J
I, 2, 3, 4 same as above 5 a (DATA/ADMEM) depends on 6 s (DATA/ADMEM-) depends on peripheral, usually < 3 0 7 h (DATA/ADMEM-) > 50
ADMEM DA TA
f
pP
5
_v
I -
DA TA
6
L I--
C°
Interrupt
I 2
IN TACK S YN DA TA
3 4 • ( INTERRUPT
T _
3
VECT(.
L
s (SYN/INTACK) > 50 a (DATA/INTACK) depends on peripheral, usually < 3 0 s (DATA/INTACK) depends on h (DATA/INTACK) > 50
Positive edge of SYN synchron interrupt requests and avoid new request to appear during SYN may not be available when processor is halted
STANDARDS FOR pP SYSTIi~,B (III)
3. D I R E C T
MEMORY
IS
ACCESS I
HOLDREQ ADDR l DA TA J
/uP A D R E S S
HOLDACK
i
I 2 s r DA
ADRESS
~
ADMEM
[
S YN
.I
4.
~,,.
s (ADDR ------/HOLDACK)> 0 floating set-up time 2 a (ADDR/HOLDACK) depends on peripheral, u s u a l l y < 2 0 0 P 3 h (ADDR/HOLDACK)<50 hold time d (HOLDACK/HOLDREQ) 4 depends on paP 5 d (HOLDACK-/HOLDREQ-) < 5 0 ,,, 6 a (ADDR/HOLDREQ-) >I00 depends on juP For relations between ADDR,ADMEM, WRITE, SYN and DATA, see memory section.
RESE T I ( ( R E S E T + ) > 5 0 #s,
RESE T
< 2 0 0 #s
NOTES • I) Timing values have been selected to match with n-channel uP (8080, 6800 etc.) 2) Values subject to change with faster p P are marked with a * 3) All times 4) All control
in ns unless otherwise noted. signals are inverted on the bus.
Co., Amsterdam
STANDARDS FOR ~P SYSTEMS
(III)
Jean-Pierre VUILLE ALCYON Electronique & Physique SA Lausanne, Switzerland
it accepts different CPUs it carries all necessary signals for memory and I/0 operation with any kind of device it allows interrupts it allows DMA it has a 16-bit address and 16-bit word length capability.
My first article (Newsletter Nr. 3) about standards brought an encouraging mail back, confirming the interest in this subject. Unfortunately, the 5th issue of the Newsletter is not published when I am writing the present paper. As it contents a preliminary proposal for P/C boards and bus standards, it is preferable to wait for some comments about it before publishing the most interesting general remarks, as well as the further announced topics (suggestions for mother P/C boards, interrupt chains, list of connectors, basic schemas). This will probably be done in the next issue. Looking towards
Detailed diagrams As a matter of example, basic diagrams for the following P/C boards will be given in the next issue : CPU (with a few RAM and PROM, allowing to realize a minimal system with a single board) RAM ROM and/or PROM Parallel and serial I/O
16-bits processors
The preliminary proposal for bus standards (please refer to the above mentioned article in Newsletter Nr. 5, fig. 3) did not appear satisfactory after some time to the team which worked it out (Prof. J.-D. Nicoud, Swiss Federal Institute of Technology and a group of industrial engineers of West Switzerland) : all status and control signals carried by the bus suit as well an 8-bit or 16-bit processor. Consequently, why not to extend data path to 8 further lines, chosen among the free ones ? They will remain free as far as an 8-bit processor is used.
The purpose of such pub ications is essentially to demonstrate the flexibi ity of the bus and its signals. At this point, I would ike to raise up a discussion on the following subject : is it suitable, in the chosen standards, to bufferize all the elements connected to the bus ? If so, should non-inverting buffers be systematically implemented ?
This decision logically leads to group the 8 extra data lines either opposite to the former 8, or beside. The first solution was chosen, for P/C lay out ease. It was thus necessary to move up some control signals. The final proposal is described on fig. 2. Hardware functional
Advantages of bufferizing and I/0 capability.
: greater addressing
Drawbacks : chip count (in terms of cost, surface occupation and power consumption). The introduced complexity would be in opposition with the label of simplicity the standards should deserve.
standards
Prof. Nicoud's paoer "Hardware Standards for Microprocessors and Peripherals" (Euromicro Newsletter Nr. 3) described the function of all control signals. The exact timing characteristics are now given on fig. 3, 4, 5.
As a compromise, P/C boards could be designed with buffers and some copper ribbons to short-cut them when not used. Please write me your comments about it.
Please note that all control signals are active in the low state. Thus completed, the bus serves the desired purpose :
10
11
STANDARDS FOR ~P SYSTD,IS (I I I)
lU P
Systems
p/c boards
Fig. I 2.5
,~
components
1,6
~, _2"5min"
/// /
I
1.75 I°'s~--~-.~96,3-g,=
~
1,75
~]-~
'6x~'5°
+0,3
lO0 o
co e,,,.
2x22p
2x 37p
=
96,3~,= 100
-=
_
j.Ts &5 3 3,~ 2 33.~
...=4,5
_
I00
/
J.-P. VUILLE
12
IJP Systems board
P/C
to bus
Components
+24
AO/ = I
Vn.r
÷12 V
J
-9V
f
AD3 AD4 AD5 AD6 AD?" ----
IN TREO L 0 W HOL DREQLO W R E S E TLO W WRITELOW NOTYETLOW DA 0 DA 1 DA 2 DA 3 DA~ DA 5 DA6 DA 7
CHAIN)
{free free -5V +5V
GND
OV
3
~
• ÷2~ Vn.r
"
~12V
=6=
AD 0 AD I AD2
free
=
We/dings
. . 5 =
coding
(DAISY
connector
"~
"
7
--
=
8
"
"
9
----"
-I t O = =11 = = 12= =13 = =1/,, - 15= = 16 = =
~
free
17=
=18-19= = 20= = 21-= 22" = 23= =24= - 25~ -26= " 2?-" 28= = 29= =30, =31, = 32, = 33 = = 3Z." 35= " 36= =3?" =
Reor
c o ding ADS AD9 A D I0 A D 11 A D 12 A D 13 AD1/~ -- A D 1 5
I N TA CKL OW HOL DA CKLOW SYNLOW •- A D M E M L O W AD PERLOW DA 8 DA 9 D A 8 - D A 15 DA 10 For 16-bit CPU .- DA l l ( free with D A 12 8-bit C PU ) .... DA 13 DA 14 DA 15 free (DAISY CHAINJ free
-5V ÷5V GND
}
OV
view
Fi9 2
STANDARDS FOR pP SYSTE~ ( I I I )
13
pP Systems Timing
definition (See
of bus signals
notes at the
end)
1. MEMORY SIGNALS Ao
Read ADDR
½
WRITE A DMEM NO T YE
r'-
h
5 r
r
r
gMENORY DAT, t"
I__
7
(ADDR/ADMEM)>O (>200 ~') (ADDR/ADMEM) > 0 (WRITE/ADMEM)>O (>200"] (WRITE/ADMEM) >0 [ND TYET/ADMEi~I) < 100 * (DATA/A DMEM) ) d e p e n s i
7 q (DATA/ADDR) I
tL__
DA TA
s h 3 s 4 h 5 d Ga
8
m°nm°ry
s (DA TA/ADMEM-) depens on/uP h (DATA/ADMEki-) >20, < 300"
address set-up time address hold time write set-up time write hold time delay time of NOTYET access time from ADMEM qccess fime from ADDR set-up time of DATA hold time of DATA
NOTYET duration change ADMEM duration and allow to match processor and memory.
8
B.
Write A DDR
~_~1 S (ADDR/ADMEM)~200* &~
WRI TE ADMEM I L--
NOTYET S YN
i
2, 3, 4, 5 same as above G S {SYN/ADMEM)>50 7 s (DATA / S Y N - ) > O 8 s (DATA/ADMEM-) depens on memory 9 h (DATA/ADMEM-}>50 10 e (DATA/ADMEM} depens on pP
set-up time of SYN data set-up time before SYNdata set-up time data hold time data access time
Negative edge of SYN indicates that data is valid (necessary for dynamic memories).
6
DATA 10
,L=J
J.-P.
14
o
VUILLE
SIGNALS
PERIPHERAL
A. Input ADDR
~
WRITE ADMEM DA TA
I, 2, 3, 4 same as above 5 a (DATA/ADMEM) depends on peripheral, usually<300 _ 6 s (DATA/ADMEM-) depends on 7 h (DATA/ADMEM-) > 20
[ .~l
t 5
~PERIPHEttAL ~1_
m
DATA
6
r
B.
Output ADDR
2
WRI TE
~
J
I, 2, 3, 4 same as above 5 a (DATA/ADMEM) depends on 6 s (DATA/ADMEM-) depends on peripheral, usually < 3 0 7 h (DATA/ADMEM-) > 50
ADMEM DA TA
f
pP
5
_v
I -
DA TA
6
L I--
C°
Interrupt
I 2
IN TACK S YN DA TA
3 4 • ( INTERRUPT
T _
3
VECT(.
L
s (SYN/INTACK) > 50 a (DATA/INTACK) depends on peripheral, usually < 3 0 s (DATA/INTACK) depends on h (DATA/INTACK) > 50
Positive edge of SYN synchron interrupt requests and avoid new request to appear during SYN may not be available when processor is halted
STANDARDS FOR pP SYSTIi~,B (III)
3. D I R E C T
MEMORY
IS
ACCESS I
HOLDREQ ADDR l DA TA J
/uP A D R E S S
HOLDACK
i
I 2 s r DA
ADRESS
~
ADMEM
[
S YN
.I
4.
~,,.
s (ADDR ------/HOLDACK)> 0 floating set-up time 2 a (ADDR/HOLDACK) depends on peripheral, u s u a l l y < 2 0 0 P 3 h (ADDR/HOLDACK)<50 hold time d (HOLDACK/HOLDREQ) 4 depends on paP 5 d (HOLDACK-/HOLDREQ-) < 5 0 ,,, 6 a (ADDR/HOLDREQ-) >I00 depends on juP For relations between ADDR,ADMEM, WRITE, SYN and DATA, see memory section.
RESE T I ( ( R E S E T + ) > 5 0 #s,
RESE T
< 2 0 0 #s
NOTES • I) Timing values have been selected to match with n-channel uP (8080, 6800 etc.) 2) Values subject to change with faster p P are marked with a * 3) All times 4) All control
in ns unless otherwise noted. signals are inverted on the bus.