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Journal Pre-proofs State-of-the-art low frequency noise performance of n-MOSFET for analog/RF applications E.G. Ioannidis, K. Rohracher, H. Enichlmair PII: DOI: Reference:

S0038-1101(19)30567-2 https://doi.org/10.1016/j.sse.2019.107754 SSE 107754

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Solid-State Electronics

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6 September 2019 11 December 2019 19 December 2019

Please cite this article as: Ioannidis, E.G., Rohracher, K., Enichlmair, H., State-of-the-art low frequency noise performance of n-MOSFET for analog/RF applications, Solid-State Electronics (2019), doi: https://doi.org/10.1016/ j.sse.2019.107754

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State-of-the-art low frequency noise performance of n-MOSFET for analog/RF applications

E. G. Ioannidis, K. Rohracher and H. Enichlmair. ams AG Tobelbader Strasse 30, 8141 Premstaetten, Austria e-mail: [email protected]

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Abstract

In this paper, we present the results of low frequency noise (LFN) characterization of n-MOSFET. We are going to show that the device treated with the new anneal step at the end of the process shows outstanding LFN performance. Results demonstrate that the new implemented process change can improve the noise level up to ~6x. The LFN variability of the device under test improved up to ~2x.

Keywords: low frequency noise, variability, CMOS, n- MOSFET

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1. Introduction Low frequency noise is one of the most important parameters in analog and RF design [1]. In theory, an amplifier can amplify an arbitrarily small signal to any desired level [2]. The reality is completely different. There is a physical limit to the smallest signal that can be amplified originating from the noise. In this respect, there is still a demand from analog and RF circuit designers for active and passive devices that shows outstanding low frequency noise performance. In this work, we are focusing on LFN characterization of n-MOSFET from a CMOS technology node. The development of a CMOS technology node has many aspects. In general, the node should meet some well-defined requirements. The hierarchy of the specifications depends heavily on the target applications. Usually, the electrical parameters of all the devices should be centered and a sufficient yield should be reached. Thus, the process engineers should be extremely cautious when they need to tune the noise performance. It is mandatory to keep the DC performance unchanged when trying to improve the noise or else we can enter an endless loop of process changes. There is a thin line between DC analog performance and noise reduction that it should not be crossed. There are available techniques to reduce noise in a circuit by design which is not the focus of this work. Another way is to optimize the process itself to reduce the noise on the device level [3,17-19]. A very important issue when you are tuning the process is not to alter the electrical behavior of the device. In this experiment, we created a process split that improved the noise of n-MOSFET by a factor of six. In addition, the low frequency noise variability of the device improved by a factor of two. The DC behavior was not altered. The device can be used from designers and process engineers 3

for high performance analog applications where noise is on the critical path of overall performance. The results of this work can be used in parallel with some previous investigations of an anneal step after gate stack formation [17] and the impact of different Lightly Doped Drain (LDD) implants, gate oxide thickness and different well doping [18-19]. 2. Experiment Electrical measurements were carried out on n-MOSFET transistors issued from a bulk CMOS technology node. The channel material is Si. We characterized the following Width/Length devices: 10/0.35, 10/1.2 and 0.36/0.35μm. We focus the LFN analysis for the device with W/L=10/1.2μm and we used the other geometries for variability analysis purposes. The gate stack consists of SiO2-based oxide dielectric with equivalent oxide thickness around 9.3nm. The gate is polysilicon. In the following, we are going to present in more details the different process splits investigated in this experiment. Table 1 summarizes all the changes. At the end of CMOS process an anneal step is applied called “alloy step”. The temperature is compatible with an AlCu backend process in highly H2 rich ambient. This saturates dangling bonds in gate oxide interface resulting in more stable device LFN performance. Within this experiment the duration of this anneal step increased. We performed electrical DC characterization in order to verify the functionality of the device under test and use the analysis results for LFN purposes. LFN measurements performed using a 4

Cascade Edge system [4]. For LFN analysis we biased the drain voltage VD with 1.6, 2.75 and 3.3V and the gate voltage from weak to strong inversion. Statistical variability measurements performed for drain bias at 3.3V and various gate voltages. This experiment focuses on the improvement of LFN and statistical variability for analog/RF applications. The experimental bandwidth is 10Hz to 1kHz. All the spectra presented in this work are the median of at least 10 dies for LFN analysis. All noise parameters were extracted at f=10Hz. The statistical noise variability performed for at least 60 dies around the wafer. The methodology flow starts with the investigation of the basic electrical performance followed by the noise analysis. We verified the noise model that can fit the experimental data and we compare the noise performance using the main parameters of this model. Last, we explore how the different process affects the LFN variability performance of the measured devices. There are two dominant models that explains the flicker noise in MOSFETs. The carrier number fluctuations (CNFs) (Equs. 1-2 Table 2) [6] due to carrier trapping/detrapping from traps located in the interface between the gate and channel. The correlated mobility fluctuations (CMFs) model assumes that the charge fluctuations creates carrier mobility fluctuations, Equs. 3-4 [8-10]. On the other hand, the Hooge mobility fluctuations assumes that the flicker noise arise from fluctuations of the carrier mobility possibly through a fluctuation of the scattering cross section entering the collision probability [7].

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LFN is subjected to variability as any other parameter that can affect the functionality of analog and digital circuits [5,11-12]. In this regard, it is important to investigate the LFN statistical variability in parallel with standard noise characterization and provide to circuit designers an overall performance for low frequency noise. We followed the analysis presented in [13-14]. We calculated a LFN/RTN matching dynamic parameter, as in static mismatch analysis, from the slope of σVth versus the reciprocal of device area. We used this parameter to compare the different process splits and evaluate the LFN variability performance.

3. Results and discussion 3.1 DC analysis In Fig. 1, the input characteristics of n-MOSFET with W/L = 10/1.2μm in the saturation region of operation, for both process split wafers, are plotted. The different process did not alter the DC performance of the devices. Similar results were obtained for the transconductance to drain current values shown at Fig. 2. The DC analysis of the different wafers revealed no significant difference on the performance of n-MOSFET for all different geometries and drain bias conditions. We believe that since the equivalent oxide thickness values, Fig. 8, due to the anneal is almost unchanged. The static DC performance of the device is not altered since is mainly dominated by the Cox.

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3.2 LFN analysis Figs. 3-4 shows the median drain-current spectra versus frequency for various drain current and drain voltage bias of 3.3V of n-MOSFET device with W/L = 10/1.2μm for both wafers. The shape of the spectra is clearly 1/f -like for all the bias conditions with γ values close to 1. Same behavior was observed for all drain biases. The next step in our analysis procedure is the identification of the model that best fits our experimental data. For this purpose, we plotted on Figs. 5-6, the square root of the input-referred gate voltage noise versus ID/GM, following the general CMF model of [10], see Equ. 3 Table 2. A linear relation of √SVG versus ID/GM is observed for both process split wafers. In both figures the square root of the input-referred gate voltage from various drain bias is presented indicating the validity of the CMF model in all region of operation. In Fig. 7, a fit of the CMF model for one drain bias, VD=3.3V in this case, is presented to show the good agreement of the model with the experimental data. Table 3 summarizes the basic parameter values of the general CMF model according the Equs. 2 and 3 of Table 2. The new alloy wafer shows significant improvement in LFN. The volumetric trap density of the n-MOSFET is improved almost ~6x using the new process flow. It appears that the anneal step with much higher duration better passivates traps in the Si/SiO2 interface of relevant device regions. The effective Coulomb scattering coefficient values are similar to the reported in literature [10]. 7

For both wafers the interface trap density values extracted from LFN data are state-of-the-art as can be seen by the comparison of the values with those noted in [15] for similar n-MOSFET EOT devices. To the best of our knowledge this low frequency noise performance of n-MOSFET is unique in the literature and can be used from analog/RF designers for any design where the noise is the critical parameter requirement. On the other hand, the values of Ω, related to the effective Coulomb scattering coefficient and gate oxide capacitance, are increased by ~2x. This increase could be explained through the increase of the effective Coulomb scattering coefficient since the equivalent oxide thickness (EOT) remained unchanged, Fig. 8. The EOT is calculated from a large area n-MOSFET capacitor from the formula tox=ε0.εox/Cox where ε0 is 3.9, εox=8.85*10-12 F/m and Cox is measured in accumulation.

3.3 LFN variability analysis The last section of this manuscript deals with the investigation of low frequency noise variability. Figs 8-9 shows the dispersion in the drain current noise for two different area devices and process split wafers. It can be seen how important is the modelling and characterization of low frequency noise variability for the circuit designers. It is essential for any circuit simulator to include statistical dispersion data in order to give a realistic worst case simulation to the designers.

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One of the most efficient ways to model LFN variability is using the methodology developed in [13-14]. Based on this analysis, we calculated for each measured device the σVTH by integration of the corresponding spectrum in a frequency range fmin (10Hz) to fmax (1kHz):

[5] As can be seen from the Figs 10-11, the median values of σVTH versus drain current are constant. Based on these results we plotted the median σVTH versus the reciprocal of the device area for both processed wafers for ID=1μA, Fig. 12. From the slope of the curves, we extracted a similar value to static mismatch that corresponds to dynamic variability, Am in mV.μm. There is an improvement of dynamic variability by a factor of two for the new alloy processed wafer. This improvement can be directly related to the reduction of the volumetric trap density observed from standard LFN analysis and in the work of [16]. According to this work, the average noise power is proportional to trap density, while the standard deviation of noise power is proportional to the square root of trap density, Equs (3-5) of [16]. The LFN variability improved up to ~2x in our case which is very close to the value predicted in [16].

4. Conclusions LFN statistical characterization performed on n-MOSFET. Results showed that the general CMF model valid in all regions of operation can explain the experimental data. The basic 9

parameters of this model used to compare two different processed wafers. The main difference between these wafers were the duration of the final anneal step. The volumetric trap density of the measured devices were ~10x lower compared to other n-MOSFET with similar EOT values that were found in literature. Furthermore, the new alloy wafer improved the trap density by a factor of six compared to the standard alloy wafer. The dynamic-mismatch parameter, extracted from statistical LFN data, improved by a factor of two. We believe this device can be used from analog/RF designers for circuits where the noise is of paramount importance.

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References [1] B. Razavi, “CMOS technology characterization for analog and RF design,” IEEE Journal of SolidState Circuits, vol. 34, no. 3, pp. 268-276, March 1999. [2] W. M. Leach, “Fundamentals of low-noise analog circuit design,” Proceedings of the IEEE, vol. 82, no. 10, pp. 1515-1538, Oct. 1994. [3] Philippe Gaubert and Akinobu Teramoto, “New Processes and Technologies to Reduce the Low -Frequency Noise of Digital and Analog Circuits,” Open access Intech, http://dx.doi.org/10.5772/64630, Oct. 2016. [4] https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwi5wt_ im5HkAhUNz4UKHVWCvMQFjAAegQIARAC&url=https%3A%2F%2Fwww.electronicsdatasheets.com%2Fdownload %2F52cfe121e34e24cc6d56abd5.pdf%3Fformat%3Dpdf&usg=AOvVaw3L7aTxfpMdw_Ax9I1H3 0m7 [5] E. G. Ioannidis et al., “Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors,” 2011 International Electron Devices Meeting, Washington, DC, 2011, pp. 18.6.1-18.6.4. [6] A. L. McWhorter, Semiconductor Surface Physics, H. Kingston, Ed. Philadelphia, PA, USA: Univ. Pennsylvania Press, 1957, p. 207. 11

[7] F. N. Hooge, “1/ f noise is no surface effect,” Phys. Lett., vol. 29, no. 3, pp. 139–140, 1969. [8] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in metaloxide-semiconductor field-effect transistors,” IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654–665, Mar. 1990. [9] G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, and J. Brini, “Improved analysis of low frequency noise in field-effect MOS transistors,” Phys. Status Solidi A, vol. 124, no. 2, pp. 571– 581, 1991. [10] E.G. Ioannidis, C.A. Dimitriadis, S. Haendler, R.A. Bianchi, J. Jomaah, G. Ghibaudo, “Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs,” Solid-State Electronics 76 (2012). [11] K. Takeuchi, T. Nagumo, S. Yokogawa, K. Imai, Y. Hayashi, “Single charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude,” 2009 Symposium on VLSI technology digest of Technical papers. p. 54–55. [12] D.J. Frank, Y. Taur, “Design considerations for CMOS near the limits of scaling,” Solid State Electronics, pp 315-320, 2002. [13] E. G. Ioannidis, S. Haendler, C. G. Theodorou, N. Planes, C. A. Dimitriadis and G. Ghibaudo, “Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs,” 2014 44th European Solid State Device Research Conference (ESSDERC), Venice, 2014, pp. 214-217.

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[14] C. G. Theodorou, E. G. Ioannidis, S. Haendler, N. Planes, E. Josse, C. A. Dimitriadis, G. Ghibaudo, “New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs,” 2015 IEEE International Reliability Physics Symposium, Monterey, CA, 2015, pp. XT.1.1-XT.1.6. [15] E.G. Ioannidis, S. Haendler, C.G. Theodorou, S. Lasserre, C.A. Dimitriadis, G. Ghibaudo, “Evolution of low frequency noise and noise variability through CMOS bulk technology nodes from 0.5 μm down to 20 nm,” Solid-State Electronics 95 (2014). [16] G. I. Wirth, R. da Silva and R. Brederlow, “Statistical Model for the Circuit Bandwidth Dependence of Low-Frequency Noise in Deep-Submicrometer MOSFETs,” in IEEE Transactions on Electron Devices, vol. 54, no. 2, pp. 340-345, Feb. 2007. [17] E.G. Ioannidis, W.C. Pflanzl, E. Stueckler, V. Vescoli, S. Carniello, E. Seebacher, “Impact of hydrogen anneal on low frequency noise of n- and p-MOSFET,” Solid-State Electronics ,Volume 126, December 2016. [18] E.G. Ioannidis, K. Rohracher, F. Roger, W.C. Pflanzl, F.P. Leisenberger, E. Wachmann, E. Seebacher, V. Vescoli, “Impact of source/drain and bulk engineering on LFN performance of nand p-MOSFET,” Solid-State Electronics,Volume 135, September 2017. [19] E.G. Ioannidis, F.P. Leisenberger, H. Enichlmair, “Low frequency noise investigation of nMOSFET single cells for memory applications,” Solid-State Electronics, Volume 151, January 2019.

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Tables and Figures captions Table 1. Process split explanation Table 2. CNF and CMF low frequency noise model. Table 3. Typical values of SVFB, Ω, Nt and αsc.μeff for both wafers Fig.1. ID-VG curves for W/L=10/1.2μm for VD=3.3V in lin-lin and log-lin scale for n-MOSFET. Fig.2. GMID-ID curves for W/L=10/1.2μm for VD=3.3V in lin-log scale for n-MOSFET. Fig.3. Ten dies-median drain-current power spectral density versus frequency for std alloy processed wafer at VD=3.3V and various gate biases for n-MOSFET with W/L = 10/1.2μm. Fig.4. Ten dies-median drain-current power spectral density versus frequency for new alloy processed wafer at VD=3.3V and various gate biases for n-MOSFET W/L = 10/1.2μm. Fig.5. Square root of input-referred gate voltage noise versus ID/GM for n-MOSFET W/L = 10/1.2μm various drain voltage bias for std alloy processed wafer (symbols) and the corresponding linear fit (straight line). 14

Fig.6. Square root of input-referred gate voltage noise versus ID/GM for n-MOSFET W/L = 10/1.2μm various drain voltage bias and new alloy processed wafer (symbols) and the corresponding linear fit (dashed line). Fig.7. Normalized drain current power spectral density (symbols) for n-MOSFET W/L = 10/1.2 μm and corresponding CMF (solid line) versus drain current for std and new alloy wafer and drain bias 3.3V. Fig.8. Box plot of the equivalent oxide thickness (EOT) for a large area capacitor n-MOSFET measured on 10 sites from std and new alloy wafer. Fig.9. Drain current noise SID as a function of frequency for n-MOSFET W/L=0.36/0.35μm for 60 sites at VD=3.3V and ID=1μA for the std alloy wafer. Fig.10. Drain current noise SID as a function of frequency for n-MOSFET W/L=10/0.35μm for 60 sites at VD=3.3V and ID=1μA for the new alloy processed wafer. Fig.11. Mean value (60 dies) of σVTH versus drain current for different geometries n-MOSFET at VD=3.3V for the std alloy processed wafer. Fig.12. Mean value (60 dies) of σVTH versus drain current for different geometries n-MOSFET at VD=3.3V for the new alloy processed wafer. Fig.13. Mean value (60 dies) of σVTH versus 1/sqrt(W.L) for n-MOSFET at VD=3.3V,ID=1μA for all processed wafers.

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Table 1. Process split analysis Process split

Description

Std_alloy

Anneal in Highly concentrated H2 chamber for A hrs at temperature of B oC

New_alloy

Anneal in Highly concentrated H2 chamber for 4*A hrs at temperature of B oC

Table 2. CNF and CMF low frequency model

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CNF:

SID GM 2 ( ) .SVFB (1) 2 ID ID

CNF: SVFB 

CMF: SVG  SVFB  . SVFB .

CMF:

q 2 .kT ..N t (2) W .L.C ox2 . f 

ID (3) GM

SID GM 2 ID 2 ( ) .SVFB.(1  . ) (4) 2 ID GM ID

Where Ω=asc.μeff.Cox, asc is the Coulomb scattering coefficient, μeff is the effective carrier mobility, Cox is the gate dielectric capacitance per unit area, SVFB is the flat-band voltage spectral density, SVG=fγ.SID/GM2 the input voltage spectral density, ID is the drain current, GM is the transconductance, SID is the drain current noise spectrum, kT is the thermal energy, λ is the tunnel attenuation distance (≈0.1nm for SiO2), q is the elementary charge, f is the frequency, γ is the slope of the drain current spectrum (close to 1) and Nt is the gate dielectric trap density in cm-3.eV-1.

Table 3. Basic parameters values of CMF model

std_alloy new _alloy

SVFB(V2) 1.81E-13 3.09E-14

Ω(V-1) 5.48 13.72

Fig. 3

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Nt(cm-3.eV-1) αsc.μeff(cm2/C) 1.45E+06 4.69E+14 7.99E+13 3.63E+06

Fig. 1

Fig. 2

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Fig. 9

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Fig. 11

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Fig. 13

Dr. Eleftherios G. Ioannidis was born in Kilkis, Greece. He received the B.Sc. degree in physics and the M.Sc. degree in electronic physics from the Aristotle University of Thessaloniki (AUTH), Thessaloniki, Greece, in 2006 and 2010, respectively. He received the Ph. D. degree in nanoelectronics from the AUTH and INPG in 2013. He is currently working with ams AG in Premstaetten, Austria in Device R&D group. His current research interests include process development, reliability and electrical/optical characterization of passive/active CMOS components and TCAD simulation.

In this paper, we present the results of low frequency noise (LFN) characterization of n-MOSFET. We are going to show that the device treated with the new anneal step at the end of the process shows outstanding LFN performance. Results demonstrate that the new implemented process change can improve the noise level up to ~6x. The LFN variability of the device under test improved up to ~2x. 24

Declaration of interests

☒ The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

☐The authors declare the following financial interests/personal relationships which may be considered as potential competing interests:

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