- Email: [email protected]
Statistical metrology for characterizing CMP processes
ELSEVIER
Microelectronic Engineering 33 (1997) 231-240
Statistical metrology for characterizing CMP processes Sharad Prasad a'*, W. Loh a, A. Kapoor a, E. Chang b, B. Stine b, D. Boning b, J. Chung b aLSI Logic Corp, 1635 McCarthy Blvd., Milpitas, CA 95035, USA bMIT EECS, Cambridge, MA 02139, USA Abstract CMP processes are used to planarize layers; however, variations in ILD thickness due to various layout factors can affect the modelling of interconnect parameters. In this paper an overview of 'Statistical Metrology' for CMP processes is presented. Using statistical metrology for CMP the process or interconnect design rules can be optimized for minimal variations.
1. Introduction Future VLSI scaling will critically depend upon the ability to fully model key interconnect processes and limit the interconnect parameter variations. Oxide CMP improves planarization but remains hampered by systematic and random sources of (InterLayer Dielectric) ILD thickness variation at the lot, wafer, die and pattern levels. As the critical dimensions shrink it is important to limit the interconnect parameter variations. Lot-to-lot variations (Fig. 1) can be caused by drifts in equipment or shifts in equipment parameters. Within a lot the variations could be caused by non-uniform processing or equipment variations in a single batch process will give rise to statistical distribution within a lot. Wafer-to-wafer and lot-to-lot variations have received significant attention and can be managed by controlling process parameters and equipment. However, die-to-die variations and variations of ILD thickness within a die are becoming increasingly important. The intradie variation is often larger than the variation within the wafer and can also be larger than the lot-to-lot or wafer-to-wafer variations. This means that the same structure at the same location within different dies would vary much less than structures within the same die.
2. Statistical metrology 2.1. Measurement of variations Statistical metrology is a methodology to assess variations and assess the impact of those variations. :g
Corresponding author. Fax: (1-408) 954-3458; e-mail: [email protected]
0167-9317/97/$17.00 Copyright 01997 Elsevier Science B.V. All rights reserved PII S0 1 6 7 - 9 3 1 7 ( 9 6 ) 0 0 0 5 2 - 4
232
S. Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
°.*"
-- [
/L %
llr~liltl~ally
SimUl.,/
hmld
Wdldlon
I~mr
Fig. 1. Sources of variations. Process:Oxide Polishing Oxlcle
Before PlanarizatJon
Met~
After Planerization
Test Structure ,late
I
:tor ._, _ _ .
dous J~ctom
(w! various layout faotors)
Fig. 2. (a) Detecting interconnect variation. (b) Test structures with possible variations.
S. Prasad et al. I Microelectronic Engineering 33 (1997) 231-240
233
Variations can be assessed by measuring the parameter and understanding the process and device variations in that parameter as well as the spatial and feature dependencies. This requires a large number of measurements in order to separate the confounding sources of variations. In the case of CMP the ILD thickness can be extracted from the electrical measurements of metal-to-metal to capacitors (Fig. 2). The test capacitors have a uniform top plate and a bottom layer consisting of a ladder structure with various combinations of layout factors including finger width, spacing, orientation, finger length and number of fingers [1,2]. For accurate measurement of the capacitance the exact physical parameters of the capacitor should be known. Van der Pauw and Kelvin structures are used to de-couple linewidth and thickness variations [1] (Fig. 3). To measure the ILD variations a short loop experiment is run. On unstructured wafers a PECVD TEOS layer is deposited. Metal 1 is then deposited and structured. An ILD layer is deposited and then planarized by CMP to reach the target ILD thickness. Via holes are etched in the ILD and tungsten vias defined. Metal 2 is deposited and structured and then the chip is passivated. Using automated measurement techniques and 2-D capacitance simulation the ILD thickness can be extracted from the
II
Fig. 3. Probe and chip layout.
234
S. Prasad et al. / Microelectronic Engineering 33 (1997) 2 3 1 - 2 4 0
Capacitance vs. ILD Thickness Q 0 ~
+ X__
\~ ~il~!!~=,
o
width width width width width
= 5.4 = 5.2 = 5.0 = 4.8 - 4.6
um um um um um
\ \'~%~ x+~oo
~x+Aoa ~x~.A,o, o, ~x +.A.°,a" -x+A.°.~-o. "x+.A..oa. -x +& a
x.+..Ao,O, a
x.+.,-~o., o x..+A.O.o.a x"x .+ -.'AO.o'O. A . o
x x-x:*.~:=.~.g:a.°. -+8.-oa.
x-x.*.,:A,~.o.=,o x.x.~ +:~ ~:~.~:~.°..
X-x.~-.:~.Z:?-~:R....
.X.x,+.¢.&...,.
012
0'.3
014
0'.5 ILD thickness (um)
0'.6
0'.7
Fig. 4. Extracting ILD thickness from capacitance measurements. capacitance and linewidth measurements [1] (Fig. 4). Fig. 5 shows the raw dielectric thickness obtained on a single wafer. These variations need to be decomposed to understand the cause of variation.
2.2. Variation decomposition In Fig. 6 an overview of variation decomposition is illustrated. The ILD thickness variation can be assumed to be a sum of wafer-level, die-level and some die-wafer interaction variations [2]. Wafer-level variations are low frequency and smooth (Fig. 7) and these variations can be extracted using a moving average estimator. Wafer-level variations are independent of die patterns. Die-level variations are pattern dependent and layout dependent. Die-level variations are identical from die to die. These variations can be extracted using a 2-D Fourier analysis [2,3] (Fig. 8). Clearly, layout factors like variation of finger width length etc. influence the die level ILD thickness variation. Die-wafer interactions are dependent upon the die and its position on the wafer. Finally, the remaining variations are residuals (Fig. 9).
3. C M P study Using the short loop test a screening experiment is carried out. A half-fractional factorial design of experiments with six layout factors was carried out. This gave 33 structures which were randomly
S, Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
235
(a)
,3
J
Ji
:! |
:.
•
[ 2O
10
(lie n u t t i e r
...':'....
(b)
."
. ' . -..
"
a
_J 60
60
0
Y
X Fig. 5. (a) Raw interconnect dielectric thickness data. (b) Thickness variations across wafer•
236
S. Prasad et al. / Microelectronic Engineering 33 (1997) 2 3 1 - 2 4 0
:iii:i~,~:!i!l I
vL,Ln'In waf,,-o •
,.l~.'r~~ t . ' .~.'] 1
n~'U~len
t>
Total Rulduafs
Fig. 6. Variation decomposition overview.
distributed on the die. This initial experiment showed die-level variations as seen in Fig. 8 [1,2], and identified what factors are important. In particular, the die-level variation is due to layout features and neighborhood distances within the die [1]. A second set of experiments which mimics ASIC-like design was done. This chip is a full factorial design of five factors (linewidth and spacing, finger length, number of fingers and the geometrical orientation) in combination with four levels of interaction distance, yielding 129 unique structures (including several center-point structures). Additionally, test structures with and without dummy fill are also included to study the effect of dummy lines on ILD thickness (Fig. 10).
Wafer 21 - - Wafer Level Variation
''i'" .!
:
:...
:
:
.
I
...
' I
60
I-,.
60
Fig. 7. Wafer-scale dielectric thickness variations.
S. Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
237
4o 15 1
~
20
0 0 Fig. 8. Variation source: Die level.
Wafer Levd_..~.. o.s Variations
o.4 50
0 0 +
Raw Data
0.40"5 .
~
! 50
o o Die Level
o.~i
Die-Wafer .............~-0.1 Interaction
Residuals
50
~
0 0
50 +
0.1 o
-0.1
50
Fig. 9. Pattern variation sources.
0 0
50
238
S. Prasad et al. / Microelectronic Engineering 33 (1997) 2 3 1 - 2 4 0
/ Run .by Run Variation
Within Wafer Variation Variation
Process Control S ategy ¥
Optimize process to minimize layout dependence: .................... :...............:-..............~.... I~ilil 2
",.i
'..i
1 1000~'--"~'----~400 6OO
2(X)
0
-zt~
"-40
Fig. 10. Metrology to optimize process.
4. Impact Using statistical metrology techniques
(a) the CMP process could be optimized; (b) interconnect design rules could be modified. The CMP process could be characterized, controlled and optimized for manufacturing. The process could be optimized so that die-level variations are minimal due to layout factors (Fig. 10). The process could be optimized so that, depending upon a product for a given range of layout factors, the die-level and wafer-level variations are within product specifications (Fig. 1 l). Finally, where the layout factors cannot be pre-determined in an ASIC-like environment a dummy fill approach could be used. The interconnect design rules could be determined such that the layout density range is within a very tight region where the ILD thickness variation is very small (Fig. 12). This would ensure very tight regulation of interconnect device parameters such as interconnect capacitance, and crosstalk between interconnect lines.
S. Prasad
Y
et al. I Microelectronic
Engineering
33 (1997)
231-240
Vary density, circuit block separation More dense
Less dense
Fig. I I. CMP Metrology
..,.“i
. . ;:+..f,
for interconnect
..
. j#
.J_. .. .Ii .. :.i,....,,...I ,,,...._.i .
..
design rules.
j ..,,..... f .,...._,, f . .
. .. i .. . ... i
.
.. i . .. j.. ..__.. i..,....., j ,.....,.. 4 .._...,
..
j
j
j
1
1
!
4 . ... t . . . i .. I
:
I
:
j ..
!
I 4
I 1 . . .
t
. . y
.
..I.
I!
,....,. I_;. ... .j .. . .i .. 7I . .. tI . ... ii.. . i’! ... ..&.... I: I i rj - ! Ij i ; ! ’ $ .‘a O!. &, .: 0: A :* a% 0.1 ti Corfventional Layout Density Range Fig. 12. Interconnect
dielectric
thickness
relationship
to density.
239
240
S. Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
References [1] E. Chang et al., IEDM Tech. Digest (1995). [2] R. Divecha et al., Proc. 1st IEEE Int. Workshop on Statistical Metrology, June 1996. [3] B. Stine et al., VMIC (1996).
Microelectronic Engineering 33 (1997) 231-240
Statistical metrology for characterizing CMP processes Sharad Prasad a'*, W. Loh a, A. Kapoor a, E. Chang b, B. Stine b, D. Boning b, J. Chung b aLSI Logic Corp, 1635 McCarthy Blvd., Milpitas, CA 95035, USA bMIT EECS, Cambridge, MA 02139, USA Abstract CMP processes are used to planarize layers; however, variations in ILD thickness due to various layout factors can affect the modelling of interconnect parameters. In this paper an overview of 'Statistical Metrology' for CMP processes is presented. Using statistical metrology for CMP the process or interconnect design rules can be optimized for minimal variations.
1. Introduction Future VLSI scaling will critically depend upon the ability to fully model key interconnect processes and limit the interconnect parameter variations. Oxide CMP improves planarization but remains hampered by systematic and random sources of (InterLayer Dielectric) ILD thickness variation at the lot, wafer, die and pattern levels. As the critical dimensions shrink it is important to limit the interconnect parameter variations. Lot-to-lot variations (Fig. 1) can be caused by drifts in equipment or shifts in equipment parameters. Within a lot the variations could be caused by non-uniform processing or equipment variations in a single batch process will give rise to statistical distribution within a lot. Wafer-to-wafer and lot-to-lot variations have received significant attention and can be managed by controlling process parameters and equipment. However, die-to-die variations and variations of ILD thickness within a die are becoming increasingly important. The intradie variation is often larger than the variation within the wafer and can also be larger than the lot-to-lot or wafer-to-wafer variations. This means that the same structure at the same location within different dies would vary much less than structures within the same die.
2. Statistical metrology 2.1. Measurement of variations Statistical metrology is a methodology to assess variations and assess the impact of those variations. :g
Corresponding author. Fax: (1-408) 954-3458; e-mail: [email protected]
0167-9317/97/$17.00 Copyright 01997 Elsevier Science B.V. All rights reserved PII S0 1 6 7 - 9 3 1 7 ( 9 6 ) 0 0 0 5 2 - 4
232
S. Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
°.*"
-- [
/L %
llr~liltl~ally
SimUl.,/
hmld
Wdldlon
I~mr
Fig. 1. Sources of variations. Process:Oxide Polishing Oxlcle
Before PlanarizatJon
Met~
After Planerization
Test Structure ,late
I
:tor ._, _ _ .
dous J~ctom
(w! various layout faotors)
Fig. 2. (a) Detecting interconnect variation. (b) Test structures with possible variations.
S. Prasad et al. I Microelectronic Engineering 33 (1997) 231-240
233
Variations can be assessed by measuring the parameter and understanding the process and device variations in that parameter as well as the spatial and feature dependencies. This requires a large number of measurements in order to separate the confounding sources of variations. In the case of CMP the ILD thickness can be extracted from the electrical measurements of metal-to-metal to capacitors (Fig. 2). The test capacitors have a uniform top plate and a bottom layer consisting of a ladder structure with various combinations of layout factors including finger width, spacing, orientation, finger length and number of fingers [1,2]. For accurate measurement of the capacitance the exact physical parameters of the capacitor should be known. Van der Pauw and Kelvin structures are used to de-couple linewidth and thickness variations [1] (Fig. 3). To measure the ILD variations a short loop experiment is run. On unstructured wafers a PECVD TEOS layer is deposited. Metal 1 is then deposited and structured. An ILD layer is deposited and then planarized by CMP to reach the target ILD thickness. Via holes are etched in the ILD and tungsten vias defined. Metal 2 is deposited and structured and then the chip is passivated. Using automated measurement techniques and 2-D capacitance simulation the ILD thickness can be extracted from the
II
Fig. 3. Probe and chip layout.
234
S. Prasad et al. / Microelectronic Engineering 33 (1997) 2 3 1 - 2 4 0
Capacitance vs. ILD Thickness Q 0 ~
+ X__
\~ ~il~!!~=,
o
width width width width width
= 5.4 = 5.2 = 5.0 = 4.8 - 4.6
um um um um um
\ \'~%~ x+~oo
~x+Aoa ~x~.A,o, o, ~x +.A.°,a" -x+A.°.~-o. "x+.A..oa. -x +& a
x.+..Ao,O, a
x.+.,-~o., o x..+A.O.o.a x"x .+ -.'AO.o'O. A . o
x x-x:*.~:=.~.g:a.°. -+8.-oa.
x-x.*.,:A,~.o.=,o x.x.~ +:~ ~:~.~:~.°..
X-x.~-.:~.Z:?-~:R....
.X.x,+.¢.&...,.
012
0'.3
014
0'.5 ILD thickness (um)
0'.6
0'.7
Fig. 4. Extracting ILD thickness from capacitance measurements. capacitance and linewidth measurements [1] (Fig. 4). Fig. 5 shows the raw dielectric thickness obtained on a single wafer. These variations need to be decomposed to understand the cause of variation.
2.2. Variation decomposition In Fig. 6 an overview of variation decomposition is illustrated. The ILD thickness variation can be assumed to be a sum of wafer-level, die-level and some die-wafer interaction variations [2]. Wafer-level variations are low frequency and smooth (Fig. 7) and these variations can be extracted using a moving average estimator. Wafer-level variations are independent of die patterns. Die-level variations are pattern dependent and layout dependent. Die-level variations are identical from die to die. These variations can be extracted using a 2-D Fourier analysis [2,3] (Fig. 8). Clearly, layout factors like variation of finger width length etc. influence the die level ILD thickness variation. Die-wafer interactions are dependent upon the die and its position on the wafer. Finally, the remaining variations are residuals (Fig. 9).
3. C M P study Using the short loop test a screening experiment is carried out. A half-fractional factorial design of experiments with six layout factors was carried out. This gave 33 structures which were randomly
S, Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
235
(a)
,3
J
Ji
:! |
:.
•
[ 2O
10
(lie n u t t i e r
...':'....
(b)
."
. ' . -..
"
a
_J 60
60
0
Y
X Fig. 5. (a) Raw interconnect dielectric thickness data. (b) Thickness variations across wafer•
236
S. Prasad et al. / Microelectronic Engineering 33 (1997) 2 3 1 - 2 4 0
:iii:i~,~:!i!l I
vL,Ln'In waf,,-o •
,.l~.'r~~ t . ' .~.'] 1
n~'U~len
t>
Total Rulduafs
Fig. 6. Variation decomposition overview.
distributed on the die. This initial experiment showed die-level variations as seen in Fig. 8 [1,2], and identified what factors are important. In particular, the die-level variation is due to layout features and neighborhood distances within the die [1]. A second set of experiments which mimics ASIC-like design was done. This chip is a full factorial design of five factors (linewidth and spacing, finger length, number of fingers and the geometrical orientation) in combination with four levels of interaction distance, yielding 129 unique structures (including several center-point structures). Additionally, test structures with and without dummy fill are also included to study the effect of dummy lines on ILD thickness (Fig. 10).
Wafer 21 - - Wafer Level Variation
''i'" .!
:
:...
:
:
.
I
...
' I
60
I-,.
60
Fig. 7. Wafer-scale dielectric thickness variations.
S. Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
237
4o 15 1
~
20
0 0 Fig. 8. Variation source: Die level.
Wafer Levd_..~.. o.s Variations
o.4 50
0 0 +
Raw Data
0.40"5 .
~
! 50
o o Die Level
o.~i
Die-Wafer .............~-0.1 Interaction
Residuals
50
~
0 0
50 +
0.1 o
-0.1
50
Fig. 9. Pattern variation sources.
0 0
50
238
S. Prasad et al. / Microelectronic Engineering 33 (1997) 2 3 1 - 2 4 0
/ Run .by Run Variation
Within Wafer Variation Variation
Process Control S ategy ¥
Optimize process to minimize layout dependence: .................... :...............:-..............~.... I~ilil 2
",.i
'..i
1 1000~'--"~'----~400 6OO
2(X)
0
-zt~
"-40
Fig. 10. Metrology to optimize process.
4. Impact Using statistical metrology techniques
(a) the CMP process could be optimized; (b) interconnect design rules could be modified. The CMP process could be characterized, controlled and optimized for manufacturing. The process could be optimized so that die-level variations are minimal due to layout factors (Fig. 10). The process could be optimized so that, depending upon a product for a given range of layout factors, the die-level and wafer-level variations are within product specifications (Fig. 1 l). Finally, where the layout factors cannot be pre-determined in an ASIC-like environment a dummy fill approach could be used. The interconnect design rules could be determined such that the layout density range is within a very tight region where the ILD thickness variation is very small (Fig. 12). This would ensure very tight regulation of interconnect device parameters such as interconnect capacitance, and crosstalk between interconnect lines.
S. Prasad
Y
et al. I Microelectronic
Engineering
33 (1997)
231-240
Vary density, circuit block separation More dense
Less dense
Fig. I I. CMP Metrology
..,.“i
. . ;:+..f,
for interconnect
..
. j#
.J_. .. .Ii .. :.i,....,,...I ,,,...._.i .
..
design rules.
j ..,,..... f .,...._,, f . .
. .. i .. . ... i
.
.. i . .. j.. ..__.. i..,....., j ,.....,.. 4 .._...,
..
j
j
j
1
1
!
4 . ... t . . . i .. I
:
I
:
j ..
!
I 4
I 1 . . .
t
. . y
.
..I.
I!
,....,. I_;. ... .j .. . .i .. 7I . .. tI . ... ii.. . i’! ... ..&.... I: I i rj - ! Ij i ; ! ’ $ .‘a O!. &, .: 0: A :* a% 0.1 ti Corfventional Layout Density Range Fig. 12. Interconnect
dielectric
thickness
relationship
to density.
239
240
S. Prasad et al. / Microelectronic Engineering 33 (1997) 231-240
References [1] E. Chang et al., IEDM Tech. Digest (1995). [2] R. Divecha et al., Proc. 1st IEEE Int. Workshop on Statistical Metrology, June 1996. [3] B. Stine et al., VMIC (1996).