Status and challenges of phase change memory modeling

Solid-State Electronics 52 (2008) 1443–1451

Contents lists available at ScienceDirect

Solid-State Electronics journal homepage: www.elsevier.com/locate/sse

Status and challenges of phase change memory modeling A.L. Lacaita 1,*, D. Ielmini, D. Mantegazza Dipartimento di Elettronica e Informazione, Politecnico di Milano, piazza L. da Vinci 32, Milano and IU.NET, Italy

a r t i c l e

i n f o

Article history: Available online 19 May 2008 The review of this paper was arranged by Jurriaan Schmitz

a b s t r a c t Phase change memory (PCM) is the most performing non-volatile memory-technology alternative to FLASH. In order to design optimized cells, in term of geometry and materials, for present and future technological nodes, physics-based models for readout, programming and data retention are required. In this work, transport and phase-change modeling in PCM cell is reviewed and used to discuss (1) the programming-current reduction through geometry optimization, (2) the trade-off between programming current and readout resistance and (3) the program disturb phenomenon. In particular, scaling of PCM is extensively investigated, comparing the impact of isotropic and non-isotropic scaling on cell programmingcurrent and program-disturb. Recent developments and open issues in PCM physical modeling are finally presented. Ó 2008 Elsevier Ltd. All rights reserved.

1. Introduction Phase change memory is today considered one of the most promising candidates for next generation non-volatile memories. In fact, compared to FLASH and other emerging technologies, PCM presents good scalability, improved performances and low-cost CMOS-process compatibility [1,2]. Its functionality is based on the reversible crystalline-amorphous phase-change, induced by Joule heating in a phase-change material, typically a chalcogenide, and on the two different electrical resistances associated to the two phases [3]. The cell state is determined applying a low bias to the cell and sensing the corresponding current. Crystalline phase (SET state) has low resistance (few kX) while amorphous phase (RESET state) an high resistance (few MX). Specifically referring to the 90 nm lTrench architecture employing Ge2Sb2Te5 [4], PCM offers low voltage (maximum programming voltage: 1.4 V), fast programming (SET in about an hundred of nanoseconds and RESET in few tens of nanoseconds), long data-retention and cycling life (respectively >10 years at 85 °C and >108), single bit granularity and few additional masks in a standard CMOS process. Due to the high scalability of the phase-change material [5] and of the cell diode selector [6], PCM technology is expected to be scalable beyond the 25 nm node, whereas NOR and NAND FLASH will face serious scaling issues respectively beyond the 45 nm and 25 nm node [6]. Despite these attractive features of PCM technology, several critical issues remain, in particular concerning the scaling limitations and the cell-array reliability. The PCM scaling challenge regards the programming current reduction, since scaled selector * Corresponding author. E-mail address: [email protected] (A.L. Lacaita). 1 Also with IFN-CNR, Milano, Italy. 0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2008.04.020

limits the maximum deliverable current to be used in the programming operation. In fact, for PCM to compete with NAND FLASH, the cell area must be smaller then 4F2. A diode of this cell size in the 25 nm node requires the RESET current of the memory element to be less than 150 lA [6], while at the present the programming current of industrial test-chip demonstrators [4,7–9], up to the 90 nm technological node, is in the several hundreds of lA range. As a consequence, to assess the scalability of the memory technology, several approaches for reducing the programming current have been proposed, including material and cell engineering [10– 16]. On the other hand, some single-cell and array reliability issues must be fully addressed to validate PCM technology for several generations. In particular the effect of the program-disturb in the memory array for small pitch between adjacent cells and the data-retention capabilities at single-cell and array level must be investigated. A rigorous and accurate physics-based modeling of the cell and array behavior during reading, programming, and data retention is thus mandatory, in order to explain experimental data for actual PCM samples, to find out the optimum geometry and to make predictions for scaled technologies. 2. Cell operation and structure Phase change memory is a two-terminal, programmable resistance structure constituted by a phase-change compound, generally a chalcogenide. The crystalline-amorphous phase transition (RESET) is determined through a current pulse, that heats above the melting temperature Tm and fast cools the active material. The fast cooling (quenching) time avoids spontaneous crystallization and corresponds to the falling edge duration of the programming pulse. Higher temperatures (higher currents) increase the programmed amorphous volume. The amorphous cell below the

1444

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451

melting temperature Tm, at working conditions in a long-time range, sustains spontaneous crystallization, limiting the device non-volatility and thus constituting a data-retention issue. The amorphous-crystalline phase transition is instead induced either through a constant current pulse below melting (higher currents and longer pulse increases the crystallization rate) or melting the material and cooling it slowly (quenching time of several hundreds of nanoseconds) in order to permit crystallization. This last programming is generally more efficient, in particular at array-level, since during the sweep, for all the array cells, all portions of the programmable active volume are subjected to an optimal crystallization temperature for an optimal duration. In order to maximize the heating efficiency, in particular in the RESET operation, which requires higher programming current, the power dissipated in the chalcogenide must be maximized and the heat flow from the active material minimized. This is achieved basically through a semi-metallic (TiN [11] or Tungsten [15]) bottom-electrode pillar (heater), placed below the phase-change layer, with small contact area. This causes high bottom-electrode electrical and thermal resistances, which respectively permits high power dissipation and low heat loss. This overall structure (chalcogenide layer and heater electrode) is called vertical-resistive-electrode-planar cell or lance cell and it is reported in Fig. 1, through a 2D schematic drawing. The phase-change layer and the electrode are embedded in a dielectric environment, to further reduce the dispersion of heat flow. The programming current is provided and collected respectively by a top-electrode contact, which can be a line-metal, and a bottom-electrode which generally links the cell to the selection device or to the ground. The programmable volume (crystalline to amorphous and vice-versa) is at the interface, where the maximum temperature variation occurs. During the RESET operation, in order to achieve an effective changing in the read resistance (i.e., from low to high) the amorphous phase must be extended over the whole bottom contact, thus determining a continuous high-resistive layer opposing to the current flow. Alternative architectures to the lance permit to achieve smaller contact area and thus programming current at the same technological node. One of the most effective solutions, in term of programming current and process robustness, is the lTrench [4,17] architecture, developed by ST Microelectronics. Its 3D schematic drawing and top-view are reported in Fig. 2, while its vertical section in Fig. 3. The contact area between the heater and the active material is defined by the intersection of a thin vertical semimetallic heater and a trench (lTrench), in which the active material is deposited. Since the lTrench is defined by sub-litho etching techniques and the heater thickness by conformal film deposition, small contact area can be obtained (400 nm2 instead of 3000 nm2 for the lance, with F = 90 nm). Furthermore the lTrench structure permits to keep the programming current low maintaining a compact vertical integration and a good area CD. At F = 90 nm [4] the lance and the lTrench architectures permit to achieve RESET current (RRESET1 MX) of 700 and 400 lA respectively.

Fig. 1. Reference lance PCM cell. c-Ch and a-Ch respectively stands for crystalline and amorphous chalcogenide.

Y

Top Electrode X c-Ch Heater

Y

Plug

X Fig. 2. lTrench architecture. 3D schematic drawing (left) and floor plan (right). Typically the y-axis represents the bit-line direction, while the x-axis the word-line direction.

Dielectric

Ti-TiN GST

Protection

Z Heater

Y

Pre/contact

X Fig. 3. lTrench architecture. Vertical section.

As regard the active material investigation, a phase-change material suitable for electrical non-volatile memories should ideally [18]: (1) be able to be programmed at relative low temperature (i.e., low programming current), (2) possess fast phase-transition, have good reading window between the programmed states (high resistive contrast), (3) guarantee long data retention (stable amorphous phase, high activation energy), (4) be time-stable (low drift resistance) and, lastly, (5) be scalable. Phase-change materials employed in electrical memories generally belong to the Ge:Sb:Te ternary system, in particular to the GeTe–Sb2Te3 pseudo-binary line. The most performing compound is the Ge2Sb2Te5 (GST). Still referring to programming current optimization, nitrogen and oxygen doped Ge2Sb2Te5 [11,12] have higher electrical resistivity than the un-doped Ge2Sb2Te5, respectively due to smaller grain size and higher defects density. The higher resistivity increases the power dissipation and the heat confinement. Ge-doped SbTe material [18] also leads to low programming current due to its relatively low melting temperature (540 °C instead of 630 °C of Ge2Sb2Te5). 3. Modeling of readout and programming To address the PCM cell performances, in particular, the current reduction issue, a numerical model able to describe self-consistently (1) the electro-thermal physics and (2) the crystalline-amorphous phase-change of a PCM cell with an arbitrary 3D geometry is required. In particular, the model must account for the cell readout, programming and data retention. This review discussion specifically refers to the numerical model implemented in a standard semiconductor device simulator (Synopsis-ISE-TCAD) for the lance structure and published in [19]. In particular a 3D cylindrical geometry was assumed. The model was calibrated, as regard geometrical and physical parameters, through experimental data provided by a lance structure implemented by ST Microelectronics at 180 nm node [17], employing Ge2Sb2Te5 as active-material. According with (1) the rock-salt structure of the crystalline Ge2Sb2Te5 with 15% of acceptor like atomic vacancies [20], (2)

1445

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451

the optical absorption measurement that reveals an energy gap of 0.5 eV [21] and (3) the very small activation energy of the electrical conductivity [22], the Fermi statistics and a p-type state-density, as reported in Fig. 4 (top), were assumed in the numerical model for the crystalline GST. Considering the short-range order of the amorphous phase and previous studies on selenium based chalcogenide, the amorphous Ge2Sb2Te5 density of states is assumed characterized (Fig. 4, bottom) by a sub-band of localized states just above the valence band due to weak and strained bonds of the amorphous phase and by donor and acceptor like traps, caused by charged over and under coordinated atoms, which pinned the Fermi level at the midgap [23]. This picture is supported by absorption measurements [21] and by the activation energy value of the electrical conductivity [22], almost equal to half of the mobility band-gap. Since hole traps density is higher, a p-type conduction is assumed [23]. A band conduction transport (drift-diffusion) is adopted in both the c-GST and in the a-GST. In the latter a proper value of hole mobility is assumed (smaller than usual) in order to account for both the high-mobility band and low-mobility hopping conduction [21]. Charge and heat conservation equations and Poisson equation (both in steady-state and transient condition) were then self-consistently solved, thus constituting the physical framework of our numerical model. In the model charge carriers are considered in equilibrium with the lattice and Seebeck/Peltier effects are neglected. The electrical parameters values, thus carriers mobility and states densities of the GST (in the bands and in the band-gap) and of the heater material (modeled as a semiconductor), were calibrated in order to account for low field (voltage lower than 1.2 V) crystalline and amorphous I–V current voltage characteristic and in accordance with experimental data [21]. Measured and calculated I–V are reported in Fig. 5. The amorphous RESET curve displays for increasing bias first an ohmic behavior, then an exponential and super-exponential behavior. At the critical voltage VTH (1.2 V in Fig. 5) the cell conductivity increases (higher currents at lower voltages). Assuming an Impact Ionization mechanism, where the

E

CB

Ec

Acceptor-like localized states

Ef Ev

Fig. 5. Measured and calculated I–V characteristics for a cell in the SET and RESET state, corresponding to the crystalline or amorphous phase in the programmable volume.

generation rate both depends on the electrical field and on the carrier concentration, and a SHR recombination mechanism, the model can account for the experimental data, also in the electronic switching region, which is not reported in Fig 5 [21]. The ohmic resistance RRESET depends on the equilibrium amorphous carrier concentration and mobility. The crystalline SET curve displays a linear behavior below 0.2 V, characterized by the resistance RSET which is lower then RRESET by at least two order of magnitudes, and for higher voltages the active material conductivity significantly increases, due to the increase of temperature (Joule heating) and the consequently increase of thermal generated carriers. The SET I–V curve thus saturates to the bottom electrode characteristic, featuring a RON resistance (Fig. 5). In order to determine the thermal parameters, the melting current (i.e., the programming current that melts all the programmable volume) is extracted from experimental SET and RESET programming characteristic (see Fig. 6), that respectively provided the cell resistance (y-axis) obtained applying a programming current (x-axis) to a crystalline or amorphous cell. Referring to the SET characteristic, the melting current corresponds to the maximum programming current that avoids cell resistance increase. In fact programming current higher then the melting current applied to a crystalline cell leads to the formation of the amorphous volume and, consequently, to a resistance value increase. The extracted melting current (500 lA) and the published GST melting temperature (680 °C) permit to calibrate the thermal model. Refer-

7

VB

10

Reset-set transition

E

R [Ω]

Donor-like Traps

Ec

Set-reset transition

6

10

CB

5

10

Ef 4

Ev

Acceptor-like Traps

10

Melting 3

10

VB Fig. 4. Schematic for the states density assumed in the chalcogenide semiconductor, for the crystalline (top) and the amorphous phase (bottom).

0

200

400

600

800

1000

IP [μA] Fig. 6. SET and RESET programming characteristic for a reference 180 nm cell.

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451

0.0

0.5

1.0

1.5

2.0

2.5

0.0008

10

0.0007

Current [A]

Im

0.0005

1000

0.0004 800 0.0003

Temperature [K]

1200

0.0006

600

0.0002 0.0001

10

-2

Nucleation

-4

10

10

-6

10

-8

10

40

Vm

0

Growth

1400

Probability density [ns-1]

1446

-10

100

200

300

0.0

0.5

1.0

1.5

2.0

2.5

Voltage [V]

ring to Fig. 7 and assuming the same thermal parameters for the melted and the crystalline GST in accordance with [24], the crystalline GST and heater thermal parameters are chosen in order to obtain in the simulator a current–voltage and temperature–voltage cell characteristics in accordance with measured melting current and temperature. In Fig. 7 the temperature is calculated at the GST-heater contact area. Note that the top and bottom electrode (see Fig. 1) temperature is fixed at the room temperature. As already mentioned in PCM functionality the crystallineamorphous transition is the most critical, since it requires the largest programming current. While the melting temperature is a material physical constant, the melting current and voltage (Fig. 7) represent figures of merit for a particular architecture and scaling approach. It will thus be extensively used in the following. 4. Modeling of phase-change To account for the cell phase-change and thus for the programming characteristic in Fig. 6, the above discussed electro-thermal model must be self-consistently coupled with a phase-change model. To address crystallization both in a SET programming (programming current lower then Im in Fig. 8) and in an isothermal work-condition below Tm, the standard theory of kinetics is adopted [24] and the GST nucleation and growth (N/G) rates are required. We used the nucleation and growth probability published

10

10

Data

10

700

10

100 ºC 10 years

10

8

10

6

10

4

10

2

10

0

110 ºC

120 ºC

5

Time [s]

Resistance [Ω]

10

600

in [24] and reported in Fig. 9 (the growth probability is not a physical parameter: it depends on the growth velocity and spatial/time mesh size). Through (1) the thermal profile in the active material provided by the electro-thermal simulator (that is non-uniform and time-varying in the SET programming and constant during and isothermal annealing experiment), (2) the temperature dependent N/G crystallization probabilities and (3) a random-number generator (Monte Carlo approach), the cell programming characteristic was simulated in accordance with experimental data (Fig. 8, I < Im). Assuming sufficiently fast cell quenching during the programming operation, local amorphization in the GST occurs when the temperature is higher than Tm. This permits to calculate the RESET programming characteristic in Fig. 8 for current higher than Im. In fact once the electro-thermal model provides the temperature profile in the GST, local GST amorphization occurs where the local temperature T is higher than Tm, while the crystallization model is locally adopted where T < Tm. Furthermore, considering a cell in the RESET state, performing an isothermal annealing and choosing a resistance crystallization threshold, the Arrhenius plot of data-retention times [19] can be calculated (Fig. 10). The coupled model thus permits to calculate programming characteristics and data-retention times in accordance with measurements and thus to make reliable predictions for different architectures and technological nodes. As an example, Fig. 11 show experimental and calculated SET programming characteristic for both the 180 nm lance and lTrench architecture. The different programming current and SET resistance will be discussed in the following. Finally, since the developed model correctly reproduces both programming and data-retention

Calculated

10

500

Fig. 9. Nucleation and growth probability density used for the RESET-Set transition in the phase-change model [24].

Fig. 7. Measured and calculated I–V characteristics for a SET-state cell, and calculated maximum temperature at the interface between chalcogenide and heater material, as a function of the applied voltage.

6

400

Temperature [°C]

0.0000

4

160 ºC

140 ºC

180 ºC Data Calculated 200 ºC

3

0

100

200

300

400

500

600

700

800

Programming current [μA] Fig. 8. Measured and calculated programming characteristic for the RESET-SET transition.

24

26

28

30

32

1/kT [eV-1] Fig. 10. Arrhenius plot for measured and calculated retention times.

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451

10

7

lance μ-trench

Resistance [Ω]

10

10

10

6

5

4

Rset Im

3

10 0

200

400

600

800

1000

1200

Current [μA] Fig. 11. 180 nm lance and lTrench SET programming characteristics. Both measured and calculated data are reported.

behavior, the adopted crystallization kinetics [24] both for short and for long times is confirmed. 5. Optimization of cell geometry The optimized cell geometry minimizes the programming current, thus the melting current Im, or, equivalently, maximizes the generated temperature through Joule heating, once the technological node and the SET resistance are fixed. The technological node, through either lithographic or sub-lithographic techniques determines the contact area dimension, while the SET resistance the reading window and thus the array programming reliability. Then fixing the read voltage VREAD and assuming a bit-line charging sensing scheme, larger SET resistances increase the overall read-time. Ideally the programming current reduction must thus not increase the SET resistance. Referring to the lance structure, the optimized geometry is thus determined minimizing Im considering as free geometrical parameters the height of the bottom electrode Lh and of the active material layer Lc for a fixed bottom electrode diameter U and SET resistance RSET [25]. The same procedure can be used for the lTrench, pore [8] and ring [9] architectures. Referring to Fig. 7 the melting current is, for each cell geometry (Lh and LC fixed), the applied programming current which determines at the interface the GST melting temperature (680 °C). The interface temperature is calculated through the discussed numerical model. Maintaining the same bottom electrode diameter (U = 55 nm, at F = 90 nm) and the same RSET (Lh + Lc is constant), different Lh/Lc ratios modulates the temperature profile, as Fig. 12 shows. The temperature peaks shifts from the chalcogenide layer to the heater electrode increasing the Lh/Lc ratio. The optimum geometry permits to achieve for a fixed programming current the highest temperature at the interface or, equivalently, the lowest melting current.

Fig. 12. Calculated temperature profiles for different lance cell geometries, all having in common the heater diameter / and the set resistance Rset. The optimum geometry ensuring minimum programming current is shown (b).

1447

Providing more generality, the same approach is used assuming U = 30 nm, varying bot the Lh/Lc ratio and the RSET value. Fig. 13 provides the calculated melting current Im, that is the programming current which leads to the Tm at the interface. For each RSET, due to the ‘‘U-shape” Im – Lh function, an optimum ratio exists, which correspond to the minimum melting current. As already mentioned, considering the thermal profiles in Fig. 12, the minimum melting current corresponds to the geometry where the temperature peak is places at the chalcogenide layer–heater interface. In this situation, the electrical and thermal resistances of the bottom electrode and of the chalcogenide layer are almost comparable to each other, so that the temperature maximum is located at the bottom contact interface. Furthermore, from Fig. 13, increasing the overall SET resistance (in this case, since U is fixed, changing the material) lower melting currents are achieved as expected, since the power dissipation increases. 6. Scaling of PCM cell Besides the above discussed cell geometry optimization, where the optimum Lh/Lc ratio is determined for a given technological node and RSET, other solutions can lead to a programming current reduction, such as the recess contact (pore architecture), the minimization of the bottom contact area by sub-lithographic techniques and the material optimization. In particular, the recessed architecture results in (1) higher current concentration, (2) decrease of effective transition volume and (3) confinement of the transition volume far from the damaged cell edge. On the other hand, the contact area reduction and the heater and phase-change material optimization increase electrical and thermal resistances. This leads to an higher Joule heating and thermal confinement. As the cell scales, following the lithographic node F, the programming current decreases. Two scaling approach can be adopted: an isotropic scaling, where all geometrical features in the cell are reduced by the same factor, and non-isotropic, where only the lateral features (e.g., bottom electrode diameter in the reference lance cell) are reduced by the scaling factor, while the vertical size of the electrode and the chalcogenide layer are constant [26]. On the other hand cell scaling has two critical consequences: it increases the SET resistance and reduces the cell-cell pitch in the PCM array. This could lead to an increase of inter-cell thermal disturb effect during programming. Both these phenomena may have an impact on cell performance/reliability and have to be carefully evaluated for best engineering of the cell in the next scaling nodes. Assuming the lance architecture and the relation U = 0.65 F, according with [4,17], Table 1 shows the cell sizes for different

Fig. 13. Calculated Im as a function of the heater length Lh, for increasing Rset and for a fixed heater diameter / = 30 nm.

1448

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451

Im ¼ ðDT m =ðaRTH RON ÞÞ1=2 ;

Table 1 Geometrical features of PCM cell assumed in the numerical simulations F (nm)

Size of PCM cell

90 65 45 32 22 16

/ (nm)

Lc (nm)

Lh (nm)

56 40 28 20 14 12

70 51 35 25 17 12

180 130 90 64 44 32

technological nodes in case of isotropic scaling (both U and Lc + Lh are reduced) and an optimum cell geometry (Lh/Lc ratio which guarantees the minimum melting current Im), according with the previous discussion. In case of non-isotropic scaling Lc and Lh values, calculated with F = 90 nm, are maintained for all the technological nodes. The optima melting currents are reported in Fig. 14a for both the isotropic and non-isotropic scaling approach. The calculated series of the electrical heater and high-field GST resistance (RON), for different technological nodes, are reported in Fig. 14b. The GST layer contribute to RON is almost negligible due to the GST high conductivity at high field. The temperature increase, respect the external reference temperature, at the chalcogenide-heater interface, induced by Joule heating, can be approximated by the formula: DT ¼ aRTH P D

ð1Þ

where a accounts for heat inefficiency, RTH is the equivalent cell total thermal resistance from the hot spot (the position of maximum temperature located close to the bottom contact) to the top and bottom thermal contacts of the cell, determined by the heater and chalcogenide layer thermal resistances RTH-c and RTH-h (RTH = RTHc//RTH-h) and PD is the power dissipated in the device which is approximately PD = RON  I2, where I is the programming current. The melting current is thus:

3

10

Im [μA]

a

ð2Þ

where DTm is fixed and depends on the active-material physical properties. The impact of F variation, for the isotropic and non-isotropic scaling approach, on RTH and RON must be address to qualitatively explain the simulation results in Fig. 14. First in the RTH the RTH-h can be neglected since its value is relatively large in the discussed lance architecture. For isotropic scaling both RTH and RON increases for decreasing F namely as RTH 1 F-1 and RON 1 F–1. Substituting these functional behaviors in Eq. (2) we find Im 1 F, in accordance with simulations results. For non-isotropic scaling RON 1 F–2, in accordance with simulation results in Fig. 14b, since in this case only the electrode diameter is scaling, while the length is kept constant. Considering the independence of RTH from the heater resistance and the spreading of heat conduction from the small bottom contact to the large top contact, RTH 1 F–1. So, in case of non-isotropic scaling Im 1 F1.5. Simulation results in Fig. 14a can instead be accounted by the relation Im 1 F1.3. In fact, more detailed simulation analyses show that RTH 1 F–0.7, as a result of parallel heat conduction through the non ideal thermal insulating materials surrounding the bottom electrode. 7. Scaling discussion The non-isotropic scaling permits to achieve the smallest programming current at fixed technological node, as the simulation results in Fig. 14a and the previous simplified discussion prove. At the same time three disadvantages for the overall performances of the cell occur. The high aspect ratio Lh/U of the non-isotropic scaling is technological difficult to be fabricated and controlled. In particular, the process step of depositing the heater material to realize a high-aspect ratio lance-shape electrode become increasingly difficult with the scaling. Then non-isotropic scaling leads to higher SET resistance RSET, in accordance with RON (Fig. 14b). As already mentioned, high read resistance should be basically avoid in order to maximize the read current IREAD and consequently the cell sensing capabilities between the SET and the RESET state. A slower enhancement of RSET as in the isotropic scaling case is thus to be preferred from this standpoint. The trade-off between programming and read current can be better addressed through Fig. 15. For each technological node, still assuming U = 0.65 F, the minimum melting current associated with the optimum geometry and the corresponding SET resistance are reported, both in case of isotropic scaling and in case of non-isotropic scaling. The slopes of the Im – RSET function in Fig. 15 can be ex-

2

10

3

1

10

2

10

10

F=90nm

F [nm]

b

90nm

65nm 45nm

5

Ron [Ω]

Im [μA]

10

32nm 2

22nm

10

16nm

32nm

4

16nm

10

Isotropic scaling Non-isotropic scaling ITRS 2006

isotropic non-isotropic 1

3

10

1

2

10

10

F [nm] Fig. 14. Calculated Im (a) and Ron (b), as a function of F for isotropic and nonisotropic scaling. Symbols are experimental data from [4].

10 3 10

4

10

5

10

Rset [Ω] Fig. 15. Calculated Im as a function of Rset, for isotropic and non-isotropic scaling in a lance cell. Also shown are values reported in the ITRS 2006 Update [27].

1449

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451

Im / F / R1 SET

ð3Þ

for isotropic, and Im / F 1:3 / ðRSET Þ1:3 ¼ R0:65 SET 1=2

ð4Þ

for non-isotropic scaling. The product g = Im  RSET, assumed as a technology figure of merit, must be minimized, in order to improve both programming and reading performances. According with results plotted in Fig. 15, isotropic scaling is thus preferable in PCM technology. Fig. 15 also provides Im and RSET values reported in the International Technology Roadmap for Semiconductors for PCM scaling [27], from F = 90 to 32 nm. The values shown are lower than the corresponding results from our simulations, for both the programming current and the SET resistance. This can be explained by the different electrode diameter assumed (e.g., U = 32 nm in [27] as compared to U = 56 nm in our work for F = 90 nm) and assuming different material properties (e.g., electrical and thermal resistivities). 8. Program disturb and mixed scaling approach The cell RESET operation impacts on neighboring cells (program disturb) is a PCM-array reliability issue, due to the high programming temperature and the close inter-cell pitch. This is shown through the simulator results in Fig. 16: when a programming pulse is applied to a cell in the array (Fig. 16, left), heat conduction and spreading from the programmed-cell volume results in a temperature increase also in the neighboring cell (Fig. 16, right). In particular, an increase in the temperature of an amorphous cell leads either to a traps number variation [28,29], corresponding to a cell resistance increase, or to the chalcogenide crystallization, corresponding to a cell resistance decrease, depending on the temperature value and the disturb time-duration. These phenomena are respectively critical for multi-level-cell and data-retention. Further more scaling can enhance the temperature disturb due to the intercell pitch reduction. The discussed numerical model for the reading and programming operation permits to address the program disturb phenomenon, in term of effective temperature increase, for different architectures, technological nodes and scaling approaches (isotropic or non-isotropic). In particular, we performed numerical simulations to calculate the maximum temperature T2 in correspondence of the first-nearest neighbor disturbed bit (see Fig. 16) during a 50 ns-long RESET pulse applied to the programmed bit. T2 is the temperature at the edge of the RESET amorphous volume, at the contact between the chalcogenide layer and the below

dielectric (Fig. 16). The calculated T2 temperature for isotropic and non-isotropic scaling and from 90 to 16 nm technological node are collected in Fig. 17. In case of isotropic scaling T2 temperature is constant at different technological nodes F, while non-isotropic scaling increases T2 values for lower F. This effect can be explained through the 2D equivalent thermal network model of the programmed and the neighbor cell of Fig. 18. Assuming the programming current Im and the corresponding temperature increase DTm in the programmed cell, through the schematic in Fig. 18, the approximated temperature rise in adjacent cell DT2 is: DT 2 ¼ DT m R2 =ðR12 þ R2 Þ

ð5Þ

where, according with Fig. 18, R2 and R12 are respectively the parallel between thermal resistances Rh2 and Rc2 and the thermal resistance from the programmed to the disturbed bit. For isotropic scaling, all the thermal resistances in Fig. 18 increase similarly, according with R 1 F–1, thus R2/R12 and DT2 are constant. For nonisotropic scaling, Rc2 and Rh2 decrease with F, according with R / F-2, since Lh and Lc are constant, while the contact area decreases. On the other hand, at first order, R12 decreases, since the inter cell pitch is reduced. This, according with relation (5) is the basis of DT2 increase in Fig. 17. To quantify the disturb temperature Tdist, that is the maximum temperature T2 that avoids cell crystallization, we assume, as worst case, to apply 109 RESET pulses to an array cell. Each RESET pulse is 50 ns long. Consequently the overall disturb time tdist is tdist = 50 s. Accordingly with the previously presented data-retention results (Fig. 10), in particular extrapolating a cell activation energy EA = 2.8 eV and considering measured data-retention times, Tdist corresponding to tdist = 50 s can be calculated Tdist = 470 K (see Fig. 10 at Time = 50 s). From simulation results in Fig. 17, calculated according with sizes in Table 1, non-isotropic

1000 900 800 Isotropic

T2 [K]

plained considering that RSET 1 F–1 for isotropic and RSET 1 F–2 for non-isotropic scaling. In fact, also considering the previous relation between Im and F:

700

Non-isotropic

600

Mixed

500

Tdist

400 300 10

100

F [nm] Fig. 17. Calculated maximum temperature in the disturbed bit T2, for isotropic, non-isotropic and mixed scaling approaches.

Chalcogenide

RC1

R12

RC2

Insulator

RH2

Heater

RH1

Fig. 16. Calculated temperature profile in a 2-cell block within a PCM array. While one cell is being programmed, the temperature increases also in the neighbouring cell, raising a reliability concern.

Fig. 18. Schematic for the thermal resistance network of the programmed/disturbed cell blocks. Thermal coupling resistance R12 controls the program disturb behavior in the array.

1450

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451

The programming characteristics and the data-retention times can be calculated thus permitting predictions for scaled devices and low temperatures. The inter-cell program disturb can be addressed for several scaling approaches. Recent and future development of the PCM modeling activity have also been pointed out.

References

Fig. 19. Crystallization times for 2 k PCM cells at 160 and 180 °C and Monte Carlo simulation results.

scaling does not provide reliable T2 temperature below the 65 nm node, while isotropic scaling guarantees for a constant safe temperature T2 lower than Tdist. In order to exploit the higher current reduction capabilities of non-isotropic scaling, while providing acceptable program disturb performances, a mixed scaling approach can be introduced (Fig. 17). The non-isotropic scaling can be adopted up to F = 70 nm, where T2 = Tdist while for more scaled technologies the isotropic scaling permits to maintain constant T2 temperatures equal to Tdist. 9. Open issues The electro-thermal and phase-change simulator permits to account for readout, programming and data retention experimental data. Furthermore it allows (1) cell geometry optimization, (2) predictions for data-retention capabilities at low temperature and in scaled technology, (3) programming-current and (4) program-disturb predictions for scaled devices. In this work the lance and the lTrench architectures have been investigated, but any PCM geometry can be implemented. To gain a deeper quantitative understanding and predictability of PCM technology, some physical phenomena typical of chalcogenide materials must be further investigated and included in the model, like alternative transports and switching mechanisms [30–32], the amorphous resistance increase due to traps density variation [29] and the statistical variation among array-cells in data retention timess [33,34]. As regard the last issue, recently an array statistical 3D modeling of dataretention has been presented [34]. The Monte Carlo phase-change model previously presented was used and a spread in the nucleation probability was assumed in the active material in order to account for the spread in data-retention times ðtX Þ in cells arrays. The calculated crystallization time tX at different temperatures are in agreement with experimental data, as Fig. 19 shows. Note that the model also account for the different spread of tX at different T (the slope of the distributions in Fig. 19). In particular, in order to perform simulation on k-cells a reading scheme based on resistor network was adopted [34] instead of the previously discussed drift-diffusion scheme. The model thus permits retention predictions at array level for low-temperature and scaled technology. 10. Conclusions The state of the art of PCM physics-based electro-thermal and phase-change model has been reviewed. It represent a design tool for optimum cell geometry for actual and scaled technologies, in particular in terms of programming current and SET resistance.

[1] Lai S. Current status of the phase change memory and its future. IEDM Tech Dig 2003:255–8. [2] Atwood G, Bez R. Current status of chalcogenide phase change memory. In: Device research conference digest; 2005. p. 29–33. [3] Ovshinsky SR. Reversible electrical switching phenomena in disordered structures. Phys Rev Lett 1968;21:1450–3. [4] Pellizzer F, Benvenuti A, Gleixner B, Kim Y, Johnson B, Magistretti M et al. A 90 nm phase change memory technology for stand-alone non-volatile memory applications. In: Symp VLSI Tech Dig; 2006. p. 122–3. [5] Raoux S, Rettner CT, Jordan-Sweet JL, Deline VR, Philipp JB, Lung H-L. Scaling properties of phase change nanostructures and thin films. EPCOS 2006:905–8. [6] Schrott A, Lung H-L, Happ T, Lam C. Phase-change memory development status. VLSI-TSA 2007. [7] Ahn SJ, Song YJ, Jeong CW, Shin JM, Fai Y, Hwang YN, et al. Highly manufacturable high density phase change memory of 64Mb and beyond. IEDM Tech Dig 2004:907–10. [8] Cho SL et al. Highly scalable on-axis confined structure for high density PRAM beyond 256 Mb. VLSI Tech Dig 2005:96–7. [9] Ahn SJ et al. Highly reliable 50 nm contact cell technology for 256 Mb PRAM. In: Symp on VLSI Tech: 2005. p. 98–9. [10] Hwang YN, Lee SH, Ahn SJ, Lee SY, Ryoo KC, Hong HS, et al. Writing current reduction for high-density phase-change RAM. IEDM Tech Dig 2003:893. [11] Horii H, Yi JH, Park JH, Ha YH, Baek IG, Park SO et al. A novel cell technology using N-doped GeSbTe films for phase change RAM. In: Symp on VLSI Tech Dig; 2003. p. 177–8. [12] Matsuzaki N, Kurotsuchi K, Matsui Y, Tonomura O, Yamamoto N, Fujisaki Y, et al. Oxygen-doped Ge2Sb2Te5 phase-change memory cells featuring 1.5-V/100-mA standard 0.13 mm CMOS operations. IEDM Tech Dig 2005:738–41. [13] Chen YC, Rettner CT, Raoux S, Burr GW, Chen SH, Shelby RM, et al. Ultrathin phase-change bridge memory device using GeSb. IEDM Tech Dig 2006:777–80. [14] Song Y, Ryoo K, Hwang Y, Jeong C, Lim D, Park S et al. Highly reliable 256 Mb PRAM with advanced ring contact technology and novel encapsulating technology. In: Symp VLSI Tech Dig; 2006. p. 118–9. [15] Takaura N, Terao M, Kurotsuchi K, Yamauchi T, Tonomura O, Hanaoka Y. A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations. IEDM Tech Dig 2003;6:897. [16] Bergmann R, Breitwisch M, Burr GW, Cheek R, Chen CF, Chen SH et al. Novel one-mask self-heating pillar phase change memory. In: Symp VLSI Tech Dig; 2006. p. 120–1. [17] Pellizzer F, Pirovano A, Ottogalli F, Magistretti M, Scaravaggi M, Zuliani P et al. Novel lTrench phase-change memory cell for embedded and standalone non-volatile memory applications. In: Symp on VLSI Tech Dig; 2004. p. 18–9. [18] Wuttig M, Yamada N. Phase-change materials for rewriteable data storage. Nat Mater 2007;6. [19] Lacaita AL et al. Electrothermal and phase-change dynamics in chalcogenidebased memories. IEDM Tech Dig 2004;5:911–4. [20] Yamada N, Matsunaga T. Structure of laser-crystallized Ge2 Sb2+x Te5 sputtered thin films for use in optical memory. J Appl Phys 2000;88(12):7020–8. [21] Pirovano A, Lacaita AL, Benvenuti A, Pellizzer F, Bez R. Electronic switching in phase-change memories. IEEE Trans Electron Dev 2004;51:452–9. [22] Pirovano A, Redaelli A, Pellizzer F, Ottogalli F, Tosi M, Ielmini D. Reliability study of phase change nonvolatile memories. IEEE Trans Dev Mater Reliab 2004;4:422. [23] Cohen MH, Fritzsche H, Ovshinsky SR. Simple band model for amorphous semiconducting alloys. Phys Rev Lett 1969;22:1065–8. [24] Peng C, Cheng L, Mansuripur M. Experimental and theoretical investigations of laser-induced crystallization and amorphization in phase-change optical recording media. J Appl Phys 1997;82(9):4183–91. [25] Russo U, Redaelli A, Ielmini D, Lacaita AL. Geometry and material optimization for programming current scaling in phase-change memory. In: International conference on memory technology and design, ICMTD; 2007. [26] Pirovano A, Lacaita AL, Benvenuti A, Pellizzer F, Bez R. Scaling analysis of phase-change memory technology. IEDM Tech Dig 2003:699–702. [27] ITRS 2006 Update, available online at . [28] Pirovano A, Lacaita AL, Pellizzer F, Kostylev SA, Benvenuti A, Bez R. Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials. IEEE Trans Electron Dev 2004;51:714–9. [29] Ielmini D, Lavizzari S, Sharma D, Lacaita AL. Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation. IEDM Tech Dig 2007;77:3.

A.L. Lacaita et al. / Solid-State Electronics 52 (2008) 1443–1451 [30] Ielmini D, Lacaita AL, Mantegazza D. Recovery and drift dynamics of resistance and threshold voltages in phase-change memories. IEEE Trans Electron Dev 2007;54:308. [31] Ielmini D, Zhang Y. Physics-based analytical model of chalcogenide-based memories for array simulation. IEDM Tech Dig 2006:401–4. [32] Ielmini D, Zhang Y. Evidence for trap-limited transport in the sub-threshold conduction regime of chalcogenide glasses. Appl Phys Lett 2007;90:102–92.

1451

[33] Mantegazza D, Ielmini D, Pirovano A, Lacaita AL, Varesi E, Pellizzer F et al. Effects of the crystallization statistics on programming distributions in phasechange memory arrays. In: International conference on memory technology and design Tech Dig; 2007. p. 43–6. [34] Mantegazza D, Ielmini D, Varesi E, Pirovano A, Lacaita AL. Statistical analysis and modeling of programming and retention in phase change memory arrays. International Electron Device Meeting Tech Dig; 2007.