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Strain relaxation in SiGe due to process induced defects and their subsequent annealing behavior
PERGAMON
Microelectronics Reliability 38 (1998) 1611±1619
Strain relaxation in SiGe due to process induced defects and their subsequent annealing behavior D. Misra *, P.K. Swain { Department Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102, U.S.A. Received for publication 22 December 1997
Abstract Ion implantation and reactive ion etching are known to create defects in silicon which get cured during subsequent annealing operations. In this paper we have reported the annealing behavior of phosphorus implanted into strained SiGe layer at room temperature. The implantation was performed at 155 KeV with a dose of 1 1014/ cm2. Post implantation annealing was performed at 600, 700, 800 and 9008C for 10 s in a rapid thermal process furnace. Annealing behavior of defects generated as a consequence of dry etching is also reported. RTP annealing on reactive ion etching (RIE) etched samples were performed at 650, 700, 750 and 800 8C. I±V, C±V and DLTS measurements hint towards the presence of permanent dislocation loops created as a consequence of RIE and implantation causing strain relaxation. # 1998 Elsevier Science Ltd. All rights reserved.
1. Introduction The fact that the fundamental band gap (indirect) of strained GexSil-x layers covers a fairly large range between 1300 and 1550 nm [1, 2] which makes this alloy very attractive for applications involving long wavelength integrated opto-electronics using silicon substrate. Advanced epitaxial techniques like molecular beam epitaxy (MBE), rapid thermal chemical vapor deposition (RTCVD) has made it possible to grow pseudomorphic GexSil-x layers on silicon substrate [3]. Tunability of band gap in these ®lms has made them important for hetero-structure electronic devices. Several devices using SiGe like HBT [4, 5], pMOSFET [6, 7] have been demonstrated to have signi®cant performance leverage over the conventional bipolar transistors and p-MOSFET. This is made possible because of the enhanced mobility that is achieved due to selective doping. All these have stimulated
* Corresponding author. { Present address: Sarno Corporation, CNS300, Princeton, NJ 08543-5300, U.S.A.
much interest among researchers to obtain a thorough understanding of this alloy. Ion implantation is known to be an important process tool to introduce precise amounts of impurities (dopants) into semiconductors. Introduction of highpoint-defect density due to implantation can signi®cantly enhance the strain relaxation process in strained Si/SiGe/Si heterostructures. It is known that reduction in thermal stability following implantation is due to the ability of these implantation induced point defects to aggregate into small dislocation loops as observed in bulk semiconductors. Annealing at implant activation temperature (800±9008C; carried out for a time span varying from seconds to minutes) is known to propagate the dislocations over a length of tens of microns [8] and hence extension of these defects into the active device region is inevitable. These dislocations can result in large leakage currents and substantially reduce the gain and speed of the devices fabricated therefrom. It is known that implantation-induced damage in SixGe1-x and its subsequent annealing behavior are quite dierent from that normally observed in Si and Ge [9]. Si is amorphized to take advantage of solid-phase epitaxial regrowth during subsequent
0026-2714/98/$ - see front matter # 1998 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 9 8 ) 0 0 0 2 2 - 5
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D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
annealing to achieve dopant activation, minimize channeling tails, and decrease residual extended defect densities resulting from implantation. However, implantation-induced amorphization and solid-phase regrowth may result in relaxed SiGe of poor crystalline quality. The advantage of rapid thermal annealing which is normally performed for a much shorter time span as compared to the conventional furnace annealing is that it achieves the desired dopant activation without relieving the coherent strain as reported by Lie et al. [10]. During this short annealing period very few dislocations can nucleate and propagate, which are normally responsible for strain relaxation. On the other hand, reactive ion etching appears to be the most promising technique which is required to transform the submicron patterns for very large scale integrated (VLSI) circuits. However, it is known to have the disadvantage of being a low density plasma source utilizing high energy ions. Energetic ions and deep UV radiation are likely to create lattice damage due to physical defects by these ions and charge release/relaxation by photons which in turn produce trapping centers for electrons and holes at interfaces as well as in the bulk. It may also create strain-relieving mis®t dislocations and/or threading dislocations. Presence of these dislocations will greatly aect the performance of the devices and hence should be kept away from the active device regions. Thorough knowledge of the defects induced during device processing thus becomes necessary. Though reactive ion etching of Si has been studied in detail [11], although not much is known about SiGe at present. Wet etching on the other hand is known to be a rather non-destructive method and hence retains the characteristics of the starting materials after the processing is done. In bulk semiconductors annealing causes condensation of point defects into dislocation loops which then shrink and disappear after further annealing. The driving force behind the eventual shrinking is the reduction in self energy of the dislocation loops. Hence, it is important to be fully aware of various defects generated during processing and the eect of annealing on those defects. Lowering of the fundamental band gap in coherently strained SiGe is well established [1]. Relaxation in strain (as a consequence of implantation and annealing) is expected to increase the band gap as well as reduce the carrier mobility which will signi®cantly modulate the device characteristics fabricated therefrom. Hence it is important to be fully aware of the implantation and subsequent annealing behavior of strained SiGe. In this paper, annealing behavior following RIE, wet etching and implantation of phosphorus into a strained Si/SiGe/Si heterostructure is reported.
2. Experimental Typically 15% of Ge is used to grow strained SiGe ®lms for high mobility advantages. Undoped 530 AÊ thick Sil-xGex (x = 0.15) were grown on p-Si substrate by the conventional CVD at atmospheric pressure. A 1500±1900 AÊ thick Si cap layer was deposited on the Sil-xGex layer. SiH2Cl2 and GeH4 were used as the silicon and germanium source respectively. Planar diodes (circular, diameter = 200 mm) were formed by implanting phosphorus at room temperature at 155 KeV with a dose of 1014 cmÿ2 using a photolithography step. The projected range and straggle at this energy according to the TRIM-92 simulation code are about 1970 and 597 AÊ which approximately placed the peak of the implanted dose at the center of SiGe layer. Since the doping level of the p-Si substrate is 2 1016 cmÿ3, the implantation dose of 1014 cmÿ2 (which results in an impurity concentration of 05 1018 cmÿ3 [12]) was chosen to achieve a p±n junction device test structure. Also this low dose of 1014 cmÿ2 is not expected to amorphize the strained SiGe layer [13]. SiGe, if amorphized, can undergo solid-phase epitaxial regrowth after annealing with the regrown layers having inferior crystalline quality and a large density of threading dislocations [14]. Post implantation annealing was performed in a rapid thermal processing furnace in vacuum (10ÿ7 Torr) for 10 s. Annealing temperature was varied in the range 600±9008C in steps of 1008C. The temperature ramp-up was 908C/s and cool-down was 1608C/s. Assuming a similar diusion coecient for phosphorus in SiGe as for Si (the Ge content being less), Suprem-III simulations carried out on the above device structure indicates 100% dopant activation. To form contacts Al was deposited by thermal evaporation. Post metal annealing was performed in N2 at 4008C for 20 min to complete the test device. A further experiment was carried out in order to investigate the impact of RIE on the samples. A DRYTECH 100 reactor at a chamber pressure of 150 mTorr with a ¯ow rate of 50 sccm SF6 and Freon 115 each were used. The rf power was 400 W. The etch rate was 40 AÊ/s and etching was continued for 28 s for partial removal of the cap layer (approximately 110 AÊ). On the other hand wet etching was carried out in a strain sensitive etchant solution of 25 mg KOH, 1 mg K2Cr2O7, 25 ml propanol in 100 ml of water at 268C. The etch rate was 160 AÊ/min and etching was continued for 7 min. Both dry and wet etched samples were annealed at temperature of 650, 700, 750 and 8008C for 60 s in a rapid thermal process (RTP) reactor under vacuum. SiO2 was then deposited by LPCVD at 4508C. Thickness of SiO2 was 400 AÊ. Aluminum dots were then evaporated through a metal mask by thermal evaporation to make MOS capacitors. Back contact was made with Al deposition on the Si substrate.
D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
Fig. 1. Schematic drawing of the MOS device structure used for the investigations.
A post metal annealing was carried out at 3508C in ambient N2. A completed sample is shown in Fig. 1. Forward as well as reverse I±V characteristics of the diodes was measured using HP4145B at various temperatures. High frequency CV measurement of the MOS capacitators were performed using a Boonton 72BD capacitance meter and HP4145.
3. Results and discussions Current vs voltage characteristics of the implanted and annealed samples measured at 200 K are summarized in Fig. 1. An ideality factor (Z) for the diodes was calculated from the slope of these plots and is summarized in Table 1. It is known that the band gap (Eg) is related to the activation energy (Ea) for the forward current by the relation: Eg Ea qV kD ln If =D 1=T qV
1
where k is the Boltzmann's constant and T is the absolute temperature, from which the band gap can be
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estimated. Diode characteristics are ideal over 1±1.0 v (Fig. 2), and the band gap values thus calculated are summarized in Table 1. It is observed that the band gap increases from 0.940±1.010 eV as a function of annealing temperature. Fig. 3 demonstrates the DLTS spectra for the asimplanted and annealed samples. As may be seen from this ®gure there exists a peak for the as-implanted sample. As the samples are annealed in the temperature range 600±9008C, the single peak as seen for the as-implanted sample changed to two well resolved peaks (T1 and T2), corresponding to two distinct trap levels. It is noticed that the relative peak intensity for T2 is more than that of T1 for the 600 and 7008C annealed samples. But the intensities are reversed for the 800 and 9008C annealed samples. Samples annealed at 600 and 7008C for which T2 dominates over T1 indicates the presence of a three-dimensional network of dislocations [15]. With an increase in annealing temperature to 800 and 9008C, peak T1 dominates over T2 thus indicating that the DLTS measurements are more sensitive to the mis®t dislocations lying in the (100) growth plane. A typical Arrhenius plot employed to calculate the defect level is summarized in Fig. 4. The calculated defect levels and their concentrations are summarized in Table 1. The presence of such defects are due to ion implantation and subsequent annealing. Samples, as implanted and annealed at 600, 700 and 8008C, have Z values in the range of 1.19±1.28 indicating a dominant diusion current in the diodes (Fig. 2). However, it has a value of 1.71 for the 9008C annealed samples which clearly indicates that recombination current is dominating over the diusion current in these samples. Decrease in forward current in conjunction with increase in ideality factor may be understood by considering the generation of more recombination sites caused by ion implantation and subsequent annealing.
Table 1 Calculated ideality factor (Z), band gap, mis®t strain, defect levels and defect concentration for the phosphorus implanted Si0.85Ge0.15 planner diodes From DLTS measurements From I±V measurements
Defect level (eV)
Annealing temperature (8C)
Ideality factor (Z)
Band gap (eV)
Mis®t strain (%)$
T1
T2
Defect conc. (cmÿ3)
No annealing 600 700 800 900
1.19 1.21 1.24 1.28 1.71
0.940 0.954 0.966 0.980 1.010
0.582 0.534 0.460 0.398 0.281
0.23 0.32 0.312 0.304 0.236
Ð 0.56 0.43 0.405 0.358
9.01014 5.31014 1.21014 8.71013 7.71013
$Mis®t strain was calculated indirectly from the band gap.
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Table 2 Observed defect levels and defect concentrations for the dry- and wet-etched samples Annealing temperature (8C) Dry etched Wet etched
EcÿEt (eV) Defect conc. (cmÿ3) EcÿEt (eV) Defect conc. (cmÿ3)
650
700
750
800
0.62 8.151015 0.31 3.101015
0.57 7.721015 0.43 2.551015
0.56 7.361015 0.56 2.221015
0.44 7.071015 0.44 1.871015
Figures 5 and 6 demonstrate the DLTS spectra of the dry and wet etched samples respectively, annealed at dierent temperatures, recorded during cooling of the sample from 370 to 80 K in steps of 2 K. As may be seen from these ®gures there exists a peak for each sample and temperature. The calculated trap levels and the corresponding trap concentrations are summarized in Table 2. However, no DLTS peak was observed for the wet etched, unannealed samples, indicating the samples to be strained and free of defects in the SiGe layer. The presence of a defect level at 0.31 eV for the wet etched 6508C annealed sample could be due to small point defects. It is known that in bulk semiconductors annealing causes condensation of point defects into dislocation loops, which then eventually shrink and disappear after further annealing. Reduction in self energy of the dislocation loops is the driving force behind their shrinking. But if a dislocation is present in GexSil-x
and intends to expand it will impinge on the epilayer/ substrate interface. If the ®lms are strained the self energy of the loops will be balanced by the strain energy that is relaxed within the loop. The total energy is thus given by the algebraic sum of the two, i.e. Etotal Eloop ÿ Estrain :
2
The most general behavior of Eq. (2) is an initial increase of total energy with an increase in the radius of the circular loop r, which passes through a maximum activation barrier DE at a critical radius r0 and then decrease as r is further increased. It becomes zero at rl and then becomes negative. This is illustrated in Fig. 7. As the annealing temperature increases in a wet etched sample from 650 to 7008C the mobility of the point defects also increases. These point defects form dislocation loops of increased radius. However, their radius is smaller than the critical radius r0. Hence from
Fig. 2. Current vs. voltage characteristics of the as-implanted and annealed samples measured at 2008C.
D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
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Fig. 3. DLTS spectra obtained for the as-implanted and annealed samples.
the discussions above, Fig. 7, their energy will be increased and thus we observe a defect level at 0.43 eV. A similar mechanism increases the trap level to 0.56 eV after annealing at higher temperature i.e. 7508C. But a further annealing at 8008C increases the radius of the condensing loops beyond the critical radius r0 and thus
Fig. 4. A typical Arrhenius plot used to calculate the trap levels for the dry etched samples.
from Fig. 7 the total energy decreases, so the defect level moves to 0.44 eV [16]. It is well established that RIE creates dislocation loops either by high energy ion bombardment or by electron stress which are able to create mis®t dislocation due to their energies. So it is apparent that a dry etched sample will be less strained as compared with its wet etched counterpart. Hence, in our case we may assume that the dry etched 6508C sample is relatively more relaxed with respect to the 6508C wet etched one. It is obvious that a point defect/dislocation loop will move more freely (i.e. have higher mobility) in the dry etched sample than the wet etched one. So, the dry etched 6508C annealed sample will contain dislocation loops having a bigger radius which, from Fig. 7 will correspond to a higher energy. This may be the reason behind the trap level at 0.62 eV calculated for this sample. With an increase in the annealing temperature, dislocation loops condense and form bigger loops. However, it is observed that the energy of the defect levels decrease from 0.62 to 0.57, 0.56 and 0.44 eV for annealing at 700, 750 and 8008C, respectively. This clearly indicates that the radius of the dislocation loops present in the relatively relaxed 6508C annealed ®lm is already beyond the critical radius r0. As may be clearly seen from Fig. 7 any further increase in radius will decrease the total energy. Thus a dry etched sample is relaxed at a lower temperature as compared to a wet etched one prepared under similar conditions. A decreasing trap density with increasing annealing temperature in the dry as well as the wet etched samples is in line with the observed increase in the loop radius as per our model (Table 2). When the radius of the loops increases, they merge to form loops
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D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
Fig. 5. DLTS spectra obtained for the dry etched sample.
of a bigger radius and hence results in a decrease in their density. The appearance of the same defect level for the 750 and 8008C annealed, dry as well as wet etched sample,
according to our model indicates a similar lattice mechanism. This strongly suggest that the lattice is getting completely relaxed at 7508C and further annealing on the samples manifests the same behavior irrespec-
Fig. 6. DLTS signal obtained for the wet etched samples.
D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
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Fig. 7. Variation of total energy of the dislocation loops as a function of loop radius.
tive of the fact that they were dry etched or wet etched. Our results are in agreement with that of Hull et al. [17] which indicates that at low Ge concentration, annealing between 550 and 7508C causes signi®cant strain relaxation. An estimate of the size of the dislocation loops can be obtained by using Eq. (2) and the expressions for Eloop and Estrain given by Bacon and Crocker [18]. According to them mb2 r b2z n b2z Eloop 1 ÿ 1 ÿ b2 4 1 ÿ n b2 2 h pra i mb2 r ÿ 1:758 ln b 32 1 ÿ n2 2 b b2 6 ÿ 4n z2 ÿ 1 ÿ 2n 1 ÿ z2 ; 3 b b Estrain
pr2 m 1 ve bg cos w cos c be cos2 w: 1 ÿ v
4
From Eq. (2) it is observed that Etotal will be zero when the loop and strain energy as given above are equal; i.e. i mb2 r h nih pra 1ÿ ln ÿ 1:758 4 1 ÿ n 2 b pr2 m 1 ne b cos c cos y: 5 1 ÿ n
Simpli®cation of Eq. (5) gives: 0:85ln pr=2 0:06r; where the following numerical substitutions have been made: b = 4 AÊ, n = 0.3, a = 2, e = 0.04. cos c = 0.5 and cos y = 0.742 (see Ref [16] for a detailed discussion). Solving the above equation gives a value of r116AÊ (i.e. r0=3 AÊ). From the discussions above, it is known that the radii of the dry etched samples (r) lie in the range r0
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D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
Fig. 8. Weak beam dark ®eld TEM micrograph showing the dislocation loops.
mental band gap of coherently strained SiGe (containing 15% Ge) is lowered to 0.940 eV as compared to the unstrained SiGe which has a band gap of 1.02 eV. We observe from our measurements (Table 1) that implanted SiGe has a band gap of 0.940 eV which matches exactly with that of the coherently strained SiGe with 15% Ge. The observed increase in band gap with annealing (i.e. decrease in mis®t strain) (Table 1) can be understood by considering the existence of permanent dislocation loops created as a result of implantation and annealing which cause complete relaxation. From Table 1 it is seen that ion implanted samples after annealing at 600 and 7008C show defect levels of 0.56 and 0.44 eV, respectively. On the other hand the dry etched samples have similar defect levels for the 750 and 8008C annealed samples. From our proposed model it is believed that defect levels at 0.56 and 0.43 eV as seen for the dry etched samples are due to the presence of dislocation loops whose size increases with an increase in annealing temperature (Fig. 6). Hence it could be inferred that the defect levels of 0.56 and 0.44 eV for the ion implanted samples annealed at 600 and 7008C, are also due to dislocation loops. As the annealing temperature increases further to 800 and 9008C the defect levels change to 0.405 and 0.35 eV respectively thus indicating the presence of loops of larger radii (Fig. 7). We also observe another set of defect level that changes from 0.32±0.23 eV with annealing in the range 600±9008C. These defects, as explained earlier, are due to point defects. During implantation highly energetic ions impinge on the Si/ SiGe/Si layer and collides with some host atoms thereby creating point defects. Some of these incident ions enter into the bulk of Si/SiGe/Si that creates the dislocation loops.
4. Conclusions The above investigations reveal that ion implantation alone into strained SiGe layer does not relieve the strain. However, post implantation annealing in the range 600 to 9008C causes relaxation in strain which consequently increases the band gap. Degradation in the ideality factor is observed with an increase in annealing temperature indicating the presence of additional recombination centers. The generation of permanent dislocation loops appears to contribe to the relaxation mechanism. On the other hand, reactive ion etching induces dislocation loops whose size increases with an increase in annealing temperature which eventually changes the trap levels. It is also known that RTP annealing of p-implanted SiGe at 7008C in the range 10±40 s provides almost 100% dopant activation. Hence, SiGe can be integrated into Si technology for high speed device fabrications by suitably choosing the process conditions where complete dopant activation can be achieved without relaxing the strain, thereby preserving superior device quality.
References [1] Braunstein R, Moore AR, Herman F. Phys. Rev. 1958;109:695. [2] Lang DV, People R, Beans JC, Sergent AM. Appl. Phys. Lett. 1985;47:1333. [3] People R. IEEE J. Quantum Electron. 1986;QE-22:1696. [4] Patton GL, Comfort JH, Meyerson BS, Crabbe EF, Scilla GJ, DeFresart E, Stork JMC, Sun JYC, Harame DL, Burghartz JN. IEEE Electron Dev. Lett. 1990;11:171. [5] Sturm JC, Prinz EJ, Magge CW. IEEE Electron Dev. Lett. 1991;12:303. [6] Nayak DK, Woo JCS, Park JS, Wang KL, MacWilliams KP. IEEE Electron Dev. Lett. 1991;12:154.
D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619 [7] Verdonckt-Vandebroek S, Crabbe EF, Meyerson BS, Harame DL, Restle PJ, Stork JMC, Johnson JB. IEEE Trans. Electron Dev. 1994;41(1):90. [8] Hull R, Bean JC, Bahnck DE, Peticolas L, Short KT, Unterwald FC. Interpretation of dislocation propagation velocities in strained GexSil ÿ x/Si(100) heterostructures by the diusive kink pair model.. J. Appl. Phys 1991;70:2052±65. [9] Lie DYC, Vantomme A, Eisen F, Nicolet MA, Carns TK, Wang KL. J. Appl. Phys 1993;74:6039. [10] Lie DYC, Song JH, Nicolet MA, Theodore ND. Advantage of rapid thermal annealing over furnace annealing for p-implanted metastable Si/Ge0.12Si0.88. Appl. Phys. Lett. 1995; 66(5):592±4. [11] Coburn JW. Plasma Etching and Reactive Ion Etching. New York: American vacuum Society, 1982. [12] Gandhi SK. VLSI fabrication principles. New York: John Wiley and Sons, 1994.
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[13] Hull R, Bean JC, Bonar JM, Higashi GS, Short KT, Temkin H, White AE. Enhanced strain relaxation in Si/ GexSil ÿ x/Si heterostructure via point-defect concentration introduced by ion implantation. Appl. Phys. Lett. 1990;56(24):2445±7. [14] Lie DYC, Theodore ND, Song JH, Nicolet MA. Solidphase epitaxial regrowth and dopant activation of pimplanted metastable pseudomorphic Ge0.12Si0.88 on Si(100). J. Appl. Phys. 1995;77(10):5160±6. [15] Grillot PN, Ringel SA, Watson GP, Fitzgerald EA, Xie YH. Mat. Res. Soc. Symp. Proc. 1994;vol. 325:159±64. [16] Swain PK, Misra D, Thompson PE. Eect of dry etching and subsequent annealing of Si/SiGe/Si heterostructure. J. Appl. Phys. 1996;79(8):4402±6. [17] Hull R, Bean JC, Leibenguth REd. Mater. Res. Soc. Symp. Proc. 1988;505:116. [18] Bacon DJ, Crocker AG. Phil. Mag. 1965;12:195.
Microelectronics Reliability 38 (1998) 1611±1619
Strain relaxation in SiGe due to process induced defects and their subsequent annealing behavior D. Misra *, P.K. Swain { Department Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102, U.S.A. Received for publication 22 December 1997
Abstract Ion implantation and reactive ion etching are known to create defects in silicon which get cured during subsequent annealing operations. In this paper we have reported the annealing behavior of phosphorus implanted into strained SiGe layer at room temperature. The implantation was performed at 155 KeV with a dose of 1 1014/ cm2. Post implantation annealing was performed at 600, 700, 800 and 9008C for 10 s in a rapid thermal process furnace. Annealing behavior of defects generated as a consequence of dry etching is also reported. RTP annealing on reactive ion etching (RIE) etched samples were performed at 650, 700, 750 and 800 8C. I±V, C±V and DLTS measurements hint towards the presence of permanent dislocation loops created as a consequence of RIE and implantation causing strain relaxation. # 1998 Elsevier Science Ltd. All rights reserved.
1. Introduction The fact that the fundamental band gap (indirect) of strained GexSil-x layers covers a fairly large range between 1300 and 1550 nm [1, 2] which makes this alloy very attractive for applications involving long wavelength integrated opto-electronics using silicon substrate. Advanced epitaxial techniques like molecular beam epitaxy (MBE), rapid thermal chemical vapor deposition (RTCVD) has made it possible to grow pseudomorphic GexSil-x layers on silicon substrate [3]. Tunability of band gap in these ®lms has made them important for hetero-structure electronic devices. Several devices using SiGe like HBT [4, 5], pMOSFET [6, 7] have been demonstrated to have signi®cant performance leverage over the conventional bipolar transistors and p-MOSFET. This is made possible because of the enhanced mobility that is achieved due to selective doping. All these have stimulated
* Corresponding author. { Present address: Sarno Corporation, CNS300, Princeton, NJ 08543-5300, U.S.A.
much interest among researchers to obtain a thorough understanding of this alloy. Ion implantation is known to be an important process tool to introduce precise amounts of impurities (dopants) into semiconductors. Introduction of highpoint-defect density due to implantation can signi®cantly enhance the strain relaxation process in strained Si/SiGe/Si heterostructures. It is known that reduction in thermal stability following implantation is due to the ability of these implantation induced point defects to aggregate into small dislocation loops as observed in bulk semiconductors. Annealing at implant activation temperature (800±9008C; carried out for a time span varying from seconds to minutes) is known to propagate the dislocations over a length of tens of microns [8] and hence extension of these defects into the active device region is inevitable. These dislocations can result in large leakage currents and substantially reduce the gain and speed of the devices fabricated therefrom. It is known that implantation-induced damage in SixGe1-x and its subsequent annealing behavior are quite dierent from that normally observed in Si and Ge [9]. Si is amorphized to take advantage of solid-phase epitaxial regrowth during subsequent
0026-2714/98/$ - see front matter # 1998 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 9 8 ) 0 0 0 2 2 - 5
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D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
annealing to achieve dopant activation, minimize channeling tails, and decrease residual extended defect densities resulting from implantation. However, implantation-induced amorphization and solid-phase regrowth may result in relaxed SiGe of poor crystalline quality. The advantage of rapid thermal annealing which is normally performed for a much shorter time span as compared to the conventional furnace annealing is that it achieves the desired dopant activation without relieving the coherent strain as reported by Lie et al. [10]. During this short annealing period very few dislocations can nucleate and propagate, which are normally responsible for strain relaxation. On the other hand, reactive ion etching appears to be the most promising technique which is required to transform the submicron patterns for very large scale integrated (VLSI) circuits. However, it is known to have the disadvantage of being a low density plasma source utilizing high energy ions. Energetic ions and deep UV radiation are likely to create lattice damage due to physical defects by these ions and charge release/relaxation by photons which in turn produce trapping centers for electrons and holes at interfaces as well as in the bulk. It may also create strain-relieving mis®t dislocations and/or threading dislocations. Presence of these dislocations will greatly aect the performance of the devices and hence should be kept away from the active device regions. Thorough knowledge of the defects induced during device processing thus becomes necessary. Though reactive ion etching of Si has been studied in detail [11], although not much is known about SiGe at present. Wet etching on the other hand is known to be a rather non-destructive method and hence retains the characteristics of the starting materials after the processing is done. In bulk semiconductors annealing causes condensation of point defects into dislocation loops which then shrink and disappear after further annealing. The driving force behind the eventual shrinking is the reduction in self energy of the dislocation loops. Hence, it is important to be fully aware of various defects generated during processing and the eect of annealing on those defects. Lowering of the fundamental band gap in coherently strained SiGe is well established [1]. Relaxation in strain (as a consequence of implantation and annealing) is expected to increase the band gap as well as reduce the carrier mobility which will signi®cantly modulate the device characteristics fabricated therefrom. Hence it is important to be fully aware of the implantation and subsequent annealing behavior of strained SiGe. In this paper, annealing behavior following RIE, wet etching and implantation of phosphorus into a strained Si/SiGe/Si heterostructure is reported.
2. Experimental Typically 15% of Ge is used to grow strained SiGe ®lms for high mobility advantages. Undoped 530 AÊ thick Sil-xGex (x = 0.15) were grown on p-Si substrate by the conventional CVD at atmospheric pressure. A 1500±1900 AÊ thick Si cap layer was deposited on the Sil-xGex layer. SiH2Cl2 and GeH4 were used as the silicon and germanium source respectively. Planar diodes (circular, diameter = 200 mm) were formed by implanting phosphorus at room temperature at 155 KeV with a dose of 1014 cmÿ2 using a photolithography step. The projected range and straggle at this energy according to the TRIM-92 simulation code are about 1970 and 597 AÊ which approximately placed the peak of the implanted dose at the center of SiGe layer. Since the doping level of the p-Si substrate is 2 1016 cmÿ3, the implantation dose of 1014 cmÿ2 (which results in an impurity concentration of 05 1018 cmÿ3 [12]) was chosen to achieve a p±n junction device test structure. Also this low dose of 1014 cmÿ2 is not expected to amorphize the strained SiGe layer [13]. SiGe, if amorphized, can undergo solid-phase epitaxial regrowth after annealing with the regrown layers having inferior crystalline quality and a large density of threading dislocations [14]. Post implantation annealing was performed in a rapid thermal processing furnace in vacuum (10ÿ7 Torr) for 10 s. Annealing temperature was varied in the range 600±9008C in steps of 1008C. The temperature ramp-up was 908C/s and cool-down was 1608C/s. Assuming a similar diusion coecient for phosphorus in SiGe as for Si (the Ge content being less), Suprem-III simulations carried out on the above device structure indicates 100% dopant activation. To form contacts Al was deposited by thermal evaporation. Post metal annealing was performed in N2 at 4008C for 20 min to complete the test device. A further experiment was carried out in order to investigate the impact of RIE on the samples. A DRYTECH 100 reactor at a chamber pressure of 150 mTorr with a ¯ow rate of 50 sccm SF6 and Freon 115 each were used. The rf power was 400 W. The etch rate was 40 AÊ/s and etching was continued for 28 s for partial removal of the cap layer (approximately 110 AÊ). On the other hand wet etching was carried out in a strain sensitive etchant solution of 25 mg KOH, 1 mg K2Cr2O7, 25 ml propanol in 100 ml of water at 268C. The etch rate was 160 AÊ/min and etching was continued for 7 min. Both dry and wet etched samples were annealed at temperature of 650, 700, 750 and 8008C for 60 s in a rapid thermal process (RTP) reactor under vacuum. SiO2 was then deposited by LPCVD at 4508C. Thickness of SiO2 was 400 AÊ. Aluminum dots were then evaporated through a metal mask by thermal evaporation to make MOS capacitors. Back contact was made with Al deposition on the Si substrate.
D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
Fig. 1. Schematic drawing of the MOS device structure used for the investigations.
A post metal annealing was carried out at 3508C in ambient N2. A completed sample is shown in Fig. 1. Forward as well as reverse I±V characteristics of the diodes was measured using HP4145B at various temperatures. High frequency CV measurement of the MOS capacitators were performed using a Boonton 72BD capacitance meter and HP4145.
3. Results and discussions Current vs voltage characteristics of the implanted and annealed samples measured at 200 K are summarized in Fig. 1. An ideality factor (Z) for the diodes was calculated from the slope of these plots and is summarized in Table 1. It is known that the band gap (Eg) is related to the activation energy (Ea) for the forward current by the relation: Eg Ea qV kD ln If =D 1=T qV
1
where k is the Boltzmann's constant and T is the absolute temperature, from which the band gap can be
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estimated. Diode characteristics are ideal over 1±1.0 v (Fig. 2), and the band gap values thus calculated are summarized in Table 1. It is observed that the band gap increases from 0.940±1.010 eV as a function of annealing temperature. Fig. 3 demonstrates the DLTS spectra for the asimplanted and annealed samples. As may be seen from this ®gure there exists a peak for the as-implanted sample. As the samples are annealed in the temperature range 600±9008C, the single peak as seen for the as-implanted sample changed to two well resolved peaks (T1 and T2), corresponding to two distinct trap levels. It is noticed that the relative peak intensity for T2 is more than that of T1 for the 600 and 7008C annealed samples. But the intensities are reversed for the 800 and 9008C annealed samples. Samples annealed at 600 and 7008C for which T2 dominates over T1 indicates the presence of a three-dimensional network of dislocations [15]. With an increase in annealing temperature to 800 and 9008C, peak T1 dominates over T2 thus indicating that the DLTS measurements are more sensitive to the mis®t dislocations lying in the (100) growth plane. A typical Arrhenius plot employed to calculate the defect level is summarized in Fig. 4. The calculated defect levels and their concentrations are summarized in Table 1. The presence of such defects are due to ion implantation and subsequent annealing. Samples, as implanted and annealed at 600, 700 and 8008C, have Z values in the range of 1.19±1.28 indicating a dominant diusion current in the diodes (Fig. 2). However, it has a value of 1.71 for the 9008C annealed samples which clearly indicates that recombination current is dominating over the diusion current in these samples. Decrease in forward current in conjunction with increase in ideality factor may be understood by considering the generation of more recombination sites caused by ion implantation and subsequent annealing.
Table 1 Calculated ideality factor (Z), band gap, mis®t strain, defect levels and defect concentration for the phosphorus implanted Si0.85Ge0.15 planner diodes From DLTS measurements From I±V measurements
Defect level (eV)
Annealing temperature (8C)
Ideality factor (Z)
Band gap (eV)
Mis®t strain (%)$
T1
T2
Defect conc. (cmÿ3)
No annealing 600 700 800 900
1.19 1.21 1.24 1.28 1.71
0.940 0.954 0.966 0.980 1.010
0.582 0.534 0.460 0.398 0.281
0.23 0.32 0.312 0.304 0.236
Ð 0.56 0.43 0.405 0.358
9.01014 5.31014 1.21014 8.71013 7.71013
$Mis®t strain was calculated indirectly from the band gap.
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D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
Table 2 Observed defect levels and defect concentrations for the dry- and wet-etched samples Annealing temperature (8C) Dry etched Wet etched
EcÿEt (eV) Defect conc. (cmÿ3) EcÿEt (eV) Defect conc. (cmÿ3)
650
700
750
800
0.62 8.151015 0.31 3.101015
0.57 7.721015 0.43 2.551015
0.56 7.361015 0.56 2.221015
0.44 7.071015 0.44 1.871015
Figures 5 and 6 demonstrate the DLTS spectra of the dry and wet etched samples respectively, annealed at dierent temperatures, recorded during cooling of the sample from 370 to 80 K in steps of 2 K. As may be seen from these ®gures there exists a peak for each sample and temperature. The calculated trap levels and the corresponding trap concentrations are summarized in Table 2. However, no DLTS peak was observed for the wet etched, unannealed samples, indicating the samples to be strained and free of defects in the SiGe layer. The presence of a defect level at 0.31 eV for the wet etched 6508C annealed sample could be due to small point defects. It is known that in bulk semiconductors annealing causes condensation of point defects into dislocation loops, which then eventually shrink and disappear after further annealing. Reduction in self energy of the dislocation loops is the driving force behind their shrinking. But if a dislocation is present in GexSil-x
and intends to expand it will impinge on the epilayer/ substrate interface. If the ®lms are strained the self energy of the loops will be balanced by the strain energy that is relaxed within the loop. The total energy is thus given by the algebraic sum of the two, i.e. Etotal Eloop ÿ Estrain :
2
The most general behavior of Eq. (2) is an initial increase of total energy with an increase in the radius of the circular loop r, which passes through a maximum activation barrier DE at a critical radius r0 and then decrease as r is further increased. It becomes zero at rl and then becomes negative. This is illustrated in Fig. 7. As the annealing temperature increases in a wet etched sample from 650 to 7008C the mobility of the point defects also increases. These point defects form dislocation loops of increased radius. However, their radius is smaller than the critical radius r0. Hence from
Fig. 2. Current vs. voltage characteristics of the as-implanted and annealed samples measured at 2008C.
D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
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Fig. 3. DLTS spectra obtained for the as-implanted and annealed samples.
the discussions above, Fig. 7, their energy will be increased and thus we observe a defect level at 0.43 eV. A similar mechanism increases the trap level to 0.56 eV after annealing at higher temperature i.e. 7508C. But a further annealing at 8008C increases the radius of the condensing loops beyond the critical radius r0 and thus
Fig. 4. A typical Arrhenius plot used to calculate the trap levels for the dry etched samples.
from Fig. 7 the total energy decreases, so the defect level moves to 0.44 eV [16]. It is well established that RIE creates dislocation loops either by high energy ion bombardment or by electron stress which are able to create mis®t dislocation due to their energies. So it is apparent that a dry etched sample will be less strained as compared with its wet etched counterpart. Hence, in our case we may assume that the dry etched 6508C sample is relatively more relaxed with respect to the 6508C wet etched one. It is obvious that a point defect/dislocation loop will move more freely (i.e. have higher mobility) in the dry etched sample than the wet etched one. So, the dry etched 6508C annealed sample will contain dislocation loops having a bigger radius which, from Fig. 7 will correspond to a higher energy. This may be the reason behind the trap level at 0.62 eV calculated for this sample. With an increase in the annealing temperature, dislocation loops condense and form bigger loops. However, it is observed that the energy of the defect levels decrease from 0.62 to 0.57, 0.56 and 0.44 eV for annealing at 700, 750 and 8008C, respectively. This clearly indicates that the radius of the dislocation loops present in the relatively relaxed 6508C annealed ®lm is already beyond the critical radius r0. As may be clearly seen from Fig. 7 any further increase in radius will decrease the total energy. Thus a dry etched sample is relaxed at a lower temperature as compared to a wet etched one prepared under similar conditions. A decreasing trap density with increasing annealing temperature in the dry as well as the wet etched samples is in line with the observed increase in the loop radius as per our model (Table 2). When the radius of the loops increases, they merge to form loops
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D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
Fig. 5. DLTS spectra obtained for the dry etched sample.
of a bigger radius and hence results in a decrease in their density. The appearance of the same defect level for the 750 and 8008C annealed, dry as well as wet etched sample,
according to our model indicates a similar lattice mechanism. This strongly suggest that the lattice is getting completely relaxed at 7508C and further annealing on the samples manifests the same behavior irrespec-
Fig. 6. DLTS signal obtained for the wet etched samples.
D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
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Fig. 7. Variation of total energy of the dislocation loops as a function of loop radius.
tive of the fact that they were dry etched or wet etched. Our results are in agreement with that of Hull et al. [17] which indicates that at low Ge concentration, annealing between 550 and 7508C causes signi®cant strain relaxation. An estimate of the size of the dislocation loops can be obtained by using Eq. (2) and the expressions for Eloop and Estrain given by Bacon and Crocker [18]. According to them mb2 r b2z n b2z Eloop 1 ÿ 1 ÿ b2 4 1 ÿ n b2 2 h pra i mb2 r ÿ 1:758 ln b 32 1 ÿ n2 2 b b2 6 ÿ 4n z2 ÿ 1 ÿ 2n 1 ÿ z2 ; 3 b b Estrain
pr2 m 1 ve bg cos w cos c be cos2 w: 1 ÿ v
4
From Eq. (2) it is observed that Etotal will be zero when the loop and strain energy as given above are equal; i.e. i mb2 r h nih pra 1ÿ ln ÿ 1:758 4 1 ÿ n 2 b pr2 m 1 ne b cos c cos y: 5 1 ÿ n
Simpli®cation of Eq. (5) gives: 0:85ln pr=2 0:06r; where the following numerical substitutions have been made: b = 4 AÊ, n = 0.3, a = 2, e = 0.04. cos c = 0.5 and cos y = 0.742 (see Ref [16] for a detailed discussion). Solving the above equation gives a value of r116AÊ (i.e. r0=3 AÊ). From the discussions above, it is known that the radii of the dry etched samples (r) lie in the range r0
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D. Misra, P.K. Swain / Microelectronics Reliability 38 (1998) 1611±1619
Fig. 8. Weak beam dark ®eld TEM micrograph showing the dislocation loops.
mental band gap of coherently strained SiGe (containing 15% Ge) is lowered to 0.940 eV as compared to the unstrained SiGe which has a band gap of 1.02 eV. We observe from our measurements (Table 1) that implanted SiGe has a band gap of 0.940 eV which matches exactly with that of the coherently strained SiGe with 15% Ge. The observed increase in band gap with annealing (i.e. decrease in mis®t strain) (Table 1) can be understood by considering the existence of permanent dislocation loops created as a result of implantation and annealing which cause complete relaxation. From Table 1 it is seen that ion implanted samples after annealing at 600 and 7008C show defect levels of 0.56 and 0.44 eV, respectively. On the other hand the dry etched samples have similar defect levels for the 750 and 8008C annealed samples. From our proposed model it is believed that defect levels at 0.56 and 0.43 eV as seen for the dry etched samples are due to the presence of dislocation loops whose size increases with an increase in annealing temperature (Fig. 6). Hence it could be inferred that the defect levels of 0.56 and 0.44 eV for the ion implanted samples annealed at 600 and 7008C, are also due to dislocation loops. As the annealing temperature increases further to 800 and 9008C the defect levels change to 0.405 and 0.35 eV respectively thus indicating the presence of loops of larger radii (Fig. 7). We also observe another set of defect level that changes from 0.32±0.23 eV with annealing in the range 600±9008C. These defects, as explained earlier, are due to point defects. During implantation highly energetic ions impinge on the Si/ SiGe/Si layer and collides with some host atoms thereby creating point defects. Some of these incident ions enter into the bulk of Si/SiGe/Si that creates the dislocation loops.
4. Conclusions The above investigations reveal that ion implantation alone into strained SiGe layer does not relieve the strain. However, post implantation annealing in the range 600 to 9008C causes relaxation in strain which consequently increases the band gap. Degradation in the ideality factor is observed with an increase in annealing temperature indicating the presence of additional recombination centers. The generation of permanent dislocation loops appears to contribe to the relaxation mechanism. On the other hand, reactive ion etching induces dislocation loops whose size increases with an increase in annealing temperature which eventually changes the trap levels. It is also known that RTP annealing of p-implanted SiGe at 7008C in the range 10±40 s provides almost 100% dopant activation. Hence, SiGe can be integrated into Si technology for high speed device fabrications by suitably choosing the process conditions where complete dopant activation can be achieved without relaxing the strain, thereby preserving superior device quality.
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