Strategy of one and half layer routing

Microprocessing and Microprogramming32 (1991) 417-424 North-Holland

STRATEGY

OF ONE

AND

417

HALF LAYER ROUTLNG

Michal Servlt, Jan Schmidt Czech Technical University, Department of Computers, Kariovo n~m~st~ 13, Praha 2, CS-12135 Czechoslovakia, phone (~-42 2) 293485, fox (+42 2)2~0151

Routing in one custom and one predefined interconnection layer environment represents a specific problem for automatic routers. A proven strategy of one-and-half layer muting is d~'ribed. The consists of three consecutive phases: an initial routing phase, a completion phase and an optimization phase. This strategy can be easily adapted to more complex routing environments. A maze-type router operating on a general grid-graph model of a routing space plays a key role in the phases. The quality of a path is measured by a 2-heredltary incremental cost function. This makes it possible to avoid the misuse of predefined underpasses as well as to establish routing d i r ~ i o n priorities. A designer can easily influence the performance of the router beea~e the topobgy of a path generated depends on the cost function definition. The initial routing phase consists of net ordering followed by routing all the nets in one-at-a-time mode. The completion phase is based on re-ordering and re-routing of incomplete and ~blockage" nets. The optimizatlon phase consists of the cost function re-definition foflowed by re-routing of all the nets.

1

Introduction

The choice of a suitable routing strategy depends generally on the environment in which the routing is performed. The two-custom routing laver environment (for example in the case of ]C's with two metal interconnection layers) is the most popular and therefore well examined. However, cheap MOS gate arrays use only one custom metal layer plus a predellned polysilicon layer for interconnection. The polysilicon layer contains a large number of prefabricated underpasses (polysilicon bars). Connection between the underpasses and metal segments are made through predetlned vias. This une-and-half intercoanection layer environment represents a specific problem for routers because the routing space is complicated by a high degree of irregularity and because the rules of efficient routing are ~ t trivial. Therefore, an efficient one-and-half router should be able to obey complex rules in complex space in order to reach reasonable routing performance. Automatic routing methods can be classified as ~areaoriented" methods and "net-oriented" methods. Channel touters, switchbox reuters, gree~ty routers, single row

routers and global touters are typical examp~ of areaoriented methods which manage to achieve suboptL~num assignment of aH net segments to the given routing area. Area-orlented m e t h o d s contain strong m e c h ~ allowing the solution of conflicts among routing space demands of different nets. Unfortunately, such mechan/sms can be implemented efficiently only if the rout/rig space and wiring patterns ate simple (for example in the c ~ e of a classical channel model [1, 9]) or the size of a problem is relatively small (for example in the case of a global graph model [2]). Obviously, the real one-and-half layer routing problems are neither simple nor small. Therefore we were forced to focus our attention to net-oriented methods. N e t - o r i e n t e d m e t h o d s work by trying to connect one connection at a time. The basis of these methods is an algorithm for finding a path, called a link, interconnecting two pins or more general objects. As far as the author knows, the Lee algorithm [3] is tbe first one d~igavd for this purpose. It is actually an application of the shortest path algorithm presented by Moore [4] to a grid structure representing routing space. The original Lee algorithm was followed by a large number of suggestions on devebping efficient implementations, composing new strategies

M. Servit, J. Schmidt

418

simulating the human way of routing, and applying it to a different environments, including current VLSI design (for review see [5, 6]). Basically, the demands of a designer are expressed in terms of cost f u n c t i o n definition. These ~gorithms, oftee referred to as maze ~dgor~thms, are still alive as they are very general, easily adaptable to different routing rules and guarantee finding a path if one exists. It will be shown how to adapt a maze router to one-and-half interconnection layer environment. The net oriented methods work in a one-connection-at-atime mode. The solution depen.-ls on the order in which nets are attempted. Either an unwise ordering or unforeseen wire patterns could cause a routing failure. It will be shown that these disadvantages can be suppressed.

El zvirDnrnent and its M o d e l The one-a~d-half interconnection layer environment consists of one custom layer and one prefabricated layer. The custom layer is essentiallyfree for routing. The prefabricated layer contains fixed wiring patterns. Both layers are interconnected through fixed or custom vias.

The VUGAF gate array family can serve as an example. The architecture of this CMOS one custom layer gate array family is simple: basic cells are arranged into columns separated by routing channels, I/O cells are placed on the periphery of a chip. However, the internal structure of interconnection layers is complicated (see Fig.l). The polysilicon (prefabricated) layer consists of fixed polysilicon underpasses which have different orientations, different lengths and different number of fixed vias (see UI, U$ ... [15). The metal (custom) layer contains a number of predefined wires forming ground and power leads (see GND, UDD) and internal eustomisation of cells (see IN, OUT). A cell customization leaves usually some "internal" cell space for routing on both layers. This space represents generally essential part of the overall routing capability. A two-layer grid g r a p h is a natural model of routing environment of this kind [5]. The construction of this graph is simple. The metal (first) layer is represented by a rectilinear (not necessarily equidistant) grid. Vias are represented by edges parallel to the z-axis. Polysilicon underpasses are represented by second layer edges and vertices. Edges and vertices of our graph model can be either free for routing or used for customization. The grid graph of the lower leftpart of Fig.1 isshown in Fig.2.

~Wpq~WR~e

~ i-J

L

i IN

OUT UDD OUT I H

OUT GHD OUT

IN

Figure 1: The example of internal structure of intereonnection layers.

Strategy of o ~ and hall layer routing

Metal

0

O

O

U5

419

In the initial r o u t i n g p h a s e we first order the n e ~ and then route them one-at-a-time. The routing 5o]ution depends generally on the order in which nets are attempted. We have found experimentally that a proper ordering increases the probability of success [8]. A simple estimation of a net's complexity [8, 10] is uaed as a sorting key. An efficient maze-path algorithm is used as an approach to net routing. The algorithm is e x p i r e d (n - l)-times when an n-pin net is routed. A llnk is constructed in each run. This guarantees suboptgmum Steiner tree construction [5, 8].

Figure 2: The example of grid-graph model of intercon-

nection layers.

Strategy of Routing

3

Our primary goal is to achieve 100% completion. Moreover, the total length of underpasses used for routing should be minimized because polysilicon is a poor conductor. These aims are often in contradiction. Therefore we suggested the strategy consisting of three consecutive phases: an initial routing phase, a completion phr~e and an optimization phase. The maze-type router plays a key role in all phases because the topology of a path generated depends on the cost function definition. A designer can express his demands in terms of cost increments. The following pseudocode outlines the strategy: begin

{initial routing phase} "order all nets" repeat "route a net" u n t i l "all nets have been routed"

A specific treatment can be given to sensitive nets (clock etc.) in the initial routing phase by increasing their priority in ordering and/or by changing the c ~ t function definition in favour of metal wires. The initial routing phase produces a feasible - - often complete - - solution. The c o m p l e t i o n p h a s e is empioyed in case 100% completion is not aciffeved. This phase consists of three steps. First, a group of nets containing incomplete and "blockage" nets is determined and removed by a designer. Then, a designer sorts the removed nets so that incomplete nets are routed first. Tiffs order increases the probability of success. Finally, the chosen nets are re-routed in one-at-a-time mode. "gifts process is repeated until a complete solution is achieved. During the o p t i m i z a t i o n phase, the co6t function is changed in favour of the metal wires. The optimizer ripsup and reroutes all the nets one at a time while maintaining the feasibility of routing until no more improvements can be obtained for any nets. This approach is simple and easily adaptable to different optimization criteria, which makes it preferable to traditional opthnizers [5, 12, 13] that are very complicated or have a limited scope.

{completion phase} while "routing pattern is not complete" d o begin "choose a group of nets which are to be re-routed" "order a group of nets" "remove a group of nets" repeat "route a net" u n t i l "all chosen nets have been re-routed" end

{ optimization phase} "change cost increments" repeat "remove a net" "route a net" u n t i l "all nets have been re-routed" end.

4

Initial R o u t i n g Rules

Our experience with manual single-custom layer routing has provided us with two rules of thumb for successful initial routing: ® Long metal wires parallel to polysillcon underp~ses should be avoided (see Fig.3a). Therefore the routing space has to be divided into areas where the x-direction is preferred for metal wires and areas where the y-direction is preferred for metal wires. • Misuse of underpasses should be avoided because each underpass can serve only one net (see Fig.3b).

M. Se~ft, ~,Schm~t

420

In other words, metal wires which do not "cross" alas are preferred tc metal wires which "cross" vias

unintentionally.

In order to avoid the misuse of underpasses it is neceessary to use a 2 - h e r e d l t a r y c o s t f u n c t i o n cl = f ( e i , e i - I ) for metal layer edges. The "standard" value of cost increment is employed when an underpass is used correctly. The "penalty" is added when an underpass is used incorrectly.

~AD

GOOD

To be more specific, ~11 via edges el have the same value V of cost increment and all polysilicon edges el have the same value P of cost increment which does not depend on previous edge ei-l. For a metal layer edge ci, the value of a cost increment depends on the orientation of ei as well as on ei-1. The standard value M p of cost for the preferred direction or the standard value M n of cost for the direction not preferred is employed if ei-n is a via edge or if it is a metal layer edge and there is not the via edge emanating from the vertex which is common to ei and ei-n. Example of the path-cost computation is shown in Fig.4 where P = 1, V = 0, MP = 1 and M n = 3.

a

BAD

GOOD )m a

m

Im

|

-

,.

~

m

m

)

well as the cost increments associated with the via edges can be uniform, i.e not dependent on the orientation and on the position of an edge.

"' .

ml m

R

b Figure 3: The rules of sucressful initial routing. These rules can be expressed in terms of the cost function r~e~nition. The maze algorithm guarantees finding a ,~rr~nirnum-eost p a t h interconnecting two vertices (or suhgraphs) of our grid graph model. The total cost of a path is computed as the sum of the cost increments azs~ciated with the edges forming the path. That is, if p is n p a t h consisting of the chain of edges el, ez, ..., ek, and ci is a nonnegative cost increment associated with edge ei, then the total cost of the path p is ~i=x k cl. The actual value of a cost increment may depend on the path bSstory [3]. If an incremental cost function is based on a ~ s t o r y of n edges, so ci = f(ei, ei-l, ..., el-n-l), then the function is said to be n - h e r e d i t a r y . In order to avoid long metal wires parallel to polysilicon underpasses it is su[~cient to use a 1 - h e r e d i t a r y c o s t f u n c t i o n c/ -- f ( e i ) with different cost increments for metal layer edges oriented in the preferred direction and in the direction not preferred [5, 6,11]. The routing space generally contains regions with horizontal preferred direction and regions with vertical preferred direction. The

cost increments associated with thc polysiliconedges as

Figure 4: The path-cost computation. The penalty value of cost for the preferred direction ( M P + P E N ) or the penalty value of cost for the direction not preferred ( M n + P E N ) is employed if ei-t is a metal layer edge and there is the via edge emanating from the vertex which is common to ci and ei-1. Example is shown in Fig.5 where penalty P E N i = 6. Generally, tile value of P E N i depends on the topology (length) of the misused underpass. Let us note that different l-hereditary cost functions are traditionally used for routing on IC's and PCB's [5, 6, 7, 8, 11]. However, the employment of a 2hereditary cost function for this purpose was considered only theoretically [3, 5].

Strategy

M/ P ~

/

/v

of one and haft/ayer roofing

M.~

Figure 5: The path-cost computation.

5

Description of Experiments

We chose VUGAF700 gate array for the experimental comparison of the performance of various cost function definitions. This one custom layer CMOS gate array contains 46 I/O cells and 700 basic cells ar:~anged into 14 columns. Each column incorporates 25 pairs of basic cells. Each basic cell contains 4 transistors; in other words a 2-input NAND gate "covers" one basic cell. The polysilicon layer contains over 10,000 of underpasses of five different types (see Tab.l).

underpass U1 U2 U3 U4 U5

7980 312 1750 30 700

length number symbolic [grid steps] of vios penalty 3 2 PENI 4 2 PEN2 5 2 PEN3 7 2 PEN4 13 4 PENs

Table 1: The types of polysilicon underpasses. We chose three routing examples (see Tab.2). Each of them represents a certain class of real routing problems which can be characterized by the utilisatian of cells, by the number of nets, by the number of interconnected pins and by the number of links (two-pin connections).

421

The 2-hereditary cost function was described by the metal layer increments for the preferzed direct~a M p and for the direction M ~ not preferred, by the p o l y s i ~ layer increments P, by the via increments V and by the penalties PEN~,i = 1,2...5. The variety of possible c ~ t function definitions is enormous due to the fact that we can set the values of 9 parameters in a relatively wide range. However, only some of them seem to be rea~aab~e for the initial routing phase and some of them seem to be convenient for the optimization phase. Therefcce we prepared two experiments. E x p e r i m e n t ~:1 was devoted to the initial rou~ing phase. The completion ratio, or rather the number of unsuccessfuly routed links, was used as the performance measure. The Experiment # I should: ® confirm the importance of both rules of s u c c ~ f a l initial routing; e detect "good" cost function definlt~oas for the inb tlal routing phase. We set M P = 1. M s = 1, V = O , P = 1, P E N I = 3 , PEN2 = 4, PEN3 = 5, PEN4 = 7 and PEN5 = 13 as the basic t,a h e s of cost increments. The value of M ~ was changed in the range < 1,9 > during the experiment. The values of PENi were changed so that PENt was in the range < 0, 8 > and the values of PENi rer~ued proportional to the length of respective underpasses. E x p e r i m e n t ~ 2 was devoted to the optim/zation pha.~. The initial muting was performed with the "best" choice of muting rules for all three exampbs first. The completion phase was empbyed in order to reach 100% completion when necess~y. The "optim/zati~a" experiment we started with the same basic values of cost increments as in the Experiment #1. Howewer, the value of P was changed in the range < 1,9 > instead of the value of M r. The total length of polysilicon underpasses used for routing was exploited as the performance measm-~. All experiments has been performed on Logostar PC/386 computer (25 MHz clock) running under MS DOS.

example utilization number number number[ of cells of nets of pins of links [ #1184.0% #2 91.1% #3 98.4%

246 291 349

821 912 1070

Table 2: The routing examples.

575[ 621 721

6

Results and Discussion

The results of the E x p e r i m e n t :~1 are shown in Tab.3. It is quite clear that routing rules which do not use a penalty for a misuse of an underpass, i.e. such routing

M. Sew[t, .!. Schmidt

422

rules that PEN~ = O,i = 1,2...5, provide unacceptable results. Routing rules which do net respect routing direction priority on the metal layer, i.e such routing rules that M " = M p, provide poor completion ratio either. However, routing direction priority seems to be less important especially for relatively simple routing examples. We can conclude that the advantages of 2h e r e d i t a r y cost function were confirmed.

range < 5, 9 > and the choice of PEN1 in the range of < 4, 8 > provided tha~ M p = 1, M '~ = 1, and V = 0.

PEN! 1

P The choice of the "best" initial routing rules is rather complicated because the optimum is fiat (see Tab.3). According to the results of the experimen{, the range < 4,8 > for P E N t and the range < 3,7 > for M ~ seems to be reasonable provided that PEN1 > M ~, M p = 1, V = 0 and P = 1. Let us note that a good choice of routing rules enables to reach the average completion ratio over 99.9%. We were interested in other performance measures too, namely in the running time and in the total length of underpasses used for routing. Generally, the dependance of these measuress on the cost function definition has the same character, i.e. the running time and the total length of underpasses used for routing reaches the lowest value when the completion ratio is h~ghest.

1

3 M~ 5 7 9

0 i78.3 70.3 68.7 69.7 62.0

2 16.0 3.3 4.0 4.0 5.3

4 15.3 0.3 2.7 4.0 4.3

6 17.7 0.3 0.3 2.7 4.7

17.01 0.3 1.0 0.7 3.7

Table 3: The comparison of routing rules for the initial ,-outing phase. The table contains the average numbers of unauccessfuly routed links for different values of M " and P E N i ; M r'= 1, V = O, P = 1. The results of the E x p e r i m e n t # 2 are shown in Tab.4. The ~nitial routing was done with the following parameters: M p = 1, M n = 3, V = O, P = 1, PEN1 = 6 , P E N 2 = 8, PEN3 = 10, PEN4 = 14 and P E N s = 26. The completion procedure had to be employed in the case of Example # 3 because one link was nfissing. It is quite clear that the total length of polysilicon underpasses used for routing can be decreased substantially when the optimization routine is employed with a proper definition of the routing rules. However, the optimum is rather flat (see Tab.4). According to the results of the experiment, we can reccommend the choice of P in the

3 5 7 9

0

2

+69.6% +75.5% +77.8% +79.3% +83.5%

-12.8% -23.9% -27.2% -26.3% -25.7%

4

6

8

-12.4% -12.1% -11.8% -26.0% -25.8% -26.0% -28.40A - 2 8 . 5 ~ -28.3°~ -27.90~ - 2 8 . 1 ~ -28.50~ -27.6% - 2 7 . 9 ~ -28.8~'~

Table 4: The comparison of routing rules for the optimization phase. The table contains the average change of the length of polysilicon ande~Imsses used for routing for different values of P and PENi; M p = 1, M" = 1, V=0. We were interested in other performance measures too. Typical results of the routing strategy described are shown in Tab.5.

U

Example # 1 IRP OP Example # 2 IRP OP Example # 3 IRP CP OP

I missin9 links

A! wires

PolySi underpasses

num. of vias

r~nning time [sec]

0 0

14673 17263

4621 3268

2351 1534

267 320

0 0

14307 18588

7963 5309

3797 2401

303 355

1 0 0

20513 10956 5012 20710 11057 5055 25071 8284 3773

383 4 438

Table 5: The typical results of routing. IRP - initial routing phase; CP - completion phase; OP - optimization phase.

7

Conclusions

The strategy of one-an-half layer routing described in this paper is based on a maze-type path finding algorithm, on a 2-hereditary cost function and on a general gridgraph model of a routing space. This strategy can be easily adapted to more complex routing environments consisting of several predefined layers and several custom

Strategy of one and half layer rout'rig

layers. A designer has three powerful tools enabling him to influence the overall routing performance: • Net ordering which allowes to express routing priorities. ® 2-hereditary cost function which allowes to express a broad spectrum of routing rules. • Grid-graph model which allowes to describe a routing space in detail. The strategy described was employed in F U G A S (FUlly automated Gate Array layout System) developed at the Czech Technical University of Prague. FUGAS was implemented in the Pascal programming language on VAX and IBM PC computers. Maze-type path finding algorithms are known for long running times and large memory requirements. Practical experience has shown that these disadvantages can be suppressed by meticulous code design and careful data structure choice [5,14]. On the other hand, maze touters are able to produce complex routing patterns exploiting internal space of cells. This feature is extremely convenient for routing on gate arrays with one custom layer because of their complicated internal structure and generally poor wiribility. The net oriented methods work in a one-connection-ata-time mode. The solution depends on the order in which nets are attempted. Either an unwise ordering or unforeseen wire patterns could cause routing failure. Therefore, net-oriented routing is not generally regarded us the best method for high density chips. However, practical experience and many experiments have shown that a simple strategy based on proper ordering, careful choice of a cost function and a simple rip-up-and-reroute technique can provide good routing resultseven for high density chips.

Acknowledgments We thank Z.MuzikA[ and Z.Fri§, who took part in the implementation of a production version of FUGAS, and with whom we have enjoyed close collaboration.

423

References [1] Burstein,M.: Channel Routing. In "Layout Design and Verification" (ed.T.Ohtsuki), EIsev~r, 1 ~ . [2] Kuh,E.S. and Marek-Sadowska,M.: Global Routing. In "Layout Design and Verification" (ed.T.Ohtsuki), Elsevier, 1986. [3] Lee,C.Y.: An Algorithm for Path Connections and its Application. IRE Trans. Electron. Computers, EC-10, 1961, pp 346-365. [4] Moore, E.F.: The Shortest Path Through a Maze. Annals of the Harward Computation Laboratory, 30, 1959, pp 285-292. [5l Serv[t,M.: Routing on Integrated Circuits and Printed Circuit Boards (in Czech). ~SVTS FEL Publishers, 1988. [6] Ohtsuki,T.: Maze-Rtmniag and Line-Search Algorithms. In "Layout Design and Ver~cation" (ed. T.Ohtsuki), Elsevier,1986. [7] Hoel,J.l~.: Some Variations of Lees Algnrithn~ IEEE Trans. on Computers, C-25, 1976, pp 19-24. [8] Servit,M. and Schmidt,J.: Expe.dments wlth Routing on Printed Circuit Boards. Computer Aided .D~ sign, 12, 1980, pp 231-234. [9] Song,J.N. and Cheu,Y.K.: An Algorithm for One and Half Layer Channel Rou~ing. 22nd D A Conf. Proc., 1985, pp 131-136. [I0] Servlt,M.: Heuristic Algorithms for R~tilinear Steiner Trees. Digital Processes, 7, 1981, pp 21-32. [II] Rubin,F.: A Comparison nfWir~ Spreading Metrics for Printed Circuit boards. J. of Design Automation and Fault-Tolerant Computing, 2,1978, pp 231-239. [12] Servit,M.: Minimizing the Number of ~eedthroughs in Two-Layer Printed Boards. Digital Processes, 3, 1977, pp 177-183. [13] Sadowska,M.: An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. IEEE Trans. on Computer-Aided Design, CAD-3, 1984, pp 184-190. [14] Servit,M.: Routing on Gate Arrays with One Custom InterconnectionLayer. Custom Circuits Conference Proc., Hungary, 1991 (to be published).