Studies of deep-level defects at III–V heterointerfaces

MATERIALS SCIENCE& ENBIEEIglIG ELSEVIER

Materials Science and Engineering B28 (1994) 387-392

B

Studies of deep-level defects at III-V heterointerfaces P. Krispin Paul-Drude-Institut fiir Festkgrperelectronik, Hausvogteiplatz 5- 7, D- 10117 Berlin, Germany

Abstract The results of recent deep-level investigations at III-V heterointerfaces are briefly reviewed. In particular, electronic states in n-type GaAs/AIGaAs heterojunctions, grown by molecular beam epitaxy, are studied by deep-level transient spectroscopy. In the A1 composition range 0.25-1.00, a series of well-defined deep levels is found which accumulates on the AIGaAs side of the inverted heterointerface (GaAs grown on AIGaAs). The series of levels originates from intrinsic defects associated with arsenic vacancies. The enhanced appearance of intrinsic defects at the inverted GaAs/AIGaAs interface provides new information on the microscopic processes involved in growing strained AIGaAs layers and in gettering impurities at heterointerfaces.

Keywords: AIGaAs; Electron states; Heterostructures; Molecular and atom beam epitaxy

1. Introduction

For the operation of heterojunction-based semiconductor devices, e.g. quantum-well lasers, tunnelling diodes, heterojunction bipolar and modulation-doped field effect transistors and, in general, strained-layer structures, the interface between the semiconducting materials is of essential importance. In addition to the structural perfection of the interface (abruptness of composition, smoothness), electronic states at heterointerfaces can severely affect the properties of heterostructures. Whereas the individual layers of heterostructures can be grown nearly defect free by modern epitaxial growth techniques, electron and hole traps often accumulate at heterointerfaces. Recently, electronic states, i,e. genuine interface states as well as defect-associated deep levels in the adjacent bulk material, have attracted much attention due to their impact on the performance of semiconductor heterostructure devices. Densities of fixed charges as high as 1011 cm -2 have been detected at GaAs/AIGaAs [1-5], InP/InGaAs [6-8], GaAs/InGaAs [9, 10] and InAIAs/InGaAs [11] interfaces by the capacitance/voltage ( C/V ) technique or admittance spectroscopy. Moreover, deep levels which accumulate at GaAs/A1GaAs [1, 2, 12-14], InP/ InGaAs [6, 15, 16] and GaAs/InGaAs [17] interfaces have been observed by deep-level transient spectroscopy (DLTS)[18]. 0921-5107/94/$7.00 © 1994 - Elsevier Science S.A. All rights reserved SSDI 0921-5107(94)00701-D

Considering, in particular, the GaAs/A1GaAs interface grown by molecular beam epitaxy (MBE), electronic states at interfaces were identifed as the main non-radiative recombination centres in heterostructures [19-23]. Their influence on the threshold current of laser diodes was demonstrated [12, 14]. Furthermore, it was found by secondary-ion mass spectrometry (SIMS) that impurities such as oxygen are piled up at GaAs/A1GaAs heterointerfaces [24, 25]. Therefore, it has frequently been supposed that the electronic states at the GaAs/AIGaAs interface are mainly connected with the incorporation of impurities. However, there is no direct experimental evidence so far to indicate that the dominant electronic states at GaAs/ A1GaAs interfaces originate from impurities. For A1 mole fractions below 0.4, it is well known that the normal interface (AIGaAs grown on GaAs) is nearly perfect as far as the electronic properties are concerned. A remarkable density of interracial charge is usually found at the inverted interface (GaAs grown on A1GaAs) [1-4]. In order to investigate the distribution of defect-related electronic states across MBE-grown GaAs/AIGaAs interfaces, n-type heterojunctions were studied by DLTS [1, 12, 13]. However, the depth profiles of deep levels at the interfaces remain controversial. McAfee et al. [12] and Okumura et al. [1] reported electron traps at 0.66 eV and 0.70 eV localized near the inverted interface. As et al. [13] observed the accumulation of several deep

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MaterialsScience and Engineering B28 (1994) AS'7-3~)2

levels in the AIGaAs layer near the normal interface. As for the other III-V heterostructures, there are only speculations about the origin of all of these interfacial electronic states. It is the aim of this paper to consider in detail the single GaAs/AIGaAs interface at various compositions. We discuss the results of C / V and DLTS measurements performed on MBE-grown GaAs/ A1GaAs heterojunctions.

where a n is the capture cross-section of the deep level for electrons, t,~h is the thermal velocity of electrons in the conduction band, N~. is the effective density of states of the conduction band, k is Boltzmann's constant and T is the temperature. Plotting ln(e,1/T ~) vs. 1/7, the thermal activation energy E~h and the capture cross-section a, of the deep level can be obtained. If the electronic capture process is also thermally activated, the energy E,h is the sum of the true deep-level energy E, and the activation energy E,, for the capture process.

2. Experimental details Comparable growth conditions were used for the specially designed heterostructures. A series of silicondoped GaAs/A1GaAs heterojunctions with AI mole fractions ranging from 0.25 to 1.00 was grown by conventional MBE on (001) substrates. The various heterointerfaces were produced at the same substrate temperature of 610 °C without interrupting the growth. The temperature of the Si cell was kept constant during the growth of the heterojunctions and resulted in an apparent carrier concentration of about 1 x 1017 cm-3 in the GaAs layer. The thickness of the AIGaAs layers was always below the critical thickness for lattice relaxation and chosen in such a way that the space charge region of a metal-semiconductor contact or a p+-n junction could be shifted through the interface by the applied bias. Typically, the heterostructure consisted of an n-type AIGaAs layer embedded in n-type GaAs layers. MBEgrown GaAs p +-n junctions, Hg probes or vacuumdeposited AI dots on the GaAs top layer were applied as contacts for the C / V and DLTS measurements. A DLTS system based on a 1 MHz capacitance bridge and a lock-in integrator was employed [26]. Negative DLTS signals were observed which are linked with the occurrence of electron traps in n-type material. Depth profiles of the deep-level concentrations across the heterointerface were measured using the double-correlation DLTS (DDLTS) method [27]. The depth was calculated from the capacitance C. Since the DLTS response A C/C originates from the region where the Fermi level E v crosses the deep level E t, the depth has to be corrected by the distance ). for every deep level according to [13] 2 = [2eeo(Ev- Et)/e2Ncv] '/2

(1)

where ee 0 is the dielectric constant, e is the elementary charge and Nov is the apparent carrier concentration. The thermal activation energies Eth of electron traps were determined from the thermal emission rate e,, for electrons from the deep level into the conduction band [18] e n = anVth N c e x p ( - E,h/kT )

(2)

3. Results and discussion In this section, we present results on GaAs/A1As heterojunctions in detail, because their properties are typical of the GaAs/AIGaAs interface over the entire composition range. The compositional dependence of the deep-level data is discussed in Section 3.3.

3.1. Enhanced depletion of carriers at the inverted GaAs/AlAs interface

Characteristic depth profiles of the apparent electron concentration Nov measured at room temperature by the C / V method are shown in Fig. 1 for the normal and inverted GaAs/AIAs interface of the same wafer. The applied biases and positions of the interfaces are indicated. The normal interface can be investigated after appropriate recess etching. It is clearly seen from Fig. l(a) that there is a carrier accumulation on the GaAs side of the normal interface. On the AlAs side, a depletion region is observed, from which the interfacial charge density is estimated to be below 2 x 1()~J cm-2. Around the inverted interface, located at 200 nm in the as-grown sample (Fig. l(b)), the depletion region is drastically enlarged and the accumulation of carriers on the GaAs side is missing. It yields a density of fixed charges of about 1012 cm -2. Apparently, a remarkably large number of acceptor-like defects occurs at this interface. A further indication for a high density of electronic states at the inverted interface is the bump in the profile at 275 nm in Fig. l(b), which originates from the additional capacitance contribution of deep states at the inverted interface (see Ref. [7]). If the AI content is decreased on the AIGaAs side of the heterointerface, the interfacial charge density is generally reduced at the normal and inverted interface. In this case, the accumulation of carriers on the GaAs side may be observed not only at the normal, but also at the inverted GaAs/AIGaAs interface.

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3.2. Deep levels in n-type GaAs/AlAs heterojunctions

-3.0V, (2) - 3.0 V/ - 2.0 V, (3) - 2.0 V/ -1.0 V, (4) -1.0V/ 0.5 V, (5) - 0.3 V/+ 0.1 V. Curve 2 in Fig. 2(a) has been shifted for clarity.

For the GaAs/AIAs sample studied in Fig. l(b), the DLTS signal A C/C is shown in Fig. 2 as a fraction of temperature. Various bias conditions correspond to different depths near the inverted GaAs/AIAs interface. A sequence of well-defined peaks labelled p0 to p6 is revealed. At sufficiently high reverse bias (Fig. 2(a)), the peaks p2 (205 K), p5 (385 K) and p6 (above 400 K) are observed. It should be noted that the peak at 400 K in curve 1 originates from a superposition of the levels p5 and p6. Lowering the reverse bias (Fig. 2(b)), the levels p0 (80 K), pl (150 K), p3 (275 K) and p4 (335 K) appear and disappear again. Apparently, the peak height which is linked to the deep-level concentration becomes largest at a certain bias for every electron trap. In the AlAs layer (curve 1 in Fig. 2(a)), the traps p0, pl, p3 and p4 are not detected, whereas a small amount of the level p2 is always found. The level p2 is the well-known DX centre [28] and originates from the deep Si donor. Close to the inverted heterointerface, the levels p3 and p4 are dominant and have nearly the same concentrations (Fig. 2(b)). Characteristic depth profiles of the levels p3 and p4 across the inverted GaAs/AIAs interface measured by

the DDLTS technique [27] are displayed in Fig. 3. The bias (bottom axis) was converted into depth (top axis) via the capacitance which was measured at 275 K and 335 K for the traps p3 and p4 respectively. Both traps are concentrated at a certain depth marked by an arrow. Because the DLTS peak temperatures for these two levels are close together (see Fig. 2(b)), the peaks of the profiles are asymmetrically broadened. The peak height is the same for both levels. Taking into account the shift in depth due to the ;t effect (see Eq. (1)), it can be concluded from the peak positions of the depth profiles in Fig. 3 that the deep levels p3 and p4 accumulate directly at the GaAs/AIAs interface. From Fig. 3(b), it can be further estimated that at least the signal of the level p4 disappears at a distance of about 25 nm from the interface. The halfwidth of the peak matches the Debye length of about 12 nm, the ultimate resolution limit of the depth profile. The level energies E t estimated from the ;t values in Fig. 3 agree with the thermal activation energies Eth determined by the emission rate e n. Similar depth profiles were also obtained for the other levels in

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3.3. Origin of deep levels at inverted GaAs/AIGaAs interfaces In samples with inverted GaAs/AIGaAs interfaces, we find for all AI mole fractions distinct signals and bias-dependent peak heights. There is always a bias range at which the deep-level concentrations are largest. In order to compare the DLTS results for the various GaAs/A1GaAs heterojunctions, we use the DLTS peak temperature at a fixed emission rate as the signature of a deep level (see Eq. (2)). Our data on the discrete deep levels p3-p6 are summarized in Fig. 4 as filled circles. The open symbols originate from investigations on the well-known electron traps E l - E 4 which can be induced in epitaxial AIGaAs layers by high-energy electron irradiation [29-31]. Previous results of other

workers [1, 12, 13] on interface-related deep levels in GaAs/AIGaAs heterojunctions are also included in Fig. 4 and are in reasonable accordance with our data. Owing to the relatively small spread of the data points, the chemical shift of the DLTS peak temperature is clearly seen for the levels p3-p6. Each level exhibits a specific variation of the peak temperature vs. the AI mole fraction. This group of four levels is typical of the inverted GaAs/AIGaAs interface over the entire composition range. The thermal activation energies E~h of the levels p3-p6 are summarized in Table 1. The sharp levels of p3-p6 originate from isolated defects. It is evident from Fig. 4 that the DLTS peak temperatures of the levels p3-p6 agree within experimental error with those of the level sequence E 1-E4. Therefore we conclude that the deep levels p3, p4, p5 and p6 correspond to the traps E l , E2, E3 and E4 respectively. This conclusion is further supported by

P. Krispin /

MaterialsScience and Engineering B28 H 994) 387-392

the individual properties of the traps (activation energy, concentration, capture cross-section, etc.). It is commonly accepted [31] that the levels E l - E 4 originate from defects which involve an arsenic vacancy VA~.E1 and E2 are associated with two different charge states of the isolated vacancy VAs. The trap E 3 probably belongs to a defect pair consisting of an arsenic vacancy VA~and an interstitial arsenic atom Asi. The level E4 is thought to be a defect pair consisting of the vacancy WAsand the antisite defect ASGa,AI. 3.4. Segregation of native defects induced by Fermi-level pinning

Whereas the MBE-grown A1GaAs layers are free of the electron traps p3-p6, the VAs-related defects are concentrated on the AIGaAs side of the inverted interface. It is probable that the compressive stress favours the formation of vacancy-associated defects during growth of the AIGaAs layer. Since the deep levels are neither observed at the normal heterointerface nor inside the AIGaAs layer, we conclude that the intrinsic defects are formed during growth at the surface without being incorporated into the layer. Obviously, a segregation mechanism for intrinsic defects is working during growth of the n-type AIGaAs layer. We also find an accumulation of the same intrinsic defects in p+-n junctions of A1GaAs [32], i.e. if the growth of the n-type A1GaAs layer is terminated by a p-type A1GaAs layer instead of an n-type GaAs layer. Therefore we conclude that the intrinsic defects are "frozen in" at the position where the surface depletion region of the n-type AIGaAs layer is buried during growth. The mechanism which causes the VA~-related defects to segregate during growth is obviously connected with the electric field at the surface due to Fermi-level pinning. In n-type material, deep-level defects with donor-like character can be attracted to the surface due to the dipole interaction between the electrons in surface states and the positively charged defects, a mechanism which has been recently established for shallow-level dopants [33].

4. Conclusions (1) Strained AIGaAs layers grown by MBE are perfect with regard to the presence of the electron traps p3, p4, p5 and p6. There is, however, a thin layer of vacancies at the growth front which leads to an accumulation of VAs-relatd defects close to the inverted GaAs/AIGaAs interface and within the p +-n junction. The underlying microscopic process is also relevant for the formation of epitaxial Schottky barriers on A1GaAs

391

layers because the surface depletion region is similarly buried in this case. (2) The gettering effect of heterostructures and, in particular, the accumulation of impurities at the inverted GaAs/A1GaAs interface can be explained on the basis of our results. The incorporation of impurities is mainly controlled by the distribution of vacancyrelated defects which are localized at the AIGaAs surface during grOwth and at the inverted interface of GaAs/AIGaAs heterostructures. (3) The total number of electron traps found at the inverted GaAs/AIGaAs interface is not sufficient to explain the occurrence of about 10 L2 cm -2 acceptorlike defects. We believe that additional deep levels in the lower half of the AlAs band gap are caused by other VA~-related defects which may be observed in p-type heterojunctions.

Acknowledgments The author would like to thank R. Hey and H. Kostial for important contributions and H. Grahn and W. Ulrici for fruitful discussions and careful reading of the manuscript. The technical assistance of Ch. Dombrowski and M. Hrricke is greatly appreciated.

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