Study of charge storage behavior in metal-alumina-silicon dioxide-silicon(MAOS) field effect transistor

Solid-Store

Elr~~rmnic.~,

1974, Vol. 17, pp. 367-375.

Pergamon

Press.

Printedin GreatBritain

STUDY OF CHARGE STORAGE BEHAVIOR IN METAL-ALUMINA-SILICON DIOXIDESILICON(MAOS) FIELD EFFECT TRANSISTOR SHUICHI

SATO

and

TADANORI

Sony Corporation, Atsugi Plant, Semiconductor

YAMAGUCHI

Division, Atsugi-Shi, Kanagawa, Japan 243

(Received 22 June 1973; in revisedform 10 Augus? 1973) Abstract-The basic characteristics and charge storage behavior of metal-alumina-silicon dioxidesilicontMAOS) field effect transistors have been investigated as a function of the oxide thickness. The typical charge storage behaviors have also been measured on devices with SiO, films of 5OA and Al,O, films of 700A and the results are interpreted in terms of electron and hole transport processes across thin SiO, layer and electron injection from Al electrode by tunneling mechanism. In the MAOS structure, the shift of threshold voltage from initial state is within about 23 V and can be reversibly controlled, more than 106-times at least, by alternate electric fields under suitable stressing condition. It is considered that the charge storage time is practically infinite at room temperature and of the order of lo6 hr at 150°C. The failure behaviors of device parameters under the repeated field stressing and cycles can be also accounted for in terms of electron accumulation within Al,O, films and at interfaces between A&O, and SiO, films.

1. INTRODUCTION A

stable performance of field effect transistor which consists of multilayes dielectric films as a gate insulator has been the subject of extensive investigation. Recently, many investigations [ l- 181 have shown that double layer gate field effect transistors show the presence of instabilities resulting in hysteresis behavior of charge stored at the interfaces of the layers as a function of applied gate voltages. As the hysteresis behavior in useable for a memory, a number of new memory

have recently been reported such as MNOS[3-91, FAMOS[lO], MAS[ll], MAOS[12-161 and other structures[l7,18]. These devices can store an information as the nonvolatile memory associated with charge storage phenomena at interfaces of the multi insulator layers. These non-volatile charge storage devices are generally classified in two groups: one is not erasable by electric field and the other is electrically alterable type. In the MNOS memory, recently, the clearcut model [8,9] for deterioration has been discussed in details. A new electrically alterable non-volatile memory transistor has been developed by using the MAOS gate structure. The purpose of this paper is to investigate the transistor characteristics and basic charge storage behavior of the devices as a function of oxide thickness. In addition to these properties, the reliability and failure problems in

MAOS non-volatile memory transistor been discussed in details. 2.

have also

SAMPLE PREPARATION AND BASIC TRANSISTOR CHARACTERISTICS

The structure of the MAOS memory transistor described in this paper is essentially the same with that of a standard insulated gate field effect transistor, except that a silicon dioxide layer for the gate is replaced by a layer of chemically deposited alumina film (A&O,) of 700 A over the thermally oxidized thin silicon dioxide (SiO& of 5OA as shown in Fig. 1. The substrate material was 5-8 R-cm, p-type (lOO)-oriented silicon. Oxidation of gate oxide film. Thin gate oxide film of SOA was prepared by thermally oxidizing

devices

MNS[l],

SOURCE

THERMAL P-TYPE

DRAIN

G4TE

I

SILICON

SILICON

DIOXIDE(50~)

SUBSTRATE

5-Bn-cm,(lK%

Fig. 1. Schematic illustration of the metal(aluminum)alumina-silicon dioxide-silicon(MAOS) memory transistor structure. 367

368

SHUKHI SATOand TADANORI

YAMAGLJCHI

the silicon surface in the mixture of nitrogen gas: 3 l/min and dry oxygen gas, 90 cclmin at 900°C for 45-50 min including preheating. Aluminu

deposition

Nnd its physical properties.

Alumina film was chemically deposited by a method of hydrolysis of AK& with the reaction 2AlCl,, + 3C0, + 3H, *A&O, + 6HCL + 3C0. Preheating of sample before alumina film deposition was carried out in hydrogen gas of 850°C. Then, the alumina film was deposited at 850°C under the following gas how conditions using RF reactor furnace of 400 kHz. Carrier gas of hydrogen (Hz), 35 l/min, carbon dioxide (COZ), 400 ml/min and hydrogen gas saturated with AlCl, vapor by flowing through a heated AlCl, bath of 123”C, 7.5 ml/min. The growth rate of alumina film was 230 A/min in an average value. The thickness of 700 A was obtained by about 3 min reaction time. After deposition of the alumina film, samples were slowly cooled down to room temperature in the atmosphere of hydrogen gas. The index of refraction and the dielectric constant of the alumina film were II = 1.73 rt 0.01 and e.<= 9.6 - 9.8, respectively. According to the X-ray diffraction analysis, the structure of the alumina films was in good agreement with that of the y-phase structure. The film thickness of SiO, and A&O:, were measured by the method of ellipsometry. The samples were annealed in the dry oxygen gas for about 30 min after formation of double layers. The thick SiO, film of 1.4pm was also deposited by the usual chamical vapor reactions of silan and oxygen gas at the temperature of 480°C. Basic transistor charucteristics. Figure 2 shows a typical electric characteristic, i.e., source-drain current (I& vs source-drain voltage (V,,J and transconductance at 1 kHz(G,,,) vs gate voltage (V,) of n-channel enhancement type MAOS transistor with initial threshold voltage of about 4 V. The ratio, (W/L), of the channel width, W, and channel length, L, for this device is 20. The gate threshold voltage, parasitic field threshold voltage, breakdown voltage in source and drain junctions were measured as a function of oxide film thickness, and are shown in Fig. 3. (a), (b) and (c), respectively. In these experiments oxide thickness was controlled in the range of 30 - 3OOA for SiO, films and 700 - 17OOA for A1203, respectively. As shown in Fig. 3, initial gate threshold voltage and breakdown voltage in source and drain junctions on devices with SiO, film of 50 A and A&O, film of 700 A were 4 and 26 V, respectively.

SOURCE -DRAIN

VOUAGE

OR GATE VOLTAGECVOLTSI

Fig. 2. d.c. Characteristics of /V-channel enhancement type MAOS transistor. Typical properties -of I ,,_,,vs V,,_., and G,,, vs V(, on samples wjth SiO,(50 A) and A&O,(700 A).

In the n-chanel MAOS structure transistor, initial threshold voltage can be expressed as

where, QA(0) is the negative charges located at or near Si02-A&O3 interfaces; Qss is the positive charge of fast surface state located at SiO,-Si interfaces: 4.ks is the work function difference between metal and silicon; r#+ is the Fermi level; E,~, E~),~and E~ are dielectric permittivity of Si, SiOz and AIEOS, respectively; Qb is the bulk charge in Si. Using equation (1) and initial threshold voltage, interface charge density, N,( and Nss. corresponding to QA and Qss, were evaluated as N, : 4 X 10’” cmWL and N,s,s: 2 X 10” cm-“, respectively. 3. EXPERIMENTAL RESULTSANDDISCUSSION 3.1 Basic memory characteristics The main features of hysteresis characteristics, critical voltages, transfer speed of charge injection and physical mechanism of the storage behavior in MAOS memory transistor will be described.

Metal-alumina-silicon

dioxide-silicon

369

transistor

subjected to the gate voltage pulse duration of 5 set are shown in Fig. 4. Let us consider, for example, hysteresis behavior of the threshold voltage shifts of sample No. 1 when positive or negative pulse is applied to the gate under the condition that both source and drain electrodes are grounded. When positive voltage exceeding the critical voltages of 19 V was applied to the gate electrodes, the threshold voltage shifted linearly to the positive direction. Then, if negative gate voltage is applied after positive shift, threshold values will start to decrease. oxide thickness

E $0

” --

Y

”

g

‘.

P-TYPE SfUCON(100)~ 5-h-cm A1203 DEPOSIT; l35O”C GATE OXIDATION 9OO’C d:y 02 Si02: 50A

/‘/

/

I:::

:

; : ; : : ; : : : : ; : 500 xx!0 ~ 1500 AL UMINA THICKNESS(A)

0

: ;

: ; : 2000

(4

h \

FIELO OXIPE Al203=7OO(A) [_praFub~~;5-8n-cm

\

P-z \

Gate

14,um

VTH

\ -100

0

10

1000

100 SiO2 THICKNESS(i)

/ AX-

-N+-P Diode -M- Drain-Substrate (vG=vS=O(v)) P-TYPE Si Substrate 5-8h-cm) Al203 :700A

! ,::.-.I

100

: :.:..:.:

loo0

:

SiO2 THICKNESS& (c)

Fig. 3. Oxide thickness dependence of gate and parasitic threshold voltage and breakdown voltage of sourcedrain junction. (a) Threshold voltage as a function of alumina thickness with silicon dioxide thickness of 50 a. (b) Gate and parasitic threshold voltage as a function of silicon dioxide thickness with alumina thickness of 700 a. (c) Breakdown voltage as a function of gate silicon dioxide thickness with alumina layer of 700 A. Hysteresis characteristics of threshold voltage. Typical threshold voltage shifts from initial value and the hysteresis of MAOS transistor with various

SSE

Vol.

17 No.

4-D

M VOiTAGE(VOLTS)

’

50

Fig. 4. Detailed hysteresis behaviour of threshold voltage of MAOS memory transistors with Al electrodes. Note that vertical scale shows the shift from initial threshold voltage of 4 V. Voltage pulses with various heights but a constant duration of 5 set are applied to gate electrodes. Arrows indicate the sign of initial stressing voltage.

(b)

0”, 10:

GATE

As a result, threshold voltages can be controlled as the hysteresis loops: A + B + C + D + E + A process or A --, B + C + H -+ J + D + E + F + G + B process, corresponding to the heights and polarities of gate voltages. On the contrary, similar positive shifts of threshold voltage were also observed when negative gate voltages were applied to the as-grown device at the starting points. When gate voltages exceed some negative peak values at point P on each device, threshold voltage shifts finally in negative direction. This threshold voltage shift with the peak phenomena is only recognized in the first negative procedure, not in the second procedure. Similar hysteresis loops of threshold voltage in the devices (No. 2, 3 and 4) which consists of different film thickness were also observed. From these experimental results of hysteresis behavior of the threshold voltages, the charge storage mechanism in MAOS devices will be discussed in more details. It can be generally considered that these hysteresis behavior of thres-

SHLJICHI SA’TO and TADANOKI

370

hold voltage in the double insulated gate field effect transistors are caused by the carriers transported through insulator films and stored in the trapping centers located at or near interfaces. The physical mechanisms of carrier transport through insulator films may be mainly considered as follows: (1) direct tunneling across silicon dioxide layer, (2) Fowler-Nordheim tunneling through the barrier for silicon dioxide films, (3) charge transport due to the Pool-Frenkel type current, (4) Field enhanced charge transport associated with trapping centers inside oxide films. It can be seen from experimental results that threshold values vary linearly for both positive and negative gate voltages and can be shifted reversibly between two values by applying a gate voltage with appropriate amplitude, duration and polarity. As a matter of fact, positive shifts of threshold voltage will be considered to be caused by either charge accumulation or removal at or near silicon dioxide and alumina film interface responsible for the Fowler-Nordheim tunneling through the barrier of thin silicon dioxide. Because, for a given structure, thickness of underlying silicon dioxide films, d,,,, was chosen more than 50 A,. Assuming a model similar to the theory of Ross and Wallmark[4], threshold voltage shifts may be approximately expressed, under I’(; % I’(.,,,, as

Av,rt,(t)

=$

(Q.,(t) -Q,,(O))

(A +ln(Bt)),

(2)

where Q.l(t) and Q.,(O) are the total charges transferred at the time t of the applied gate pulse duration and at t = 0, respectively: N(X,,, 0) is concentration of filled trap states per unit volume at A&O,-SiO, interface at t = 0; rn,? is the electron effective mass and V,, is the effective magnitude of energy barrier; A and B are constants. Experimental results of hysteresis loops were in fairly good agreement with the theory of equation (2). On the contrary, positive shifts observed under negative bias voltages can be interpreted as follows: first the pile up of electrons injected from Al electrode into Al,O, films will occur, but further storage of electrons in A&O, under higher negative

YAMAGUCHI

bias does not take place. Under higher negative bias, the electric field for holes will exceed critical value at point P, then the hole storage only will occur so that the threshold voltage shifts in negative direction. This fact will imply that electrons can be also injected from Al electrode into the bulk region of AI,O,, films and holes are also emitted under higher negative bias voltages. The breakdown voltage dependence of source and drain junction under the condition of charge storage were also measured. When gate electrode was grounded, breakdown voltages indicated a tendency of linear decrease for those before charge storage, namely, they varied from 24 V at initial state to 10 V at threshold voltages of 20 V, This fact will also imply that the decrease of breakdown voltages is due to a negative charge accumulation at the junction surfaces. Namely, accumulation of injected negative charges tends to convert the surface potential from p-type to /If-type and causes the decrease of breakdown voltage. Criticrri ~dttrgr NIZ~ its oxide thicknrss tb prnd~~~rc~c~. From experimental values of critical voltages in the different samples as shown in Fig. 4, critical electric fields in positive or negative gate voltage and at the peak point in negative gate voltage direction were calculated. For a given structure, critical fields for silicon dioxide and alumina films were 5.5 6.0 x IO” V/cm and 2.4 x 10"V/cm in positive direction and 2.2 4.3 _ 4.5X IO” V/cm and I.7 . 1.8X 10” V/cm in negative direction, respectively. Critical electric fields for silicon dioxide and alumina films at the peak point were 7.2 7.7 x IO” V/cm and 2.2 -2.6 X 10” V/cm, respectively. It is asserted that the theoretical minimum critical fields [4] required for tunneling would be approximately 6 -_ 8 x 10” V/cm and these values are in fairly good agreement with the obtained results. Oxide thickness dependence of critical voltages can be tentatively assumed as the following

= 6x 10”k(d~,,\-+0~4~,l) (V),

(3)

where k is a constant; E,,., (.,<, is the critical fields for the gate oxide. We measured the oxide thickness dependence of critical voltage under positive bias in order to compare the tentative model with the experimental values for the case of silicon dioxide of 50 A and alumina film of 700 A. These results obtained are shown in Fig. 5 and are in good

Metal-alumina-silicon

80I

x

Measurement

PULSE

(a)

THICKNESS&

agreement with this tentative model. In this comparison, k-value of 0.8 and EoxCR, of 6 X IO6 V/cm evaluated at the each point of film thickness of silicon dioxide of 50 A and alumina film of 700 A were also used in equation (3) respectively. dependence

of threshold

voltage

phenomena

of

storage

Y

E b 6 >

Al203=700(A)

20

s,o,=50&)

shift.

The dependence of threshold voltage shifts on the applied pulse duration in devices with the silicon dioxide of 50 A and alumina film of 700 A are shown in Fig. 6, with the positive gate pulse amplitude taken as a parameter. The Fig. 6 (a) shows that the positive shift of threshold voltage varies as the logarithm of the applied gate pulse duration. The results obtained also supports that the threshold voltage shifts as described above may be explained by the model presented by the equation (2). The negative threshold voltage shift of a device under the application of negative voltages after a positive shift is shown in Fig. 6(b). In this procedure, empty electron traps located in or near alumina film under Al electrodes will be charged by electrons injected from electrodes before discharge process of stored electron from traps at silicon dioxide-alumina interface to the silicon conduction band. Therefore, the time dependence of threshold shifts under the negative pulse appiication is not represented by straight lines. Discharging

WIDTH&EC.)

1500

Fig. 5. Critical voltage as a function of oxide thickness.

Time

371

transistor

Theory

OL OXI DE

dioxide-silicon

charge.

Discharging characteristics of MAOS memory transistors with silicon dioxide of 50 A and alumina film of 700 A were measured. At the starting point of measurement, a positive bias of 38 V was applied to all samples at room temperature to shift the threshold voltages to 16.5 V in the positive direction. After the shift of threshold voltage,

PULSE

WIDTH(SEC)

(b) Fig. 6. Time dependence of threshold voltage shift on MAOS_memory transistor with SiO, of 50 A and Al,O,, of 700 A subjected to various pulse heights and durations. (a) A case of positive pulse stressing for initial states. (b) A case of negative pulse stressing for storaged state.

gate, source and drain electrodes were grounded to the earth potential. Then, samples were stored in various temperature of 22, 60, 100 and 150°C respectively. Figure 7(a) shows the decreasing of threshold voltage with time. Threshold voltage on each device was measured at the appointed time at room temperature. It was found that there are two states of discharging phenomena. One is a region of steep falling of threshold shift within about 30 min and the other is a region of slow falling with long decay time. Extraporating the slope of decay curve with the long time constatnt, the effective memory storage time is estimated to be of the order of lo6 hr or more at 150°C and almost infinite at room temperature. Slow discharging mechanism may be speculated as the following. If most of the injected electrons are captured by deep trapping center located near or at the interface region be-

312

SHUICHI SATO and TADANORI

YAMAGUCHI

speed after the negative bias stressing is faster than that after positive stressing. On the basis of the results, the following model of charge transport is proposed. If the space charges inside insulator films are described by charge density Q,, which are assumed to be located at infinitely thin SiO,A&O, interface, barrier heights of alumina; V,,,I,,q and of silicon dioxide: 1/,,, are approximately given by

VAI,,,,= and v,,,,- =

(b) Fig. 7. Discharge of stored charges on MAOS memory transistors. (a) Discharge in temperature of 22, 60, 100 and 15O”C, after threshold voltages shifted to 16.5 V under the positive bias of 38 V in height and 5 set in duration. (b) Behavior of fast discharge under no-bias, negative and positive bias of I5 V.

tween the silicon dioxide and alumina films, trapping centers will be filled up and become stable states. Consequently, the physical origin of slow discharge will be the Pool-Frenkel current through the oxide films. Because, when samples were heated in elevating temperature, discharging speed become faster than that of room temperature. The fast, small shift may be due to the dipole polarization of alumina films or due to the fast discharge of accumulated electrons which would spread out into the bulk region through trapping centers in alumina or silicon dioxide. In order to investigate these fast discharging behavior in more detail, the time dependence of threshold voltage was measured under no bias, as well as under positive or negative bias stressing of 15 V, as shown in Fig. 7(b). It is shown that discharging

Q, + Cu.,C’,.

cc,., +c , 01- C Iv,, cm + c,

(4)

(5)

respectively, where, C., and C,, are capacitances for alumina and silicon dioxide films, respectively. The model described above is subject to the following simplifying assumptions: (1) silicon surface is sufficiently accumulated, (2) space charge associated with electrons injected from Al electrode into A&O,, is not considered, (3) space charge associated with trapped electrons inside thin SiO, is not considered, (4) electric field within SiO, and A&O, films are uniform. Let us consider, for example, samples with the initial threshold voltages of 20 V under negative bias stressing. In this case, barrier heights calculated by equations (4) and (5) are IJ’,,,~= 5.3V These barrier and VA1,o.,= 9.6V, respectively. heights correspond to the electric field of E,,, = 1 x 107V/cm and _EAIZo, = I.4 X lO”V/cm, respectively. On the other hand, in case of positive bias stressing and same threshold voltages of 2OV, the barrier heights are V,,.,- = 0.7V, !& = I .5 X 10” V/cm and VA12,,:,= 15.7V, E,A120:, = 2.2 X IO”V/cm, respectively. Therefore, in negative stressing case, the actual electric fields across silicon dioxide films exceed the critical fields of 6 X 10” V/cm. The accumulated electrons at the SiO,-A&O:, interface can be transported for a short time from SiO,-Al,O,, interface to silicon conduction band through thin silicon dioxide layer by the FowlerNordheim tunneling process caused by the extra fields across the thin SiO, film. As a result, electric fields across the SiO, film decreases from 1 X 10’ V/cm to below 8 x 10” V/cm after biasing and then the threshold voltage does not vary with time. Since the electric field across SiO, films for nobias and positive bias stressing is less than 6 x 10” V/cm, most electrons accumulated at interfaces can not be transported. It may be concluded from these experiments that discharge of the stored

373

Metal-alumina-silicon dioxide-silicon transistor electron at the interface trsps is predominantly due to the tunneling conduction from traps to silicon conduction band rather than that from traps to alumina conduction band. The density of electrons injected from silicon conduction band into traps through thin SiO, can be estimated as follows: After positive shift of threshold voltages, the condition V,, = 0 can be realized under a certain positive gate voltage, V,. Assuming that the applied gate voltage that realizes V,, = 0 is equal to the threshold voltage, the stored surface electron density may be calculated approximately by using Q, - CAV, = 0. As one example, the stored electron density at SiO,-A&O, interfaces was calculated to be about 1.5 x lOI cmm2. Moreover, if most stored charges are located at the SiO,-Al,O, interfaces, the internal fields across thin SiO, films may be estimated as 1 x IO7V/cm. If this value exceeds the critical field of 6 - 8 X lo6 V/cm which is considered to be necessary for tunneling in this case, the stored electrons would discharge from interfaces to silicon conduction band. As can be seen in Fig. 7(b), the initial threshold voltage of 20 V decreases rapidly to about 12 - 13 V, and after this initial decrease, remains almost constant. The electric field at this point for SiOs films was about 8 X lo6 V/cm and was in good agreement with the electric field in other experiments and with the field expected from Fowler-Nordheim tunneling theory. In cases of no-bias and positive bias stressing by 20 V in Fig. 7(b), small shifts of threshold voltage were also recognized. In each case, the internal electric fields at initial state seems to exceed the critical field and they reduced to about 6 X 106V/cm. It may be concluded through experimental results mentioned above that the small shifts of threshold voltage would be caused by the Fowler-Nordheim tunneling effects rather than the dipole polarization of alumina films. 3.2 Memory cycle dependence

of transconductance

and gate capacitance

The change of transconductance and gate capacitance under repeated memory writing and erasing tests on different MAOS memory transistors having film thickness of silicon dioxide of 50 A and alumina of 700 A were observed and the result is shown in Fig. 8. The transconductance and the gate capacitance values described here were observed under the condition of the source and drain bias of 5 V and 1 MHz, resnectivelv. The voltage used - nulse _

here is 35 V for writing and - 40 V for erasing with duration of 100 msec. Figure 8(a) indicates that the transconductance

zcG-%

V/R!TE, VG=*35(V) t=lOO(msec)

.

ER-?SF,VG=++O(V) t=lOO(msec)

II i

Al203 SIO2 5

0

10 GATE

=700(A) ‘50(A)

+--&+-

I5

VOLTAGE(VOLTS) (a)

LL

GATE VOLTAGE

0

5 GATE

10

15

20

VOLTAGE(VOLTS)

(b)

ok-

GATE

VOLTAGE(VOLTS)

Cc)

Fig. 8. Memory repeat cycle dependence of transconductance at 1 kHz and gate capacitance at 1MHz in MAOS memory transistors. (a) Alternate cycle dependence of transconductance and gate capacitance for writing (positive bias stressing) and erasing (negative bias stressing) repeats. (b) Repeat cycle dependence of transconductance and gate capacitance for the writing repeat only. (c) Repeat cycle dependence of transconductance and gate capacitance for the erasing repeat only.

374

SHUICHI

SATO and TADANORI

reduces to almost half value of the initial one after IO’ cycles. At the same time, it is recognized that the slope of C-P’ curve changes with increasing writing-erasing repeat cycles. In order to search whether the failure process responsible for the reduction of transconductance and the change of C-V characteristics corresponds to writing process or erasing process, additional experiments were also performed by using only the writing cycles or only the erasing cycles, separately. These results are shown in Fig. 8(b) and Fig. 8(c). A tendency is indicated that the reduction of transconductance and the drastic changes in the C-V curve of gate capacitance for erasing cycles are much larger than those for writing cycles. However, threshold voltage shifts in each case indicated a similar tendency of increase in the positive direction. From these facts, it should be considered that the reduction of transconductance and the change of C-V characteristics will be mostly caused by the erase cycles in which the electron transport process results from traps to silicon conduction band through the barrier of thin silicon dioxide or from metal electrode to traps located inside alumina films. Furthermore, it is more likely to be true that these degradation and failure mechanism of MAOS memory transistor are caused by the increment of fast surface states which are probably also created in the oxide layer or near the SiO,-Si interfaces during erasing cycles. As a result, it may be concluded from the evidence mentioned above that extreme small island with high threshold voltage responsible for the creation of surface states will be created and grow up as small island inside the actual gate area with increasing the erasing cycles. Therefore, the actual gate area will be reduced with the cycle times. Recently, Woods and Tuska[X] and Keshavan and Moore[9] reported that degradation and failure mechanism in MNOS memory devices are correlated with oxide breakdown and the resulting creation of fast surface states inside the oxide or at SiO,-Si interface. Comparing a tendency of the degradation of MAOS memory devices with that of MNOS memory devices, it will be considered from these experimental results that the failure mechanisms of MAOS memory are almost analogous to these of MNOS memory. At the same time, it will be considered that this electron capture mechanism inside silicon dioxide films is analogous to the physical model in FAMOS type [ lo] or electron injected type memory device reported by many authors [ 16.171.

3.3

YAMAGUCHI

Memory

cycle

dependence

of’

threshold

voltage

Figure 9 shows the threshold voltage as a function of memory cycle times. The height and duration of pulse are 35 V for writing and -40 V for erasing and 100 msec., respectively. At the initial state, threshold voltages for erased “0 STATE”, and written “1 STATE”, were 4.2 and 15,2V, respectively. With the writing and erasing cycles, threshold voltages from both states increased linearly with the logarithm of cycle numbers and shifted to 7.7 and 17.2 V, respectively after 10” cycles. The deviation of threshold voltages before and after repeat cycles of lo4 was about 3.5 V for “0 STATE” and 2 V for “I STATE”, respectively. It is shown that the increase of threshold voltages for “0 STATE” is larger than that for “ 1 STATE”.

G

wr,te v~=*35(v).loo( msec: Erase V~=-40(vilOO(msec)

ii2 2 3

10

9

i 1

,4---T&7 ; iiiii/ : :i~r:~ 1000 : 10000 ! MEMORY CYCLES

Fig. 9. Memory cycle dependence of threshold for “1” state and “0" state.

voltage

As interpreted before, the electron injection inside alumina from metal electrodes and the creation of fast surface state at or near SiO,-Si interfaces are predominant reason for this fact. After IO4 repeat cycles, samples were annealed for 30 min at 200°C. Then, threshold voltages tend to recover to the initial level for each device. This fact can also be explained as that the captured electrons inside alumina and silicon dioxide are thermally emitted to the conduction band or the oxide films and the traps located inside the oxide films become empty. At the same time, we found that the fast surface states were annealed out and the highly distorted C-V curves returned to their original

4.

The sistors

CONCLUSION

AND SUMMARY

basic d.c. parameters on were observed as a function

MAOS tranof gate oxide

Metal-alumina-silicon

thickness and conditions. It was confirmed that the charge storage behavior in MAOS structure can be interpreted in terms of injection behaviors of electrons from silicon conduction band to trapping centers under the positive bias stressing or holes from silicon valence band to trapping centers under the negative bias stressing by the Fowler-Nordheim tunneling through the barrier of silicon dioxide layer. At the same time, negative charge injection from Al electrodes was also measured under the negative bias stressing in the range of from 4,3 - 4.5 x lo6 V/cm to 7.2 7.7 x lo6 V/cm for SiO, layer and of from 1.7 1.8 x lo6 V/cm for A&O, layer. When the electric fields under negative bias stressing exceed 7.2 7.7 x lo6 V/cm for SiO, layer and 2.2 - 2.6 X lo6 V/cm for Al,O, layer, the positive charge injection by holes occurs so that threshold voltages shift to the values corresponding to large negative bias stressing. It is concluded that most injected charges are stored near or at the interfaces of SiO,-Al,O, layers and the stored charges are responsible for the shift of threshold voltage in MAOS memory transistors. It is also concluded from the hysteresis behavior of threshold voltage as described in section 3.1 that the amount of injected charges at the interfaces or in the oxide layer changes rougnly logarithmically with time for both directions of voltage stress. This seems reasonable because the amount of injected charge from metal electrodes is extremely small or is suppressed. The charge transport behavior between silicon and the composite oxide films on devices with SiO, of 50 A and A&O, of 700 A can be caused by the Fowler-Nordheim tunneling because the current flow which occurs across the alumina or silicon dioxide by the Pool-Frenkel mechanism is extremely small at room temperature. Consequently, threshold voltage shift responsible for the injection stored charges are not measured at room temperature. It is expected that the electrically alterable non-volatile memory devices having the possible performance more than lo6

dioxide-silicon

transistor

375

memory cycles, at least, would be developed by using the charge storage behavior controlled by electric field. It will be concluded that the degradation and the failure mechanism of the MAOS memory transistor are similar to those of the MNOS memory transistor[8,9]. Acknowledgement-The

authors express their gratitude to Dr. T. Aoki for alumina film deposition and_to Mr. M. Kiuchi, Mr. Y. Kawana, Dr. T. Tsukamoto, Dr. Y. Kanai and Dr. M. Takasaki for their encouragements and support of this work.

REFERENCES

1. H. C. Pao and M. 0. Connel. ,..ADDI. Phvs. , Letrs. 12,260 (I 968). 2. D. Kahng and S. M. Sze, Bell Syst. Tech. J. 46, 1228 (1968). 3. .I. T. Wallmark and J. H. Scott, Jr., RCA Rev. 30, 335 (1969). 4. E. C. Ross and J. T. Wallmark. RCA Rev. 30. 366 (1969). 5. D. Frohman-Benchkowsky and M. Lenzlinger, J. appl. Phys. 40,3307 (1969). 6. K. Kobayashi and K. Ohta, Jup. J. uppl. Phys. 11, 538 (1972). 7. K. Kobayashi, Jap. J. appl. Phys. 11,555 (1972). 8. M. H. Woods and J. W. Tuska, Tenth Proc. Reliability Physics,

p. 120 (1972).

9. B. V. Keshavan Devices

Meeting,

and A. J. Moore, Int. Electron. Abs. 13.2, Washington, D.C.

(1972). 10. D. Frohman-Benchkowsky,

Appl. Phys. Lefts,

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