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Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices
Microelectronic Engineering 88 (2011) 1228–1231
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices P.H. Morel a, C. Leroux a, J.M. Hartmann a, C. Morin b, P. Faucherand b, S. Perraud b, L. Cagnon c, T. Baron d, B. Salem d, M. Fayolle-Lecocq a, T. Ernst a,⇑ a
CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble, France CEA, LITEN, 17 rue des Martyrs, 38054 Grenoble, France Institut Néel/CNRS/UJF-Grenoble 1, BP166, 38042 Grenoble Cedex 9, France d LTM/CNRS/UJF-Grenoble 1/Grenoble-INP/CEA, 17 rue des Martyrs, 38054 Grenoble, France b c
a r t i c l e
i n f o
Article history: Received 24 February 2011 Received in revised form 21 March 2011 Accepted 23 March 2011 Available online 29 March 2011 Keywords: CVD nanowire Selective Epitaxial Growth Nanocapacitor VLS growth Low temperature gate stack
a b s t r a c t We report a study of low temperature gate stack on silicon nanowires compatible with Back-End-Of-Line (BEOL) integration. The same gate stack is deposited at low temperature on Si nanowires obtained thanks to either Chemical Vapor Deposition (CVD) or Selective Epitaxial Growth (SEG) in patterns. Gate stack characterization on CVD nanowires (NWs) shows low leakages and good agreement with simulated curves without interface states. A dramatic decrease of the capacitance in accumulation region and faster electron generation are observed and attributed to NW defects. In contrast, SEG devices reveals lower capacitance decrease with frequency but higher interface state density of about 1013 cm 2. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Silicon nanowires have extensively been studied during the last decade for uses in nanoelectronics [1–4], optics [5], energy conversion [6] and sensors [7–10] applications. Two approaches can be used to fabricate such nanostructures: first, the top-down approach [1] uses the substrate itself as a silicon source and photolithography followed by etching for nanowire (NW) fabrication. The second approach, called bottom-up, uses a gas as silicon source (such as SiH4 or SiCl4) and the nanowires are grown on a substrate [11] in a Chemical Vapor Deposition (CVD) reactor. With the latest method and using a metal catalyst, it is possible to obtain single crystalline nanowires even on a metallic line [12]. This interesting property would allow integrating MOS devices in the metallic interconnection levels of an Integrated Circuit (IC). Such an integration makes the use of a low temperature (<400 °C) process mandatory. A template for guiding NWs is also necessary to obtain straight NWs. Thus, evaluating CVD nanowires (NWs) low temperature gate stack quality and potentialities is of the upmost interest for device purposes. One common method to characterize such a gate stack consists in breaking off nanowires after their growth and then depositing ⇑ Corresponding author. E-mail address: [email protected] (T. Ernst). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.088
the gate stack on single nanowires [13,14]. Unfortunately, by this way, only single NW can be connected and characterized. Another method consists in depositing the gate stack directly on grown NWs, thus enabling to study the NW devices in a more realistic configuration [15]. On a Si(1 0 0) oriented substrates, silicon NWs tend to grow with various directions, as on a metallic underlayer. In this study, we grew the silicon NWs on (1 0 0) oriented substrate to evidence the impact of an oxide template on the NW growth and on their electrical properties. Highly doped silicon with resistivity as low as 14 mX cm is used as the underlayer instead of any metallic layer to get good electrical contact and to characterize the gate stack itself. The NW/metallic under layer contact will have to be characterized in a further work. In the following, we will study the quality of a low temperature high-k/metal gate stack quality deposited on silicon NWs grown in an oxide template from p-Si(1 0 0) oriented substrate. Using the same oxide template, some Selective Epitaxial Growth (SEG) pillars were grown and characterized with the same gate stack for comparison. 2. Sample fabrication As shown in Fig. 1, the nanostructures are grown in similar conditions for the two techniques (CVD and SEG). A 1 lm thick SiO2
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P.H. Morel et al. / Microelectronic Engineering 88 (2011) 1228–1231
Au
SiO 2
SiO 2
(a)
Si (100)
Si (100)
(a)
(b)
200 nm
10 nm
I(V) C(V)
I(V) C(V)
Nanowire
(b) Si (100)
(c)
Si (100)
500 nm
20 nm
Substrate
(d)
Fig. 1. Schematics of the main fabrication steps on our patterned, Si(1 0 0) substrates: (a) Si NWs Chemical Vapor Deposition (CVD) using gold as catalyst and (b) Si pillar Selective Epitaxial Growth (SEG). (c) Gold removal followed by partial oxide etching and gate stack deposition and (d) gate stack deposition on SEG pillars.
layer was deposited on a (1 0 0) p-type doped silicon substrate, then patterned with a deep-UV photolithography and anisotropic etching. The obtained template consists in a 500 nm diameter holes assembly in the oxide, opened on the silicon substrate. Prior to CVD NW growth, the holes were filled by 200 nm of gold thanks to a specially developed selective process. This process consists in a first isotropic etching under the resist to protect the oxide holes sidewalls from any gold deposition. The gold located on the top of the photoresist was then removed by a 45° tilted Ion Beam Etching followed by the photo-resist stripping. NWs were then grown with a two steps sequence in a CVD reactor using the VLS mechanism [11]. After a catalyst de-wetting at 650 °C under H2, growth was carried out at the same temperature under SiH4 and HCl. For SEG pillars, the growth was carried out at 950 °C with a Cyclic Deposition/Etch approach to obtain ‘‘reference’’ high-quality nanostructures [16]. CVD NWs are about 4 lm long, 500–700 nm in diameter, and have a common saw tooth faceting at the surface. SEG pillars have a 500 nm diameter, and a 1 lm length as shown in Fig. 2. Prior to any gate stack deposition, part of the oxide template is removed using a Buffered Oxide Etchant (BOE) bath, leaving about 100 nm thick oxide at the bottom of the nanostructures. After a gold removal in a potassium iodide bath (IKI) for the CVD
Fig. 3. Cross-sectional TEM images of (a) SEG pillars after growth showing sidewall roughness and stacking faults running from the edge to the center of the pillars and (b) catalyzed CVD silicon nanowires after growth showing stacking faults and gold residues at the nanowire substrate interface.
NWs, alumina and titanium nitride layers have been deposited on both types of nanostructures by Atomic Layer Deposition at 250 °C and Physical Vapor Deposition (PVD) respectively. After photolithography and the etching of the metal gate electrode, each MOS capacitor is composed of about 2200 nanostructures connected in parallel. 3. Results and discussion Cross-sectional Transmission Electron Microscopy images (Fig. 3) after growth show the presence of stacking fault on both types of nanostructures. Fig. 3a reveals the SEG pillars’ roughness and the presence of stacking faults running from the edge to the center of the nanostructure. Interestingly, in the case of NWs, the defects are mainly located in the NW part inside the oxide template. The capacitance stack was then characterized with cross-sectional Scanning Electron Microscopy (SEM) (Fig. 4). On both pictures (Fig. 4a and b) the devices have been encapsulated with oxide and tungsten for the Focused Ion Beam sample preparation. SEM pictures reveal that the deposition of the 20 nm thick alumina layer was conformal. The top metal PVD depositions of TiN/Cu/TiN stack were not as conformal: titanium nitride layers vary from 20 to 50 nm and the copper layer from 50 to 100 nm.
TiN /Cu / TiN
(a)
400 nm
Al2O3
(b) 12 µm
(b)
500 nm
3 µm Fig. 2. SEM top views of (a) catalyzed CVD silicon nanowires and (b) SEG pillars after growth.
(a)
20µm
(c)
Fig. 4. (a) Cross-sectional SEM images of Si CVD NW and SEG pillar after the low temperature deposition of the gate stack. (c) A top view SEM image of a CVD NW capacitor with about 1000 NWs.
P.H. Morel et al. / Microelectronic Engineering 88 (2011) 1228–1231
160
103
140
102 10 1
120
Current Density (A/cm²)
Capacitance (pF)
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1 kHz
100
10 kHz
80
Theory
100 kHz
60 40
-2
-1
0
1
2
10-2 10-3 10-4 10-5
3
Fig. 5. Capacitance versus gate bias measurements on CVD NW devices showing a good agreement at 1 kHz with the simulated curve without interface states. A significant decrease at higher frequency is also observed and can be attributed to low carrier mobility in the NWs.
Capacitance (pF)
38 33
1 kHz 10 kHz 100 kHz
23 18 13 -2
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-0.5
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Gate Bias (V)
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10-6 10-7 10-8 10-9 0
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10-1
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Gate Bias (V) Fig. 6. Capacitance versus gate bias measurements on SEG pillars showing fluctuations at 1 kHz due to a high interface state density.
The gate stack is then electrically characterized by C(V) measurements with an Agilent 4284A equipment from 1 up to 100 kHz. Results are plotted in Figs. 5 and 6 for CVD NWs and SEG pillars respectively. The measured parasitic gate/substrate capacitance (12 pF) has been removed from all results. For CVD NWs, the measured oxide capacitance (Cox) is about 130 pF which is a bit higher than the 113 pF theoretical value calculated from NW geometrical dimensions after growth. In fact there is some space between the NWs and the oxide sidewalls after BOE etching. The gate stack can deposit on the NWs inside the holes and on the free part of the substrate between the NW and the oxide sidewalls, thus increasing the capacitance and decreasing the series resistance. The theoretical low frequency C(V) curve has been simulated [17] as shown in Fig. 5, considering a midgap top metal (which corresponds to the titanium nitride layer). The measured and simulated curves are in good agreement with a doping level of 1016 cm 3 and an oxide charge density of 1012 cm 2. This reveals that some charges are stored in the alumina dielectric, which is attributed to its low temperature deposition (250 °C). They could not be removed by exodiffusion due to the low thermal budget constraint of our process. At higher frequencies, the accumulation mode starts at higher voltages. This is attributed to a degraded carriers’ mobility in the considered CVD NWs. Indeed, the latter have a saw tooth faceting
Fig. 7. Current density versus gate bias on CVD NWs and on SEG pillars.
and some gold residues on their surfaces. They have also extended crystalline defects such as twinning boundaries due to template guiding. Those defects may impact the carriers’ mobility, leading to a decrease of the capacitance when frequency increases. Moreover, a faster electron generation than on SEG pillars is revealed by the increase of the capacitance for positive voltages. This phenomenon can be attributed to gold catalyst residues that have diffused inside the nanowire and that could not be removed during the IKI bath. They constitute metallic defects that generate electrons at positive voltages. In contrast, SEG pillars in Fig. 6, have a measured Cox of 35 pF in very good agreement with the theoretical calculated value of 33 pF based on geometrical dimensions after growth and oxide etching. In fact, the SEG pillars dimensions are indeed well controlled by the SiO2 template geometry. C(V) measurements plotted in Fig. 6, show the presence of rather high interface states densities on all curves from 1 to 100 kHz. Due to this very high interface state density, it is difficult to fit precisely the C(V) measurements by simulation. We can however estimate the interface state density to be as high as 1013 cm 2. The low frequency dispersion observed between 0.5 and 0.5 V reveals that the main part of the traps are fast interface states localized close to the band gap edge. Here, there is no shift in the accumulation starting voltage, maybe related to fewer crystalline defects and no gold residues. Finally, the SEG pillars reveal fewer crystalline defects but a worse interface quality than CVD NWs. Indeed, devices are quite different: the NW capacitors are composed of two parts: (i) a part inside the original hole where the NWs suffer from many crystalline defects due to the contact between the NW and the template during growth and (ii) a part outside the hole where the nanowire is free of any strain from the template. The first part is about 1 lm whereas the second one is about 3 lm. For CVD NWs, the main part of the measured capacitance corresponds to the free part where there are less crystalline defects. In contrast, for SEG pillars, the capacitance is only composed by the pillar inside the template where there are more surface defects due to the contact between the pillar and the template during growth. From capacitances measurements, areas were extracted using a dielectric constant value of 9 and 15 nm as alumina thickness. The current density measurements as a function of the gate bias (Fig. 7), reveals lower leakages for CVD NWs than for SEG pillars (about 15 nA/cm2 and 130 nA/cm2 respectively). 4. Conclusion A silicon NW integration process has been developed to fabricate functional MOS capacitors. Electrical measurements reveal
P.H. Morel et al. / Microelectronic Engineering 88 (2011) 1228–1231
that NWs have better interface quality than SEG pillars with our interconnect levels compatible gate stack. A faster electron generation and a capacitance decrease with frequency were evidenced for CVD NWs and attributed to defects. With the CVD method, we have evidenced the metallic contamination that would induce leakages in NW MOSFETs. In contrast, with the SEG method, interfaces states observed may impact carrier mobility and lower the subthreshold slope. From the industrial point of view, CVD methods seems to be difficult to use in the Front-End-Of-the-Line (FEOL) part of Ultra-Large Scale Integration (ULSI) of CMOS devices due to metallic catalyst contamination issues. CVD Si NWs are however very interesting for Back-End-Of-the-Line (BEOL) applications such as vertical transistors between interconnect lines. These MOSFETs will have to be designed taking into account defects induced by metallic contamination.
[2] [3]
[4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Acknowledgement [14]
This work was supported by the French National Research Agency (ANR) through Carnot Institute funding. A part of this work was supported by the European Research Council.
[15]
References
[17]
[1] T. Ernst, L. Duraffourg, C. Dupré, E. Bernard, P. Andreucci, S. Bécu, E. Ollier, A. Hubert, C. Halté, J. Buckley, O. Thomas, G. Delapierre, S. Deleonibus, B. de Salvo,
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P. Robert, O. Faynot, Proceeding of the 2008 IEDM Conference, San Francisco, USA, p. 745. V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess, U. Gosele, Small 2 (2006) 85. C. Dupre, T. Ernst, V. Maffini-Alvaro, V. Delaye, J.M. Hartmann, S. Borel, C. Vizioz, O. Faynot, G. Ghibaudo, S. Deleonibus, Solid-State Electron. 52 (2008) 519. L. Wei, X. Ping, C.M. Lieber, IEEE Trans. Electron Dev. 55 (2008) 2859. H. Yamada, M. Shirane, T. Chu, H. Yokoyama, S. Ishida, Y. Arakawa, Jpn. J. Appl. Phys. 44 (2005) 6541. S. Perraud, S. Poncet, S. Noel, M. Levis, P. Faucherand, E. Rouviere, P. Thony, C. Jaussaud, R. Delsol, Sol. Energy Mater. Sol. Cells 93 (2009) 1568. E. Mile, G. Jourdan, I. Bargatin, S. Labarthe, C. Marcoux, P. Andreucci, S. Hentz, C. Kharrat, E. Colinet, L. Duraffourg, Nanotechnology 21 (2010) 165504. M. Li, H.X. Tang, M.L. Roukes, Nat. Nanotechnol. 2 (2007) 114. G.F. Zheng, F. Patolsky, Y. Cui, W. Wang, C.M. Lieber, Nat. Biotechnol. 23 (2005) 1294. N.G. Portney, M. Ozkan, Anal. Bioanal. Chem. 384 (2006) 620. R.S. Wagner, W.C. Ellis, Appl. Phys. Lett. 4 (1964) 89. V.T. Renard, M. Jublot, P. Gergaud, P. Cherns, D. Rouchon, A. Chabli, V. Jousseaume, Nat. Nanotechnol. 4 (2009) 654. E.C. Garnett, Y.C. Tseng, D.R. Khanal, J. Wu, J. Bokor, P. Yang, Nat. Nanotechnol. 4 (2009) 311–314. B. Salem, F. Dhalluin, T. Baron, H. Jamgotchian, F. Bedu, H. Dallaporta, P. Gentile, N. Pauc, M.I. den Hertog, J.L. Rouvière, P. Ferret, Mat. Sci. Eng., B 159–160 (2009) 83. G. Astromskas, K. Storm, P. Caroff, M. Borgström, E. Lind, L.E. Wernersson, Microelectron. Eng. 88 (2011) 444. J.M. Hartmann, M. Py, P.H. Morel, T. Ernst, B. Prévitali, J.P. Barnes, N. Vulliet, N. Cherkashin, S. Reboh, M. Hÿtch, V. Paillard, ECS Trans. 33 (7) (2010) 391. C. Leroux, F. Allain, A. Toffoli, G. Ghibaudo, G. Reimbold, Microelectron. Eng. 84 (2007) 2408.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices P.H. Morel a, C. Leroux a, J.M. Hartmann a, C. Morin b, P. Faucherand b, S. Perraud b, L. Cagnon c, T. Baron d, B. Salem d, M. Fayolle-Lecocq a, T. Ernst a,⇑ a
CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble, France CEA, LITEN, 17 rue des Martyrs, 38054 Grenoble, France Institut Néel/CNRS/UJF-Grenoble 1, BP166, 38042 Grenoble Cedex 9, France d LTM/CNRS/UJF-Grenoble 1/Grenoble-INP/CEA, 17 rue des Martyrs, 38054 Grenoble, France b c
a r t i c l e
i n f o
Article history: Received 24 February 2011 Received in revised form 21 March 2011 Accepted 23 March 2011 Available online 29 March 2011 Keywords: CVD nanowire Selective Epitaxial Growth Nanocapacitor VLS growth Low temperature gate stack
a b s t r a c t We report a study of low temperature gate stack on silicon nanowires compatible with Back-End-Of-Line (BEOL) integration. The same gate stack is deposited at low temperature on Si nanowires obtained thanks to either Chemical Vapor Deposition (CVD) or Selective Epitaxial Growth (SEG) in patterns. Gate stack characterization on CVD nanowires (NWs) shows low leakages and good agreement with simulated curves without interface states. A dramatic decrease of the capacitance in accumulation region and faster electron generation are observed and attributed to NW defects. In contrast, SEG devices reveals lower capacitance decrease with frequency but higher interface state density of about 1013 cm 2. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Silicon nanowires have extensively been studied during the last decade for uses in nanoelectronics [1–4], optics [5], energy conversion [6] and sensors [7–10] applications. Two approaches can be used to fabricate such nanostructures: first, the top-down approach [1] uses the substrate itself as a silicon source and photolithography followed by etching for nanowire (NW) fabrication. The second approach, called bottom-up, uses a gas as silicon source (such as SiH4 or SiCl4) and the nanowires are grown on a substrate [11] in a Chemical Vapor Deposition (CVD) reactor. With the latest method and using a metal catalyst, it is possible to obtain single crystalline nanowires even on a metallic line [12]. This interesting property would allow integrating MOS devices in the metallic interconnection levels of an Integrated Circuit (IC). Such an integration makes the use of a low temperature (<400 °C) process mandatory. A template for guiding NWs is also necessary to obtain straight NWs. Thus, evaluating CVD nanowires (NWs) low temperature gate stack quality and potentialities is of the upmost interest for device purposes. One common method to characterize such a gate stack consists in breaking off nanowires after their growth and then depositing ⇑ Corresponding author. E-mail address: [email protected] (T. Ernst). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.088
the gate stack on single nanowires [13,14]. Unfortunately, by this way, only single NW can be connected and characterized. Another method consists in depositing the gate stack directly on grown NWs, thus enabling to study the NW devices in a more realistic configuration [15]. On a Si(1 0 0) oriented substrates, silicon NWs tend to grow with various directions, as on a metallic underlayer. In this study, we grew the silicon NWs on (1 0 0) oriented substrate to evidence the impact of an oxide template on the NW growth and on their electrical properties. Highly doped silicon with resistivity as low as 14 mX cm is used as the underlayer instead of any metallic layer to get good electrical contact and to characterize the gate stack itself. The NW/metallic under layer contact will have to be characterized in a further work. In the following, we will study the quality of a low temperature high-k/metal gate stack quality deposited on silicon NWs grown in an oxide template from p-Si(1 0 0) oriented substrate. Using the same oxide template, some Selective Epitaxial Growth (SEG) pillars were grown and characterized with the same gate stack for comparison. 2. Sample fabrication As shown in Fig. 1, the nanostructures are grown in similar conditions for the two techniques (CVD and SEG). A 1 lm thick SiO2
1229
P.H. Morel et al. / Microelectronic Engineering 88 (2011) 1228–1231
Au
SiO 2
SiO 2
(a)
Si (100)
Si (100)
(a)
(b)
200 nm
10 nm
I(V) C(V)
I(V) C(V)
Nanowire
(b) Si (100)
(c)
Si (100)
500 nm
20 nm
Substrate
(d)
Fig. 1. Schematics of the main fabrication steps on our patterned, Si(1 0 0) substrates: (a) Si NWs Chemical Vapor Deposition (CVD) using gold as catalyst and (b) Si pillar Selective Epitaxial Growth (SEG). (c) Gold removal followed by partial oxide etching and gate stack deposition and (d) gate stack deposition on SEG pillars.
layer was deposited on a (1 0 0) p-type doped silicon substrate, then patterned with a deep-UV photolithography and anisotropic etching. The obtained template consists in a 500 nm diameter holes assembly in the oxide, opened on the silicon substrate. Prior to CVD NW growth, the holes were filled by 200 nm of gold thanks to a specially developed selective process. This process consists in a first isotropic etching under the resist to protect the oxide holes sidewalls from any gold deposition. The gold located on the top of the photoresist was then removed by a 45° tilted Ion Beam Etching followed by the photo-resist stripping. NWs were then grown with a two steps sequence in a CVD reactor using the VLS mechanism [11]. After a catalyst de-wetting at 650 °C under H2, growth was carried out at the same temperature under SiH4 and HCl. For SEG pillars, the growth was carried out at 950 °C with a Cyclic Deposition/Etch approach to obtain ‘‘reference’’ high-quality nanostructures [16]. CVD NWs are about 4 lm long, 500–700 nm in diameter, and have a common saw tooth faceting at the surface. SEG pillars have a 500 nm diameter, and a 1 lm length as shown in Fig. 2. Prior to any gate stack deposition, part of the oxide template is removed using a Buffered Oxide Etchant (BOE) bath, leaving about 100 nm thick oxide at the bottom of the nanostructures. After a gold removal in a potassium iodide bath (IKI) for the CVD
Fig. 3. Cross-sectional TEM images of (a) SEG pillars after growth showing sidewall roughness and stacking faults running from the edge to the center of the pillars and (b) catalyzed CVD silicon nanowires after growth showing stacking faults and gold residues at the nanowire substrate interface.
NWs, alumina and titanium nitride layers have been deposited on both types of nanostructures by Atomic Layer Deposition at 250 °C and Physical Vapor Deposition (PVD) respectively. After photolithography and the etching of the metal gate electrode, each MOS capacitor is composed of about 2200 nanostructures connected in parallel. 3. Results and discussion Cross-sectional Transmission Electron Microscopy images (Fig. 3) after growth show the presence of stacking fault on both types of nanostructures. Fig. 3a reveals the SEG pillars’ roughness and the presence of stacking faults running from the edge to the center of the nanostructure. Interestingly, in the case of NWs, the defects are mainly located in the NW part inside the oxide template. The capacitance stack was then characterized with cross-sectional Scanning Electron Microscopy (SEM) (Fig. 4). On both pictures (Fig. 4a and b) the devices have been encapsulated with oxide and tungsten for the Focused Ion Beam sample preparation. SEM pictures reveal that the deposition of the 20 nm thick alumina layer was conformal. The top metal PVD depositions of TiN/Cu/TiN stack were not as conformal: titanium nitride layers vary from 20 to 50 nm and the copper layer from 50 to 100 nm.
TiN /Cu / TiN
(a)
400 nm
Al2O3
(b) 12 µm
(b)
500 nm
3 µm Fig. 2. SEM top views of (a) catalyzed CVD silicon nanowires and (b) SEG pillars after growth.
(a)
20µm
(c)
Fig. 4. (a) Cross-sectional SEM images of Si CVD NW and SEG pillar after the low temperature deposition of the gate stack. (c) A top view SEM image of a CVD NW capacitor with about 1000 NWs.
P.H. Morel et al. / Microelectronic Engineering 88 (2011) 1228–1231
160
103
140
102 10 1
120
Current Density (A/cm²)
Capacitance (pF)
1230
1 kHz
100
10 kHz
80
Theory
100 kHz
60 40
-2
-1
0
1
2
10-2 10-3 10-4 10-5
3
Fig. 5. Capacitance versus gate bias measurements on CVD NW devices showing a good agreement at 1 kHz with the simulated curve without interface states. A significant decrease at higher frequency is also observed and can be attributed to low carrier mobility in the NWs.
Capacitance (pF)
38 33
1 kHz 10 kHz 100 kHz
23 18 13 -2
-1.5
-1
-0.5
0
0.5
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1.5
SEG Pillars
1
2
3
4
5
6
7
8
Gate Bias (V)
Gate Bias (V)
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10-6 10-7 10-8 10-9 0
20 -3
10-1
2
Gate Bias (V) Fig. 6. Capacitance versus gate bias measurements on SEG pillars showing fluctuations at 1 kHz due to a high interface state density.
The gate stack is then electrically characterized by C(V) measurements with an Agilent 4284A equipment from 1 up to 100 kHz. Results are plotted in Figs. 5 and 6 for CVD NWs and SEG pillars respectively. The measured parasitic gate/substrate capacitance (12 pF) has been removed from all results. For CVD NWs, the measured oxide capacitance (Cox) is about 130 pF which is a bit higher than the 113 pF theoretical value calculated from NW geometrical dimensions after growth. In fact there is some space between the NWs and the oxide sidewalls after BOE etching. The gate stack can deposit on the NWs inside the holes and on the free part of the substrate between the NW and the oxide sidewalls, thus increasing the capacitance and decreasing the series resistance. The theoretical low frequency C(V) curve has been simulated [17] as shown in Fig. 5, considering a midgap top metal (which corresponds to the titanium nitride layer). The measured and simulated curves are in good agreement with a doping level of 1016 cm 3 and an oxide charge density of 1012 cm 2. This reveals that some charges are stored in the alumina dielectric, which is attributed to its low temperature deposition (250 °C). They could not be removed by exodiffusion due to the low thermal budget constraint of our process. At higher frequencies, the accumulation mode starts at higher voltages. This is attributed to a degraded carriers’ mobility in the considered CVD NWs. Indeed, the latter have a saw tooth faceting
Fig. 7. Current density versus gate bias on CVD NWs and on SEG pillars.
and some gold residues on their surfaces. They have also extended crystalline defects such as twinning boundaries due to template guiding. Those defects may impact the carriers’ mobility, leading to a decrease of the capacitance when frequency increases. Moreover, a faster electron generation than on SEG pillars is revealed by the increase of the capacitance for positive voltages. This phenomenon can be attributed to gold catalyst residues that have diffused inside the nanowire and that could not be removed during the IKI bath. They constitute metallic defects that generate electrons at positive voltages. In contrast, SEG pillars in Fig. 6, have a measured Cox of 35 pF in very good agreement with the theoretical calculated value of 33 pF based on geometrical dimensions after growth and oxide etching. In fact, the SEG pillars dimensions are indeed well controlled by the SiO2 template geometry. C(V) measurements plotted in Fig. 6, show the presence of rather high interface states densities on all curves from 1 to 100 kHz. Due to this very high interface state density, it is difficult to fit precisely the C(V) measurements by simulation. We can however estimate the interface state density to be as high as 1013 cm 2. The low frequency dispersion observed between 0.5 and 0.5 V reveals that the main part of the traps are fast interface states localized close to the band gap edge. Here, there is no shift in the accumulation starting voltage, maybe related to fewer crystalline defects and no gold residues. Finally, the SEG pillars reveal fewer crystalline defects but a worse interface quality than CVD NWs. Indeed, devices are quite different: the NW capacitors are composed of two parts: (i) a part inside the original hole where the NWs suffer from many crystalline defects due to the contact between the NW and the template during growth and (ii) a part outside the hole where the nanowire is free of any strain from the template. The first part is about 1 lm whereas the second one is about 3 lm. For CVD NWs, the main part of the measured capacitance corresponds to the free part where there are less crystalline defects. In contrast, for SEG pillars, the capacitance is only composed by the pillar inside the template where there are more surface defects due to the contact between the pillar and the template during growth. From capacitances measurements, areas were extracted using a dielectric constant value of 9 and 15 nm as alumina thickness. The current density measurements as a function of the gate bias (Fig. 7), reveals lower leakages for CVD NWs than for SEG pillars (about 15 nA/cm2 and 130 nA/cm2 respectively). 4. Conclusion A silicon NW integration process has been developed to fabricate functional MOS capacitors. Electrical measurements reveal
P.H. Morel et al. / Microelectronic Engineering 88 (2011) 1228–1231
that NWs have better interface quality than SEG pillars with our interconnect levels compatible gate stack. A faster electron generation and a capacitance decrease with frequency were evidenced for CVD NWs and attributed to defects. With the CVD method, we have evidenced the metallic contamination that would induce leakages in NW MOSFETs. In contrast, with the SEG method, interfaces states observed may impact carrier mobility and lower the subthreshold slope. From the industrial point of view, CVD methods seems to be difficult to use in the Front-End-Of-the-Line (FEOL) part of Ultra-Large Scale Integration (ULSI) of CMOS devices due to metallic catalyst contamination issues. CVD Si NWs are however very interesting for Back-End-Of-the-Line (BEOL) applications such as vertical transistors between interconnect lines. These MOSFETs will have to be designed taking into account defects induced by metallic contamination.
[2] [3]
[4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Acknowledgement [14]
This work was supported by the French National Research Agency (ANR) through Carnot Institute funding. A part of this work was supported by the European Research Council.
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