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Study of failure modes of multilevel large-scale integrated circuits
WORLD
ABSTRACTS
ON MICROELECTRONICS
2. R E L I A B I L I T Y O F C O M P O N E N T S ,
*Study of failure m o d e s of m u l t i l e v e l large-scale integrated circuits. E. S. SCHLEGEL, June (1970), pp. 111, (1127-7103) P-169232 NASA-CR-1567. PhilcoFord Corp., Blue Bell, Pa, U.S.A. A new set of test structures has been prepared to evaluate the fundamental electrical properties of oxide-sillcon interfaces of the types likely to be found in large-scale multilevel microcircuit arrays. A discussion is given of the considerations involved in the design of each test structure in the set and of problems that arise in their use. Experimental data are given that compare the field inversion voltage under metal to that in regions not under metal. Experimental data are given on fast state annealing. The effects of processing variables on surface recombination velocity have been measured. Measurements of the surface conductivity of insulator layers used in microcircuits have shown vapour plated phosphosilicate to have a surprisingly low surface conductivity. Data have been taken that further support a postulate that mobile ion densities in an oxide are influenced by the presence of a p--n junction. A n MOS-LSI m e m o r y reliability program for a c o m m e r c i a l computer application. H. A. SPIVAK, L. E. HAWKINS and A. J. NASUTI, Proc. Ann. Symp. Reliab., Washington DC, U.S.A. IEEE Cat. No. 71C 2-R. 12-14 January (1971), p. 331. In most commercial applications the two major factors which will determine whether MOS memories displace ferrite core memories are, cost per bit and reliability. This paper describes the reliability program developed for a fully decoded, 1024-bit dynamic random access memory (RAM), monolithic M O S - L S I circuit at Honeywell Information Systems, Framingham, Massachusetts. This device represents a major advance in M O S - L S I I/C technology. With a cycle time close to 500 nsec, a power consumption of approximately 50 microwatts per bit and a chip size of 117 × 138 mils, the device is a major challenge to the existing monopoly of ferrite cores for computer main memories. This paper discusses the reasons for the various trade-off decisions made in developing the program and those tests which were found to be most useful in disclosing device performance and failure mechanisms. Also described are the data feedback and performance history procedures developed.
Total reliability requirement procedure for largescale integrated circuit array devices. C. VAN LEEUWEN and N. VAN VONNO, Proc. Ann. Symp. Reliab., Washington DC, U.S.A. IEEE Cat. No. 71C2-R. 12-14 January (1971), p. 57. The procedures described have been specifically designed to establish product integrity through extensive reliability testing. Extensive use is made of highly accelerated testing in order to reduce time required for assessing reliability, using previously developed acceleration factors to allow meaningful extrapolation. T h e plan includes review and decision points as early in device processing as dice inspection. Participation by the Reliability Department in concept,
AND RELIABILITY
TUBES, TRANSISTORS
303
A N D ICs
design and layout reviews allows reliability-oriented problems to be identified as early in the design process as possible. The development reliability assessment phase consists of the following three major evaluations: (a) qualification of the process by extensive use of process-oriented test vehicles; (b) design/circuit qualification; (c) qualification of the package with associated die-to-package interconnecting technology.
The influence of stationary dislocations and stacking faults on s o m e transistor parameters. P. C. PAREKH, Nolid-St. Electron. 14 (1971), p. 273. The influence of stationary dislocations and stacking faults on npn transistor parameters have been considered in the presence of varying amounts of gold concentrations in the base region. An increase in pipe density and soft junction breakdown was observed as the gold concentration increased. Wide variations in pipe resistance and inverse current gain were observed within a slice. For high concentration phosphorus emitter diffusion, some enhancement of the diffusion of phosphorus atoms along dislocations resulted in some compensation of the acceptor charge in the base region. This resulted in an increase in current gain and a decrease in collector-base breakdown which was punch-through limited.
Factors involved in the scanning electron microscope analysis of glass passivated devices. A. J. GONZALES, Proc. IEEE Reliab. Phys. Symp., Las Vegas, U.S.A. 31 March-2 April (1971). Glass passivation of device surfaces can modify the information which can be obtained by the scanning electron microscope. Integrated circuits containing a variety of defects have been studied before and after passivation to illustrate the deleterious effects of passivation on scanning microscopy analysis. In addition, techniques of glass removal, contrast enhancement and voltage contrast analysis have been evaluated.
Detection of loose particles within electronic c o m ponent cavities. R. W. PFEIL, Proc. Ann. Syrup. Reliab., Washington DC, U.S.A. IEEE Cat. No. 71C2-R. 12-14- January (1971), p. 48. This paper presents a detailed discussion of the evolution of particle impact noise detection (PIND) at Lockheed Missiles & Space Company (LMSC). The implementation, management system, cost savings by comparison with other test techniques and resultant improvement in system reliability are also discussed. The presence of loose extraneous material within the cavities of electronic components can go undetected during functional tests normally performed to ensure device integrity. When components containing loose particulate material are subjected to aerospace environments, this material is agitated during vibration/acceleration phases, and may migrate randomly within the component. T h e movement of the contaminants may result in their eventually becoming lodged in critical areas, causing intermittent operation or catastrophic failure.
ABSTRACTS
ON MICROELECTRONICS
2. R E L I A B I L I T Y O F C O M P O N E N T S ,
*Study of failure m o d e s of m u l t i l e v e l large-scale integrated circuits. E. S. SCHLEGEL, June (1970), pp. 111, (1127-7103) P-169232 NASA-CR-1567. PhilcoFord Corp., Blue Bell, Pa, U.S.A. A new set of test structures has been prepared to evaluate the fundamental electrical properties of oxide-sillcon interfaces of the types likely to be found in large-scale multilevel microcircuit arrays. A discussion is given of the considerations involved in the design of each test structure in the set and of problems that arise in their use. Experimental data are given that compare the field inversion voltage under metal to that in regions not under metal. Experimental data are given on fast state annealing. The effects of processing variables on surface recombination velocity have been measured. Measurements of the surface conductivity of insulator layers used in microcircuits have shown vapour plated phosphosilicate to have a surprisingly low surface conductivity. Data have been taken that further support a postulate that mobile ion densities in an oxide are influenced by the presence of a p--n junction. A n MOS-LSI m e m o r y reliability program for a c o m m e r c i a l computer application. H. A. SPIVAK, L. E. HAWKINS and A. J. NASUTI, Proc. Ann. Symp. Reliab., Washington DC, U.S.A. IEEE Cat. No. 71C 2-R. 12-14 January (1971), p. 331. In most commercial applications the two major factors which will determine whether MOS memories displace ferrite core memories are, cost per bit and reliability. This paper describes the reliability program developed for a fully decoded, 1024-bit dynamic random access memory (RAM), monolithic M O S - L S I circuit at Honeywell Information Systems, Framingham, Massachusetts. This device represents a major advance in M O S - L S I I/C technology. With a cycle time close to 500 nsec, a power consumption of approximately 50 microwatts per bit and a chip size of 117 × 138 mils, the device is a major challenge to the existing monopoly of ferrite cores for computer main memories. This paper discusses the reasons for the various trade-off decisions made in developing the program and those tests which were found to be most useful in disclosing device performance and failure mechanisms. Also described are the data feedback and performance history procedures developed.
Total reliability requirement procedure for largescale integrated circuit array devices. C. VAN LEEUWEN and N. VAN VONNO, Proc. Ann. Symp. Reliab., Washington DC, U.S.A. IEEE Cat. No. 71C2-R. 12-14 January (1971), p. 57. The procedures described have been specifically designed to establish product integrity through extensive reliability testing. Extensive use is made of highly accelerated testing in order to reduce time required for assessing reliability, using previously developed acceleration factors to allow meaningful extrapolation. T h e plan includes review and decision points as early in device processing as dice inspection. Participation by the Reliability Department in concept,
AND RELIABILITY
TUBES, TRANSISTORS
303
A N D ICs
design and layout reviews allows reliability-oriented problems to be identified as early in the design process as possible. The development reliability assessment phase consists of the following three major evaluations: (a) qualification of the process by extensive use of process-oriented test vehicles; (b) design/circuit qualification; (c) qualification of the package with associated die-to-package interconnecting technology.
The influence of stationary dislocations and stacking faults on s o m e transistor parameters. P. C. PAREKH, Nolid-St. Electron. 14 (1971), p. 273. The influence of stationary dislocations and stacking faults on npn transistor parameters have been considered in the presence of varying amounts of gold concentrations in the base region. An increase in pipe density and soft junction breakdown was observed as the gold concentration increased. Wide variations in pipe resistance and inverse current gain were observed within a slice. For high concentration phosphorus emitter diffusion, some enhancement of the diffusion of phosphorus atoms along dislocations resulted in some compensation of the acceptor charge in the base region. This resulted in an increase in current gain and a decrease in collector-base breakdown which was punch-through limited.
Factors involved in the scanning electron microscope analysis of glass passivated devices. A. J. GONZALES, Proc. IEEE Reliab. Phys. Symp., Las Vegas, U.S.A. 31 March-2 April (1971). Glass passivation of device surfaces can modify the information which can be obtained by the scanning electron microscope. Integrated circuits containing a variety of defects have been studied before and after passivation to illustrate the deleterious effects of passivation on scanning microscopy analysis. In addition, techniques of glass removal, contrast enhancement and voltage contrast analysis have been evaluated.
Detection of loose particles within electronic c o m ponent cavities. R. W. PFEIL, Proc. Ann. Syrup. Reliab., Washington DC, U.S.A. IEEE Cat. No. 71C2-R. 12-14- January (1971), p. 48. This paper presents a detailed discussion of the evolution of particle impact noise detection (PIND) at Lockheed Missiles & Space Company (LMSC). The implementation, management system, cost savings by comparison with other test techniques and resultant improvement in system reliability are also discussed. The presence of loose extraneous material within the cavities of electronic components can go undetected during functional tests normally performed to ensure device integrity. When components containing loose particulate material are subjected to aerospace environments, this material is agitated during vibration/acceleration phases, and may migrate randomly within the component. T h e movement of the contaminants may result in their eventually becoming lodged in critical areas, causing intermittent operation or catastrophic failure.