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Study of hot-carrier degradation in submicrometer LDD NMOSFET's from 1f noise and charge pumping current measurements at different temperature anneals
MICROELECTRONIC ENGINEERING
ELSEVIER
Microelectronic
Engineering
28 (1995) 257-260
Study of hot-carrier degradation in submicrometer LDD NMOSFET’s from l/f noise and charge pumping current measurements at different temperature anneals D.S. Ang ‘, C.H. Ling” and Y.T. Yeow b ‘Department of Electrical Engineering, National University of Singapore, Singapore 05 1l.* bDepartment of Electrical Engineering, University of Queensland, Brisbane, Australia The l/f noise and variable frequency charge pumping current are used to probe hot-carrier induced oxide and interface traps. A strong correlation between the noise and charge pumping data is observed, confirming carrier capture by near-interface traps as the physical origin of l/f noise in MOS transistors. Results also suggest an oxide trap density that decreases with distance from the interface, and increases with energy from mid bandgap to the Si conduction band edge. 1.
INTRODUCTION
Hot-carrier degradation has been shown to result in charge trapping and oxide and interface trap generation, the damage being localised near the stressed junction. Fundamental issues involve identifying these traps, in space and in energy, and elucidating their effects on the device performance. This paper presents experimental results, based on the application of two of the most sensitive measurement techniques, namely l/f noise and charge pumping current, to the investigation of degradation in submicrometer LDD NMOSFET’s, after hot-carrier stress and after post-stress isochronal anneals. Correlating the results reveals new understanding of the non-homogeneous nature of the generated traps. 2.
EXPERIMENTAL
The test device was a surface channel LDD NMOSFET’s with dimensions 0.8 x 25p2, fabricated from 0.5~ twin-well, n+ polysilicon gate CMOS, nitride spacer technology, with gate oxide thickness &. = 13.5nm, designed for well operation V, = -2V. The device was stressed at V, = 8V, V, = V, = OV and with the gate voltage Vg = 0.6V, a value slightly higher than the threshold voltage V,. 30 min isochronal anneals in moderate vacuum, over the temperature range 373-573K, were carried out on a thermal stage provided by MMR Technologies, Inc. The l/f noise and charge pumping current were monitored after each anneal. The noise measurements were performed using PAR- 113 low noise preamplifier and HP3562A dynamic signal analyser. The charge pumping current was monitored on HP4156A parameter analyzer. The gate pulses were supplied by a HP8 112A signal generator at varying frequencies, and at constant 5V amplitude, 25ns transition times. 3.
RESULTS AND DISCUSSION
Charge pumping measurement, at high gate pulse frequencies, probes interface traps. However, as the frequency is lowered, captured electrons at interface traps have time to tunnel ’Thisworkis supported by a research grant RP930654 and a research scholarship (DSA) from the National University of Singapore. Funding support under the AAECP ASEANAustralia Microelectronics Programme is also acknowledged. 0167.9317/95/$09.50 0 1995 - Elsevier Science B.V. All rights reserved. SSDZ 0167-9317(95)00054-2
D.S. Ang et al. / Microelectronic Engineering 28 (199.5) 257-260
25%
to oxide traps, located near the Si - SO, interface [ 11.Fig. 1 shows the differential charge pumped per cycle AQcpand its annealing behaviour, for an NMOSFET stressed at low gate voltage. AQ, represents the difference in the amount of charge pumped per cycle between two gate pulse frequencies. Fig. 2 depicts (a) a snapshot of the applied gate pulse, and (b) the silicon surface band bending during time period T&2 of the charge pumping measurement. Electrons captured by the fast interface traps D, during the rising edge of the pulse, interact with the slower oxide traps N,,, via a tunneling mechanism, during time period Tin;,,,when the device is biased in inversion. When the device is driven into accumulation, near-interface oxide traps which were previously filled during the inversion cycle, are emptied by reverse tunneling of captured electrons back into the silicon substrate. This results in an additional charge pumping current component contributed by the interfacial oxide traps and leads to an increase in the amount of charge pumped per cycle Q,-&,,, if for low pulse frequencies [ 11.The relation between the electron tunneling time constant z and the distance of the trap from the interface x, is given by [2] ‘I; =
z, exp(m),
(1)
where T,,- lo-” s and a- lo8 cm-‘, typically. Using frequencies differing by a constant ratio thus allows probing of interfacial trap charge over approximately equal depth interval according to
PRE POST 313 423 473 523 573 SrREss ANNEALING TEMPERATURE, T(K)
Figure 1 : Differential charge pumped per cycle, AQc,, under hot-carrier stressing and isochronal anneal. Device is stressed at V, = BV, V, = 0.6V-V,, V, = V, = OV for
Figure 2 : (a) Snapshot of applied gate pulse; (b) silicon surface band bending during time period TJ2 of the charge pumping measurement. Arrows indicate tunneling of
t = 2 x 104s. CP measurement conditions: pulse amplitude = 5V, pulse rise and fall times = 25ns, source/drain grounded.
captured electrons into deeper oxide traps during the inversion cycle, q”;,,.
259
D.S. Ang et al. / Microelectronic Engineering 28 (1995) 257-260
where it is assumed that t, + $ < tp, fi < f2 , x1> q. The differential charge pumped per cycle, which provides an approximate measure of the amount of near-interface oxide traps within an oxide thickness Ax, is then defined as (3) An oxide trap distribution, decreasing with distance from the interface, is clearly evident from the post-stress data, as shown in Fig. 1. This trap profile persists at subsequent temperature anneals. Traps accessible to the lo/100 kHz gate pulse are completely annealed at the highest temperature of 573 K, however, some residual traps probed by the 0.1/l MHz gate pulse survive. This result suggests an oxide trap density, reported to be hole traps for the low V, stress [3], that is highest near the Si - SiO, interface, where maximum lattice strain exists, in contrast to a uniform oxide trap density assumed by some authors [4]. Annealing shows two distinct rates. Between 373K and 423K, a higher annealing rate is observed for traps nearer the interface. It is speculated that a larger built-in electric field due to the trapped holes, nearer the interface, enhances annealing, proposed to be due to electron tunneling to E’ centers, resulting in bond reformation or more probably bond compensation [5]. Above 423K, comparable annealing rates are observed, attributed to the thermal detrapping of holes [5]. Fig. 3 depicts the low frequency l/f noise characteristics. An average increase of about 8 dB is observed for the particular stress condition. Annealing leads to the recovery of the noise level to its pre-stress value, consistent with the removal of the interfacial oxide traps, observed in Fig. 1. Fig. 4 illustrates the differential change in noise level for different gate bias. We define the differential spectral density of drain curmnt fluctuations A($&) as the difference in the
16
10’
ld
I@
la’
FREQUENCY, f(Hz)
16
o* ‘...,.A IO0 10'
0 .
. *
.
.
“,“*
--
-
,,,,,a
ld ld 104 FREQUENCY, f(Hz)
‘-J
16
Figure 3 : Normalised spectral density of
Figure 4 : Plot of A(S&) vs f for various gate
drain current fluctuations of the same device in figure 1 subjected to hot-carrier stressing and isochronal annealing. Measurement bias: V, = 3V, V, = 4OOmV.
biases at V, = 400mV.
A(S,&)
increase with V,. T = 25°C.
is seen to
260
D.S. Ang et al. / Microelectronic Engineering 28 (1995) 257-260
spectral density before and after stress, expressed as a fraction of the pre-stress value. @1d/Z:) increases with applied gate bias Vg, suggesting an inhomogeneous distribution of the stress-induced interfacial oxide traps, with the density increasing from mid bandgap towards the conduction band edge [6]. Oxide traps located at energies above the Si conduction band edge are “pulled down” to the vicinity of the electron quasi-Fermi level at higher gate biases, also contributing to increase in 4Sfd/Z$. Fig. 5 plots differentialcharge pumped per cycle AQcp(0 0. l-l MHz) vs the noise spectral density S,,/Zi at 100 kHz. Excellent correlation between the noise and charge pumping data is observed, lending strong support to the electron tunneling mechanism of channel carriers into interfacial oxide traps as the physical origin of the l/f noise. Similar correlation has been observed in NMOSFET’s stressed at high gate voltage.
-
r*
4.
0
m423K
473K
I
Figure 5 : Plot ofAQcp (@ O.l-1MHz) vs S1,/Z: (@ 1OOkHz) for various annealing temperatures for the same device in figure 1. Good correlation is observed between the l/f noise and charge pumping data.
CONCLUSION
Charge pumping current at different frequencies allows depth profiling of oxide traps. The oxide trap density due to low gate voltage stress decreases with distance from the interface. The oxide traps anneal almost completely at temperatures up to 573 K. Hot-carrier induced interface trap density increases from mid bandgap towards the conduction band edge. Strong correlation between the l/f noise and charge pumping data is demonstrated. REFERENCES
[II PI
R.E. Paulsen and M.E. White, IEEE Trans. Electron Devices, vol. 41, p. 1213, 1994
131
C.H. Ling, Y.T. Yeow and L.K. Ah, IEEE Electron Device Lett., vol. 13, p. 587, 1992
[41
R. Woltjer, A. Hamada and E. Takeda, IEEE Trans. Electron Devices, vol. 40, p. 392, 1993
151
A.J. Lelis, T.R. Oldham, H.E. Boesch, Jr., F.B. McLean, IEEE Trans. Nucl. Sci., vol. 36, p. 1808,1989
S. Christensson, I. Lundstrom and C. Svensson, Solid State Electron., vol. 11, p. 797,1968
ELSEVIER
Microelectronic
Engineering
28 (1995) 257-260
Study of hot-carrier degradation in submicrometer LDD NMOSFET’s from l/f noise and charge pumping current measurements at different temperature anneals D.S. Ang ‘, C.H. Ling” and Y.T. Yeow b ‘Department of Electrical Engineering, National University of Singapore, Singapore 05 1l.* bDepartment of Electrical Engineering, University of Queensland, Brisbane, Australia The l/f noise and variable frequency charge pumping current are used to probe hot-carrier induced oxide and interface traps. A strong correlation between the noise and charge pumping data is observed, confirming carrier capture by near-interface traps as the physical origin of l/f noise in MOS transistors. Results also suggest an oxide trap density that decreases with distance from the interface, and increases with energy from mid bandgap to the Si conduction band edge. 1.
INTRODUCTION
Hot-carrier degradation has been shown to result in charge trapping and oxide and interface trap generation, the damage being localised near the stressed junction. Fundamental issues involve identifying these traps, in space and in energy, and elucidating their effects on the device performance. This paper presents experimental results, based on the application of two of the most sensitive measurement techniques, namely l/f noise and charge pumping current, to the investigation of degradation in submicrometer LDD NMOSFET’s, after hot-carrier stress and after post-stress isochronal anneals. Correlating the results reveals new understanding of the non-homogeneous nature of the generated traps. 2.
EXPERIMENTAL
The test device was a surface channel LDD NMOSFET’s with dimensions 0.8 x 25p2, fabricated from 0.5~ twin-well, n+ polysilicon gate CMOS, nitride spacer technology, with gate oxide thickness &. = 13.5nm, designed for well operation V, = -2V. The device was stressed at V, = 8V, V, = V, = OV and with the gate voltage Vg = 0.6V, a value slightly higher than the threshold voltage V,. 30 min isochronal anneals in moderate vacuum, over the temperature range 373-573K, were carried out on a thermal stage provided by MMR Technologies, Inc. The l/f noise and charge pumping current were monitored after each anneal. The noise measurements were performed using PAR- 113 low noise preamplifier and HP3562A dynamic signal analyser. The charge pumping current was monitored on HP4156A parameter analyzer. The gate pulses were supplied by a HP8 112A signal generator at varying frequencies, and at constant 5V amplitude, 25ns transition times. 3.
RESULTS AND DISCUSSION
Charge pumping measurement, at high gate pulse frequencies, probes interface traps. However, as the frequency is lowered, captured electrons at interface traps have time to tunnel ’Thisworkis supported by a research grant RP930654 and a research scholarship (DSA) from the National University of Singapore. Funding support under the AAECP ASEANAustralia Microelectronics Programme is also acknowledged. 0167.9317/95/$09.50 0 1995 - Elsevier Science B.V. All rights reserved. SSDZ 0167-9317(95)00054-2
D.S. Ang et al. / Microelectronic Engineering 28 (199.5) 257-260
25%
to oxide traps, located near the Si - SO, interface [ 11.Fig. 1 shows the differential charge pumped per cycle AQcpand its annealing behaviour, for an NMOSFET stressed at low gate voltage. AQ, represents the difference in the amount of charge pumped per cycle between two gate pulse frequencies. Fig. 2 depicts (a) a snapshot of the applied gate pulse, and (b) the silicon surface band bending during time period T&2 of the charge pumping measurement. Electrons captured by the fast interface traps D, during the rising edge of the pulse, interact with the slower oxide traps N,,, via a tunneling mechanism, during time period Tin;,,,when the device is biased in inversion. When the device is driven into accumulation, near-interface oxide traps which were previously filled during the inversion cycle, are emptied by reverse tunneling of captured electrons back into the silicon substrate. This results in an additional charge pumping current component contributed by the interfacial oxide traps and leads to an increase in the amount of charge pumped per cycle Q,-&,,, if for low pulse frequencies [ 11.The relation between the electron tunneling time constant z and the distance of the trap from the interface x, is given by [2] ‘I; =
z, exp(m),
(1)
where T,,- lo-” s and a- lo8 cm-‘, typically. Using frequencies differing by a constant ratio thus allows probing of interfacial trap charge over approximately equal depth interval according to
PRE POST 313 423 473 523 573 SrREss ANNEALING TEMPERATURE, T(K)
Figure 1 : Differential charge pumped per cycle, AQc,, under hot-carrier stressing and isochronal anneal. Device is stressed at V, = BV, V, = 0.6V-V,, V, = V, = OV for
Figure 2 : (a) Snapshot of applied gate pulse; (b) silicon surface band bending during time period TJ2 of the charge pumping measurement. Arrows indicate tunneling of
t = 2 x 104s. CP measurement conditions: pulse amplitude = 5V, pulse rise and fall times = 25ns, source/drain grounded.
captured electrons into deeper oxide traps during the inversion cycle, q”;,,.
259
D.S. Ang et al. / Microelectronic Engineering 28 (1995) 257-260
where it is assumed that t, + $ < tp, fi < f2 , x1> q. The differential charge pumped per cycle, which provides an approximate measure of the amount of near-interface oxide traps within an oxide thickness Ax, is then defined as (3) An oxide trap distribution, decreasing with distance from the interface, is clearly evident from the post-stress data, as shown in Fig. 1. This trap profile persists at subsequent temperature anneals. Traps accessible to the lo/100 kHz gate pulse are completely annealed at the highest temperature of 573 K, however, some residual traps probed by the 0.1/l MHz gate pulse survive. This result suggests an oxide trap density, reported to be hole traps for the low V, stress [3], that is highest near the Si - SiO, interface, where maximum lattice strain exists, in contrast to a uniform oxide trap density assumed by some authors [4]. Annealing shows two distinct rates. Between 373K and 423K, a higher annealing rate is observed for traps nearer the interface. It is speculated that a larger built-in electric field due to the trapped holes, nearer the interface, enhances annealing, proposed to be due to electron tunneling to E’ centers, resulting in bond reformation or more probably bond compensation [5]. Above 423K, comparable annealing rates are observed, attributed to the thermal detrapping of holes [5]. Fig. 3 depicts the low frequency l/f noise characteristics. An average increase of about 8 dB is observed for the particular stress condition. Annealing leads to the recovery of the noise level to its pre-stress value, consistent with the removal of the interfacial oxide traps, observed in Fig. 1. Fig. 4 illustrates the differential change in noise level for different gate bias. We define the differential spectral density of drain curmnt fluctuations A($&) as the difference in the
16
10’
ld
I@
la’
FREQUENCY, f(Hz)
16
o* ‘...,.A IO0 10'
0 .
. *
.
.
“,“*
--
-
,,,,,a
ld ld 104 FREQUENCY, f(Hz)
‘-J
16
Figure 3 : Normalised spectral density of
Figure 4 : Plot of A(S&) vs f for various gate
drain current fluctuations of the same device in figure 1 subjected to hot-carrier stressing and isochronal annealing. Measurement bias: V, = 3V, V, = 4OOmV.
biases at V, = 400mV.
A(S,&)
increase with V,. T = 25°C.
is seen to
260
D.S. Ang et al. / Microelectronic Engineering 28 (1995) 257-260
spectral density before and after stress, expressed as a fraction of the pre-stress value. @1d/Z:) increases with applied gate bias Vg, suggesting an inhomogeneous distribution of the stress-induced interfacial oxide traps, with the density increasing from mid bandgap towards the conduction band edge [6]. Oxide traps located at energies above the Si conduction band edge are “pulled down” to the vicinity of the electron quasi-Fermi level at higher gate biases, also contributing to increase in 4Sfd/Z$. Fig. 5 plots differentialcharge pumped per cycle AQcp(0 0. l-l MHz) vs the noise spectral density S,,/Zi at 100 kHz. Excellent correlation between the noise and charge pumping data is observed, lending strong support to the electron tunneling mechanism of channel carriers into interfacial oxide traps as the physical origin of the l/f noise. Similar correlation has been observed in NMOSFET’s stressed at high gate voltage.
-
r*
4.
0
m423K
473K
I
Figure 5 : Plot ofAQcp (@ O.l-1MHz) vs S1,/Z: (@ 1OOkHz) for various annealing temperatures for the same device in figure 1. Good correlation is observed between the l/f noise and charge pumping data.
CONCLUSION
Charge pumping current at different frequencies allows depth profiling of oxide traps. The oxide trap density due to low gate voltage stress decreases with distance from the interface. The oxide traps anneal almost completely at temperatures up to 573 K. Hot-carrier induced interface trap density increases from mid bandgap towards the conduction band edge. Strong correlation between the l/f noise and charge pumping data is demonstrated. REFERENCES
[II PI
R.E. Paulsen and M.E. White, IEEE Trans. Electron Devices, vol. 41, p. 1213, 1994
131
C.H. Ling, Y.T. Yeow and L.K. Ah, IEEE Electron Device Lett., vol. 13, p. 587, 1992
[41
R. Woltjer, A. Hamada and E. Takeda, IEEE Trans. Electron Devices, vol. 40, p. 392, 1993
151
A.J. Lelis, T.R. Oldham, H.E. Boesch, Jr., F.B. McLean, IEEE Trans. Nucl. Sci., vol. 36, p. 1808,1989
S. Christensson, I. Lundstrom and C. Svensson, Solid State Electron., vol. 11, p. 797,1968