Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Microelectron. Reliab., Vol. 35, No. 5, pp. 821-826, 1995 Copyright © 1995 ElsevierScienceLtd Printed in Great Britain.All rights reserved 0026-2714/95 $9.50+.00

Pergamon 0026-2714(94)00118-9

STUDY OF HOT ELECTRON DEGRADATION IN SUBMICROMETER GATE LENGTH MOS TRANSISTOR FABRICATED WITH SELECTIVELY DOPED SUBSTRATE ENGINEERING P. N. ANDHARE, R. K, NAHAR and S. CHANDRA Central Electronics Engineering Research Institute, Pilani 333 031, India (Received for publication 30 July 1994) Abstract--Investigations are made on the performance and hot electron degradation of sub-gm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-gm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-gin transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-gm MOS transistors.

INTRODUCTION Development of sub-p.m gate length transistor occupies a major portion of the overall development of sub-gm technology. This is so because substantial process characterisation of sub-gm technology can be done by characterisation of a transistor having a sub-I~m gate length, though other dimensions of the transistor may not be consistent with the gate length. These characterisations include optimisation of performance related parameters (like speed of the device, drive current capability), and reliability related parameters (like hot electron degradation, time dependant oxide breakdown). This approach has given rise to the principle of selective scaling, wherein only gate dimensions are scaled down to a futuristic technology, retaining other dimensions pertaining to the present technology. Such an approach has been used to enhance system performance and has resulted in many techniques of defining sub-gin gate length only by unconventional techniques using 5 gm optical photolithography without taking recourse to the costly and sophisticated electron beam photolithography [1, 2]. We have developed a new technique to delineate sub-gin gate length, which is described in this paper. There are several problems associated with high electric field that occur in short channel devices [3-9]. Hot electron degradation (HED) is one of them. HED imposes limits on VLSI scaling and device reliability. Different techniques of drain engineering have been investigated to alleviate HED effects in scaled MOSFETs. The lightly doped drain L D D structures have been preferred for drain engineering in submicron transistors. There are several publications which report the various forms of LDD structures [9] 821

implemented to improve the performance and device reliability. Some recent papers discuss the limitations of LDD structures for deep sub-gm devices [9]. Extensive work has also been done on the use of deep punch through implant [DPI] process to prevent punch through phenomenon. This led to the development of another selectively doped substrate (SDS) engineering technique known as diffusion self-aligned halo effect [7]. However, study on HED of sub-gm transistors with SDS and DPI structures is not available in the published literature. This is important because there are some basic differences between SDS and DPI techniques which can have significant potential impact on technological options and process optimisation in the sub-gm arena. EXPERIMENTAL The cross section of a MOS transistor with SDS structure and DPI structure is shown in Fig. 1. The basic difference as illustrated in the figure is that DPI structures require two implants, a low energy implant to adjust the threshold voltage and a high energy implant to prevent punch through. In SDS structures a single implant near S/D regions gives the desired performance improvement. In this study the sub-lam gate length MOS transistors were fabricated on boron doped Si wafers of 4 - 6 ohm-cm resistivity. After standard IC cleaning thermal oxide of about 0.6 gm was grown. In order to delineate the sub-gm gate length patterns we employed subtractive lithography technique [10]. Briefly the procedure is as follows: first a line is defined on positive resist using a bright field mask with a 6 gm wide line. After development the wafer is baked at 90°C and a second dark field

822

P.N. ANDHAREet MOS TRANSITOR STRUCTURE

G

s

NI *

I ]22222222222221 P -

D N"

]

subsfrafe

WITH DEEP PUNCH-THROUGH (DPI) UNDER GATE REGION

i N.I

r-~..., p . . / " ~

al.

were processed and found reproducable. Typical variation of line width across a wafer measured on a processed planar wafer is shown in the form of an histogram in Fig. 3. The typical process parameters used in the fabrication of sub-gm transistors are: S/D implant (phosphorus) 5 x 10 ~s a cm - 2 (40 KeV), gate oxide thickness 300 •, field oxide thickness 6000/~,, field implant (boron) 5 x 1 0 ] 3 a c m 2 (150KeV), SDS and DPI implants (boron) 10 ~3 a c m - 2 (90 KeV) and enhancement implant (boron) 9 x 1012 a c m 2 (50 KEY). A flow chart of the process sequence is given in Fig. 4. It may be mentioned here that this technique is useful in small research and development centers and universities where sub-gm feature size masks are not easily available. Electron mobility, substrate sensitivity index, inverse subthreshold slope and substrate current were

' N" GATE LENGTH

P - substrate . . . . . . . . . . . . . . . .

O0 -~ . . . . . . . . . . . . . . . . . . . . .

WITH SELECTIVELY DOPED SUBSTRATE (SOS) NEAR SOURCE AND DRAIN REGIONS

~2Se .* 750 oo

Fig. l, Cross section of MOS transistor with deep punch through (DPI) structure and selectively doped substrate (SDS) structure. mask is used to subtract a 51am wide line from patterned 6 gm line. After resist development the wafer is subjected to wet etch of oxide using BHF. By controlling the exposure time and etch time 0,5 lain gate length line is obtained. This is measured on SEM as shown in Fig. 2. With this process several batches

I

2

1

~

6

7

8

9

I

DIFFERENT TEST SITES ON SLICE V 0 0 3

Fig. 3. Histogram of gate length defined by the subtractive technique on a planar wafer.

Fig. 2. Scanning electron microscope of a sub-~tm line defined by subtractive photolithography.

Hot electron degradations

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823

1st OXIDATION

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FIELD OXIDATION

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3x10~ a/cmz at 120KeV

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5x10Is- 60KeV Ph

BLANKET OXIDE ETCH TO REMOVE

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SUBTRACTIVE PHOTOLITHOGRAPHY TO DEFINE SUBMICRONGATE

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30MIN at 500°c IN DRY NITROGEN Fig. 4. Flow chart of the process sequence for the fabrication of sub-lamgate length MOS transistor. measured. Hot electron degradations were monitored by measuring the pre-stress and post-stress current between source and drain in linear region. The stressing was done at gate voltage 2.5 volts (V) and source drain voltage 5 V for a period of 30 min.

RESULTS AND DISCUSSIONS The device parameters obtained on sub-tam transistors fabricated with SDS and DPI techniques are compared in Table 1. We obtained an increase in the mobility and reduction in substrate sensitivity with SDS structures

Table I. Submicrometer gate length MOS transistor parameters obtained with SDS and DPI processes Device parameter Electron mobility (cm'/V.S) Inverse subthreshold slope (mv decade- t) Substrate sensitivity factor DIBL (AVth/AVds)

SDS process 235

DPI process 209 200

200 1.9 0.03

2.1 0.05

compared to DPI structures. This is an advantage of SDS engineering. This structure has the ability to increase the enhancement threshold voltage. Therefore a much smaller shallow enhancement implant should be adequate to obtain a specified threshold voltage compared to DPI technique. This affects electron mobility and substrate sensitivity index of the transistor as both of them are influenced by the impurity concentration under the gate. So SDS structure gives higher mobility and lower substrate sensitivity for the transistors as observed. The HED observed for SDS and DPI techniques are shown in Fig. 5. As shown in the figure the data measured at different sites on a wafer show very small reduction in current after stressing in SDS structures whereas DPI structures show a substantial reduction in the current. The substrate current measured on these structures is shown in Fig. 6. The data show a much smaller substrate current [an average of about 1500 nA] for DSA whereas DPI structures show an average of about 3000 nA. The substrate current is almost reduced to half with SDS structures in sub-tam transistors. This is attributed to the nature of profile in the two cases. For identical dose and energy of implant, SDS produces a graded impurity profile in the lateral direction whereas DPI produces a junction closer to step junction. This effectively means that with SDS technique drain field in the transistor

824

P.N. ANDHAREet al.

DPI

SDS

I~ after stress Id before stress

Punch through + Enhancement portion

1.0

"0.8

"0.6

.03,

'0.2

--

chip sites

Fig. 5. Hot electron degradation of sub-lam MOS transistors with SDS and DP[ structures. SDS

OPI Punch through + Enhancement portion

IM (nA)

"SO00 .4000 -3000

"2000

.1000 1 /,

1

3

t,

5

6 7

8

10

chip sites Fig. 6. Peak substrate current of sub-pro transistors with SDS and DPI structures.

will be smaller compared to DPI technique. Therefore the substrate current is reduced, as observed. Figure 7 shows the effect of low doping under the gate on substrate current measured on submicron transistors fabricated with SDS process and low

enhancement conventional process. It is observed that I sub peak for the DSA process occurs at higher voltage whereas the peak occurs at much lower voltage for the conventional process. This shows the superior surface punchthrough property of the SDS process.

Hot electron degradations

825

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2000 L

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= 0.6 Micron = -O.5V : +5.OV

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1500

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500

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Fig. 7. Substrate current and gate voltage characteristics for SDS and conventional low enhancement processes W/L = 16/0.6.

Y

X

D

Fig. 8. Output waveform of a ring oscillator fabricated using substractive lithography and SDS process measured at Vdd = 4.8 V and, ldd = 6.4 mA × axis is 50 ns/div and Y axis is 50 mV/div.

826

P.N. ANDHAREet al.

In order to examine the usefulness of the process we fabricated a ring oscillator. The o u t p u t waveforms are shown in Fig. 8. In this case the transistor gate length was 0.6 lam. The voltage Vdd = 4.8 V a n d current l d d = 6.4 mA. A delay per invertor o b t a i n e d was a b o u t 1.6 ns.

CONCLUSIONS SDS process improves the transistor performance a n d reduces hot electron d e g r a d a t i o n , s u b s t r a t e current a n d surface p u n c h t h r o u g h in sub-rtm M O S transistors. The novel technique of delineating submicron feature size is simple a n d easily reproducable to fabricate discrete transistors a n d simple circuits. This should be attractive for those studying the sub-lam process technology a n d device physics with limited facilities. Acknowledgements--The authors would like to thank Dr. P.

D. Vyas, O. P. Wadhawan and other members of the device processing facility for their help in this work.

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2. J. Chung, M. C. Jeng, J. E. Moon, A. T. Wu, T. Y. Chan, P. K. Ko and C. Hu, Deep submicrometer MOS device fabrication using a photoresist ashing technique, IEEE Electron Device Lett. EDL-9(4), 186 (1988). 3. R. R. Troutman, VLSI Limitation from Drain Induced Barrier Lowering, IEEE Trans. Electron Devices ED-26, 461 (1979). 4. L. Risch, C. Werner, W. Muller and A. W. Wieder, Deep implant 1 tam MOSFET structure with improved threshold control for VLSI Circuitry, IEEE Trans. Electron Devices, ED-29, 601 (1982). 5. Isao Okhura, Osamu Tomisawa, Masashi Ohmori and Takao Nakano, Electrical characteristics of a DSA MOS Transistor with a fine structure, IEEE Trans. Electron Devices ED-26(4), 430 (1979). 6. S. Ogura, C. F. Codella, N. Rovedo, J. F. Shepard and J. Riseman, A half micron MOSFET using double implanted LDD, I E D M Tech. Dig. 718 (1982). 7. C. F. Codella and S. Ogura, Holo doping effects in submicron DILDD device Design, I E D M Tech. Dig. 230 (1985). 8. T. N. Buti, S. Ogura, N. Rovedo and K. Tobimatsu, A new symmetrical Holo source GOLD drain (HS GOLD) deep sub half micrometer n-MOSFET design for reliability and performance, IEEE Trans. Electron Devices, ED-38, 1757 (1991). 9. A. F. Tasch, H. Shin, T. J. Bordelon and C. M. Maziar, Limitation of LDD types of structures in deep submicrometer MOS technology, IEEE Electron Device Lett. EDL-I1, 517-519 (1990). 10. P. N. Andhare, R. K. Nahar, S. Chandra, N. M. Devashrayee, R. N. Soni, B. C. Pathak, G. S. Virdi, O. P. Wadhawan and W. S. Khokle, Development of a submicron gate length MOS transistor, International Workshop of Semiconductor Devices, New Delhi 97 (1991).